185b4fab2SMaxime COQUELIN /* 285b4fab2SMaxime COQUELIN * Copyright (C) 2013 STMicroelectronics 385b4fab2SMaxime COQUELIN * 485b4fab2SMaxime COQUELIN * I2C master mode controller driver, used in STMicroelectronics devices. 585b4fab2SMaxime COQUELIN * 685b4fab2SMaxime COQUELIN * Author: Maxime Coquelin <maxime.coquelin@st.com> 785b4fab2SMaxime COQUELIN * 885b4fab2SMaxime COQUELIN * This program is free software; you can redistribute it and/or modify 985b4fab2SMaxime COQUELIN * it under the terms of the GNU General Public License version 2, as 1085b4fab2SMaxime COQUELIN * published by the Free Software Foundation. 1185b4fab2SMaxime COQUELIN */ 1285b4fab2SMaxime COQUELIN 1385b4fab2SMaxime COQUELIN #include <linux/module.h> 1485b4fab2SMaxime COQUELIN #include <linux/platform_device.h> 1585b4fab2SMaxime COQUELIN #include <linux/i2c.h> 1685b4fab2SMaxime COQUELIN #include <linux/clk.h> 1785b4fab2SMaxime COQUELIN #include <linux/io.h> 1885b4fab2SMaxime COQUELIN #include <linux/delay.h> 1985b4fab2SMaxime COQUELIN #include <linux/interrupt.h> 2085b4fab2SMaxime COQUELIN #include <linux/err.h> 2185b4fab2SMaxime COQUELIN #include <linux/of.h> 2285b4fab2SMaxime COQUELIN #include <linux/of_address.h> 2385b4fab2SMaxime COQUELIN #include <linux/of_irq.h> 2485b4fab2SMaxime COQUELIN 2585b4fab2SMaxime COQUELIN /* SSC registers */ 2685b4fab2SMaxime COQUELIN #define SSC_BRG 0x000 2785b4fab2SMaxime COQUELIN #define SSC_TBUF 0x004 2885b4fab2SMaxime COQUELIN #define SSC_RBUF 0x008 2985b4fab2SMaxime COQUELIN #define SSC_CTL 0x00C 3085b4fab2SMaxime COQUELIN #define SSC_IEN 0x010 3185b4fab2SMaxime COQUELIN #define SSC_STA 0x014 3285b4fab2SMaxime COQUELIN #define SSC_I2C 0x018 3385b4fab2SMaxime COQUELIN #define SSC_SLAD 0x01C 3485b4fab2SMaxime COQUELIN #define SSC_REP_START_HOLD 0x020 3585b4fab2SMaxime COQUELIN #define SSC_START_HOLD 0x024 3685b4fab2SMaxime COQUELIN #define SSC_REP_START_SETUP 0x028 3785b4fab2SMaxime COQUELIN #define SSC_DATA_SETUP 0x02C 3885b4fab2SMaxime COQUELIN #define SSC_STOP_SETUP 0x030 3985b4fab2SMaxime COQUELIN #define SSC_BUS_FREE 0x034 4085b4fab2SMaxime COQUELIN #define SSC_TX_FSTAT 0x038 4185b4fab2SMaxime COQUELIN #define SSC_RX_FSTAT 0x03C 4285b4fab2SMaxime COQUELIN #define SSC_PRE_SCALER_BRG 0x040 4385b4fab2SMaxime COQUELIN #define SSC_CLR 0x080 4485b4fab2SMaxime COQUELIN #define SSC_NOISE_SUPP_WIDTH 0x100 4585b4fab2SMaxime COQUELIN #define SSC_PRSCALER 0x104 4685b4fab2SMaxime COQUELIN #define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108 4785b4fab2SMaxime COQUELIN #define SSC_PRSCALER_DATAOUT 0x10c 4885b4fab2SMaxime COQUELIN 4985b4fab2SMaxime COQUELIN /* SSC Control */ 5085b4fab2SMaxime COQUELIN #define SSC_CTL_DATA_WIDTH_9 0x8 5185b4fab2SMaxime COQUELIN #define SSC_CTL_DATA_WIDTH_MSK 0xf 5285b4fab2SMaxime COQUELIN #define SSC_CTL_BM 0xf 5385b4fab2SMaxime COQUELIN #define SSC_CTL_HB BIT(4) 5485b4fab2SMaxime COQUELIN #define SSC_CTL_PH BIT(5) 5585b4fab2SMaxime COQUELIN #define SSC_CTL_PO BIT(6) 5685b4fab2SMaxime COQUELIN #define SSC_CTL_SR BIT(7) 5785b4fab2SMaxime COQUELIN #define SSC_CTL_MS BIT(8) 5885b4fab2SMaxime COQUELIN #define SSC_CTL_EN BIT(9) 5985b4fab2SMaxime COQUELIN #define SSC_CTL_LPB BIT(10) 6085b4fab2SMaxime COQUELIN #define SSC_CTL_EN_TX_FIFO BIT(11) 6185b4fab2SMaxime COQUELIN #define SSC_CTL_EN_RX_FIFO BIT(12) 6285b4fab2SMaxime COQUELIN #define SSC_CTL_EN_CLST_RX BIT(13) 6385b4fab2SMaxime COQUELIN 6485b4fab2SMaxime COQUELIN /* SSC Interrupt Enable */ 6585b4fab2SMaxime COQUELIN #define SSC_IEN_RIEN BIT(0) 6685b4fab2SMaxime COQUELIN #define SSC_IEN_TIEN BIT(1) 6785b4fab2SMaxime COQUELIN #define SSC_IEN_TEEN BIT(2) 6885b4fab2SMaxime COQUELIN #define SSC_IEN_REEN BIT(3) 6985b4fab2SMaxime COQUELIN #define SSC_IEN_PEEN BIT(4) 7085b4fab2SMaxime COQUELIN #define SSC_IEN_AASEN BIT(6) 7185b4fab2SMaxime COQUELIN #define SSC_IEN_STOPEN BIT(7) 7285b4fab2SMaxime COQUELIN #define SSC_IEN_ARBLEN BIT(8) 7385b4fab2SMaxime COQUELIN #define SSC_IEN_NACKEN BIT(10) 7485b4fab2SMaxime COQUELIN #define SSC_IEN_REPSTRTEN BIT(11) 7585b4fab2SMaxime COQUELIN #define SSC_IEN_TX_FIFO_HALF BIT(12) 7685b4fab2SMaxime COQUELIN #define SSC_IEN_RX_FIFO_HALF_FULL BIT(14) 7785b4fab2SMaxime COQUELIN 7885b4fab2SMaxime COQUELIN /* SSC Status */ 7985b4fab2SMaxime COQUELIN #define SSC_STA_RIR BIT(0) 8085b4fab2SMaxime COQUELIN #define SSC_STA_TIR BIT(1) 8185b4fab2SMaxime COQUELIN #define SSC_STA_TE BIT(2) 8285b4fab2SMaxime COQUELIN #define SSC_STA_RE BIT(3) 8385b4fab2SMaxime COQUELIN #define SSC_STA_PE BIT(4) 8485b4fab2SMaxime COQUELIN #define SSC_STA_CLST BIT(5) 8585b4fab2SMaxime COQUELIN #define SSC_STA_AAS BIT(6) 8685b4fab2SMaxime COQUELIN #define SSC_STA_STOP BIT(7) 8785b4fab2SMaxime COQUELIN #define SSC_STA_ARBL BIT(8) 8885b4fab2SMaxime COQUELIN #define SSC_STA_BUSY BIT(9) 8985b4fab2SMaxime COQUELIN #define SSC_STA_NACK BIT(10) 9085b4fab2SMaxime COQUELIN #define SSC_STA_REPSTRT BIT(11) 9185b4fab2SMaxime COQUELIN #define SSC_STA_TX_FIFO_HALF BIT(12) 9285b4fab2SMaxime COQUELIN #define SSC_STA_TX_FIFO_FULL BIT(13) 9385b4fab2SMaxime COQUELIN #define SSC_STA_RX_FIFO_HALF BIT(14) 9485b4fab2SMaxime COQUELIN 9585b4fab2SMaxime COQUELIN /* SSC I2C Control */ 9685b4fab2SMaxime COQUELIN #define SSC_I2C_I2CM BIT(0) 9785b4fab2SMaxime COQUELIN #define SSC_I2C_STRTG BIT(1) 9885b4fab2SMaxime COQUELIN #define SSC_I2C_STOPG BIT(2) 9985b4fab2SMaxime COQUELIN #define SSC_I2C_ACKG BIT(3) 10085b4fab2SMaxime COQUELIN #define SSC_I2C_AD10 BIT(4) 10185b4fab2SMaxime COQUELIN #define SSC_I2C_TXENB BIT(5) 10285b4fab2SMaxime COQUELIN #define SSC_I2C_REPSTRTG BIT(11) 10385b4fab2SMaxime COQUELIN #define SSC_I2C_SLAVE_DISABLE BIT(12) 10485b4fab2SMaxime COQUELIN 10585b4fab2SMaxime COQUELIN /* SSC Tx FIFO Status */ 10685b4fab2SMaxime COQUELIN #define SSC_TX_FSTAT_STATUS 0x07 10785b4fab2SMaxime COQUELIN 10885b4fab2SMaxime COQUELIN /* SSC Rx FIFO Status */ 10985b4fab2SMaxime COQUELIN #define SSC_RX_FSTAT_STATUS 0x07 11085b4fab2SMaxime COQUELIN 11185b4fab2SMaxime COQUELIN /* SSC Clear bit operation */ 11285b4fab2SMaxime COQUELIN #define SSC_CLR_SSCAAS BIT(6) 11385b4fab2SMaxime COQUELIN #define SSC_CLR_SSCSTOP BIT(7) 11485b4fab2SMaxime COQUELIN #define SSC_CLR_SSCARBL BIT(8) 11585b4fab2SMaxime COQUELIN #define SSC_CLR_NACK BIT(10) 11685b4fab2SMaxime COQUELIN #define SSC_CLR_REPSTRT BIT(11) 11785b4fab2SMaxime COQUELIN 11885b4fab2SMaxime COQUELIN /* SSC Clock Prescaler */ 11985b4fab2SMaxime COQUELIN #define SSC_PRSC_VALUE 0x0f 12085b4fab2SMaxime COQUELIN 12185b4fab2SMaxime COQUELIN 12285b4fab2SMaxime COQUELIN #define SSC_TXFIFO_SIZE 0x8 12385b4fab2SMaxime COQUELIN #define SSC_RXFIFO_SIZE 0x8 12485b4fab2SMaxime COQUELIN 12585b4fab2SMaxime COQUELIN enum st_i2c_mode { 12685b4fab2SMaxime COQUELIN I2C_MODE_STANDARD, 12785b4fab2SMaxime COQUELIN I2C_MODE_FAST, 12885b4fab2SMaxime COQUELIN I2C_MODE_END, 12985b4fab2SMaxime COQUELIN }; 13085b4fab2SMaxime COQUELIN 13185b4fab2SMaxime COQUELIN /** 13285b4fab2SMaxime COQUELIN * struct st_i2c_timings - per-Mode tuning parameters 13385b4fab2SMaxime COQUELIN * @rate: I2C bus rate 13485b4fab2SMaxime COQUELIN * @rep_start_hold: I2C repeated start hold time requirement 13585b4fab2SMaxime COQUELIN * @rep_start_setup: I2C repeated start set up time requirement 13685b4fab2SMaxime COQUELIN * @start_hold: I2C start hold time requirement 13785b4fab2SMaxime COQUELIN * @data_setup_time: I2C data set up time requirement 13885b4fab2SMaxime COQUELIN * @stop_setup_time: I2C stop set up time requirement 13985b4fab2SMaxime COQUELIN * @bus_free_time: I2C bus free time requirement 14085b4fab2SMaxime COQUELIN * @sda_pulse_min_limit: I2C SDA pulse mini width limit 14185b4fab2SMaxime COQUELIN */ 14285b4fab2SMaxime COQUELIN struct st_i2c_timings { 14385b4fab2SMaxime COQUELIN u32 rate; 14485b4fab2SMaxime COQUELIN u32 rep_start_hold; 14585b4fab2SMaxime COQUELIN u32 rep_start_setup; 14685b4fab2SMaxime COQUELIN u32 start_hold; 14785b4fab2SMaxime COQUELIN u32 data_setup_time; 14885b4fab2SMaxime COQUELIN u32 stop_setup_time; 14985b4fab2SMaxime COQUELIN u32 bus_free_time; 15085b4fab2SMaxime COQUELIN u32 sda_pulse_min_limit; 15185b4fab2SMaxime COQUELIN }; 15285b4fab2SMaxime COQUELIN 15385b4fab2SMaxime COQUELIN /** 15485b4fab2SMaxime COQUELIN * struct st_i2c_client - client specific data 15585b4fab2SMaxime COQUELIN * @addr: 8-bit slave addr, including r/w bit 15685b4fab2SMaxime COQUELIN * @count: number of bytes to be transfered 15785b4fab2SMaxime COQUELIN * @xfered: number of bytes already transferred 15885b4fab2SMaxime COQUELIN * @buf: data buffer 15985b4fab2SMaxime COQUELIN * @result: result of the transfer 16085b4fab2SMaxime COQUELIN * @stop: last I2C msg to be sent, i.e. STOP to be generated 16185b4fab2SMaxime COQUELIN */ 16285b4fab2SMaxime COQUELIN struct st_i2c_client { 16385b4fab2SMaxime COQUELIN u8 addr; 16485b4fab2SMaxime COQUELIN u32 count; 16585b4fab2SMaxime COQUELIN u32 xfered; 16685b4fab2SMaxime COQUELIN u8 *buf; 16785b4fab2SMaxime COQUELIN int result; 16885b4fab2SMaxime COQUELIN bool stop; 16985b4fab2SMaxime COQUELIN }; 17085b4fab2SMaxime COQUELIN 17185b4fab2SMaxime COQUELIN /** 17285b4fab2SMaxime COQUELIN * struct st_i2c_dev - private data of the controller 17385b4fab2SMaxime COQUELIN * @adap: I2C adapter for this controller 17485b4fab2SMaxime COQUELIN * @dev: device for this controller 17585b4fab2SMaxime COQUELIN * @base: virtual memory area 17685b4fab2SMaxime COQUELIN * @complete: completion of I2C message 17785b4fab2SMaxime COQUELIN * @irq: interrupt line for th controller 17885b4fab2SMaxime COQUELIN * @clk: hw ssc block clock 17985b4fab2SMaxime COQUELIN * @mode: I2C mode of the controller. Standard or Fast only supported 18085b4fab2SMaxime COQUELIN * @scl_min_width_us: SCL line minimum pulse width in us 18185b4fab2SMaxime COQUELIN * @sda_min_width_us: SDA line minimum pulse width in us 18285b4fab2SMaxime COQUELIN * @client: I2C transfert information 18385b4fab2SMaxime COQUELIN * @busy: I2C transfer on-going 18485b4fab2SMaxime COQUELIN */ 18585b4fab2SMaxime COQUELIN struct st_i2c_dev { 18685b4fab2SMaxime COQUELIN struct i2c_adapter adap; 18785b4fab2SMaxime COQUELIN struct device *dev; 18885b4fab2SMaxime COQUELIN void __iomem *base; 18985b4fab2SMaxime COQUELIN struct completion complete; 19085b4fab2SMaxime COQUELIN int irq; 19185b4fab2SMaxime COQUELIN struct clk *clk; 19285b4fab2SMaxime COQUELIN int mode; 19385b4fab2SMaxime COQUELIN u32 scl_min_width_us; 19485b4fab2SMaxime COQUELIN u32 sda_min_width_us; 19585b4fab2SMaxime COQUELIN struct st_i2c_client client; 19685b4fab2SMaxime COQUELIN bool busy; 19785b4fab2SMaxime COQUELIN }; 19885b4fab2SMaxime COQUELIN 19985b4fab2SMaxime COQUELIN static inline void st_i2c_set_bits(void __iomem *reg, u32 mask) 20085b4fab2SMaxime COQUELIN { 20185b4fab2SMaxime COQUELIN writel_relaxed(readl_relaxed(reg) | mask, reg); 20285b4fab2SMaxime COQUELIN } 20385b4fab2SMaxime COQUELIN 20485b4fab2SMaxime COQUELIN static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask) 20585b4fab2SMaxime COQUELIN { 20685b4fab2SMaxime COQUELIN writel_relaxed(readl_relaxed(reg) & ~mask, reg); 20785b4fab2SMaxime COQUELIN } 20885b4fab2SMaxime COQUELIN 20985b4fab2SMaxime COQUELIN /* From I2C Specifications v0.5 */ 21085b4fab2SMaxime COQUELIN static struct st_i2c_timings i2c_timings[] = { 21185b4fab2SMaxime COQUELIN [I2C_MODE_STANDARD] = { 21285b4fab2SMaxime COQUELIN .rate = 100000, 21385b4fab2SMaxime COQUELIN .rep_start_hold = 4000, 21485b4fab2SMaxime COQUELIN .rep_start_setup = 4700, 21585b4fab2SMaxime COQUELIN .start_hold = 4000, 21685b4fab2SMaxime COQUELIN .data_setup_time = 250, 21785b4fab2SMaxime COQUELIN .stop_setup_time = 4000, 21885b4fab2SMaxime COQUELIN .bus_free_time = 4700, 21985b4fab2SMaxime COQUELIN }, 22085b4fab2SMaxime COQUELIN [I2C_MODE_FAST] = { 22185b4fab2SMaxime COQUELIN .rate = 400000, 22285b4fab2SMaxime COQUELIN .rep_start_hold = 600, 22385b4fab2SMaxime COQUELIN .rep_start_setup = 600, 22485b4fab2SMaxime COQUELIN .start_hold = 600, 22585b4fab2SMaxime COQUELIN .data_setup_time = 100, 22685b4fab2SMaxime COQUELIN .stop_setup_time = 600, 22785b4fab2SMaxime COQUELIN .bus_free_time = 1300, 22885b4fab2SMaxime COQUELIN }, 22985b4fab2SMaxime COQUELIN }; 23085b4fab2SMaxime COQUELIN 23185b4fab2SMaxime COQUELIN static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev) 23285b4fab2SMaxime COQUELIN { 23385b4fab2SMaxime COQUELIN int count, i; 23485b4fab2SMaxime COQUELIN 23585b4fab2SMaxime COQUELIN /* 23685b4fab2SMaxime COQUELIN * Counter only counts up to 7 but fifo size is 8... 23785b4fab2SMaxime COQUELIN * When fifo is full, counter is 0 and RIR bit of status register is 23885b4fab2SMaxime COQUELIN * set 23985b4fab2SMaxime COQUELIN */ 24085b4fab2SMaxime COQUELIN if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) 24185b4fab2SMaxime COQUELIN count = SSC_RXFIFO_SIZE; 24285b4fab2SMaxime COQUELIN else 24385b4fab2SMaxime COQUELIN count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & 24485b4fab2SMaxime COQUELIN SSC_RX_FSTAT_STATUS; 24585b4fab2SMaxime COQUELIN 24685b4fab2SMaxime COQUELIN for (i = 0; i < count; i++) 24785b4fab2SMaxime COQUELIN readl_relaxed(i2c_dev->base + SSC_RBUF); 24885b4fab2SMaxime COQUELIN } 24985b4fab2SMaxime COQUELIN 25085b4fab2SMaxime COQUELIN static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev) 25185b4fab2SMaxime COQUELIN { 25285b4fab2SMaxime COQUELIN /* 25385b4fab2SMaxime COQUELIN * FIFO needs to be emptied before reseting the IP, 25485b4fab2SMaxime COQUELIN * else the controller raises a BUSY error. 25585b4fab2SMaxime COQUELIN */ 25685b4fab2SMaxime COQUELIN st_i2c_flush_rx_fifo(i2c_dev); 25785b4fab2SMaxime COQUELIN 25885b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 25985b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 26085b4fab2SMaxime COQUELIN } 26185b4fab2SMaxime COQUELIN 26285b4fab2SMaxime COQUELIN /** 26385b4fab2SMaxime COQUELIN * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings 26485b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 26585b4fab2SMaxime COQUELIN */ 26685b4fab2SMaxime COQUELIN static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev) 26785b4fab2SMaxime COQUELIN { 26885b4fab2SMaxime COQUELIN unsigned long rate; 26985b4fab2SMaxime COQUELIN u32 val, ns_per_clk; 27085b4fab2SMaxime COQUELIN struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode]; 27185b4fab2SMaxime COQUELIN 27285b4fab2SMaxime COQUELIN st_i2c_soft_reset(i2c_dev); 27385b4fab2SMaxime COQUELIN 27485b4fab2SMaxime COQUELIN val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL | 27585b4fab2SMaxime COQUELIN SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP; 27685b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_CLR); 27785b4fab2SMaxime COQUELIN 27885b4fab2SMaxime COQUELIN /* SSC Control register setup */ 27985b4fab2SMaxime COQUELIN val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9; 28085b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_CTL); 28185b4fab2SMaxime COQUELIN 28285b4fab2SMaxime COQUELIN rate = clk_get_rate(i2c_dev->clk); 28385b4fab2SMaxime COQUELIN ns_per_clk = 1000000000 / rate; 28485b4fab2SMaxime COQUELIN 28585b4fab2SMaxime COQUELIN /* Baudrate */ 28685b4fab2SMaxime COQUELIN val = rate / (2 * t->rate); 28785b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_BRG); 28885b4fab2SMaxime COQUELIN 28985b4fab2SMaxime COQUELIN /* Pre-scaler baudrate */ 29085b4fab2SMaxime COQUELIN writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); 29185b4fab2SMaxime COQUELIN 29285b4fab2SMaxime COQUELIN /* Enable I2C mode */ 29385b4fab2SMaxime COQUELIN writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); 29485b4fab2SMaxime COQUELIN 29585b4fab2SMaxime COQUELIN /* Repeated start hold time */ 29685b4fab2SMaxime COQUELIN val = t->rep_start_hold / ns_per_clk; 29785b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); 29885b4fab2SMaxime COQUELIN 29985b4fab2SMaxime COQUELIN /* Repeated start set up time */ 30085b4fab2SMaxime COQUELIN val = t->rep_start_setup / ns_per_clk; 30185b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); 30285b4fab2SMaxime COQUELIN 30385b4fab2SMaxime COQUELIN /* Start hold time */ 30485b4fab2SMaxime COQUELIN val = t->start_hold / ns_per_clk; 30585b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); 30685b4fab2SMaxime COQUELIN 30785b4fab2SMaxime COQUELIN /* Data set up time */ 30885b4fab2SMaxime COQUELIN val = t->data_setup_time / ns_per_clk; 30985b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP); 31085b4fab2SMaxime COQUELIN 31185b4fab2SMaxime COQUELIN /* Stop set up time */ 31285b4fab2SMaxime COQUELIN val = t->stop_setup_time / ns_per_clk; 31385b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP); 31485b4fab2SMaxime COQUELIN 31585b4fab2SMaxime COQUELIN /* Bus free time */ 31685b4fab2SMaxime COQUELIN val = t->bus_free_time / ns_per_clk; 31785b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE); 31885b4fab2SMaxime COQUELIN 31985b4fab2SMaxime COQUELIN /* Prescalers set up */ 32085b4fab2SMaxime COQUELIN val = rate / 10000000; 32185b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_PRSCALER); 32285b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT); 32385b4fab2SMaxime COQUELIN 32485b4fab2SMaxime COQUELIN /* Noise suppression witdh */ 32585b4fab2SMaxime COQUELIN val = i2c_dev->scl_min_width_us * rate / 100000000; 32685b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH); 32785b4fab2SMaxime COQUELIN 32885b4fab2SMaxime COQUELIN /* Noise suppression max output data delay width */ 32985b4fab2SMaxime COQUELIN val = i2c_dev->sda_min_width_us * rate / 100000000; 33085b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT); 33185b4fab2SMaxime COQUELIN } 33285b4fab2SMaxime COQUELIN 33385b4fab2SMaxime COQUELIN static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev) 33485b4fab2SMaxime COQUELIN { 33585b4fab2SMaxime COQUELIN u32 sta; 33685b4fab2SMaxime COQUELIN int i; 33785b4fab2SMaxime COQUELIN 33885b4fab2SMaxime COQUELIN for (i = 0; i < 10; i++) { 33985b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 34085b4fab2SMaxime COQUELIN if (!(sta & SSC_STA_BUSY)) 34185b4fab2SMaxime COQUELIN return 0; 34285b4fab2SMaxime COQUELIN 34385b4fab2SMaxime COQUELIN usleep_range(2000, 4000); 34485b4fab2SMaxime COQUELIN } 34585b4fab2SMaxime COQUELIN 34685b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta); 34785b4fab2SMaxime COQUELIN 34885b4fab2SMaxime COQUELIN return -EBUSY; 34985b4fab2SMaxime COQUELIN } 35085b4fab2SMaxime COQUELIN 35185b4fab2SMaxime COQUELIN /** 35285b4fab2SMaxime COQUELIN * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO 35385b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 35485b4fab2SMaxime COQUELIN * @byte: Data to write in the Tx FIFO 35585b4fab2SMaxime COQUELIN */ 35685b4fab2SMaxime COQUELIN static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte) 35785b4fab2SMaxime COQUELIN { 35885b4fab2SMaxime COQUELIN u16 tbuf = byte << 1; 35985b4fab2SMaxime COQUELIN 36085b4fab2SMaxime COQUELIN writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF); 36185b4fab2SMaxime COQUELIN } 36285b4fab2SMaxime COQUELIN 36385b4fab2SMaxime COQUELIN /** 36485b4fab2SMaxime COQUELIN * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode 36585b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 36685b4fab2SMaxime COQUELIN * 36785b4fab2SMaxime COQUELIN * This functions fills the Tx FIFO with I2C transfert buffer when 36885b4fab2SMaxime COQUELIN * in write mode. 36985b4fab2SMaxime COQUELIN */ 37085b4fab2SMaxime COQUELIN static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev) 37185b4fab2SMaxime COQUELIN { 37285b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 37385b4fab2SMaxime COQUELIN u32 tx_fstat, sta; 37485b4fab2SMaxime COQUELIN int i; 37585b4fab2SMaxime COQUELIN 37685b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 37785b4fab2SMaxime COQUELIN if (sta & SSC_STA_TX_FIFO_FULL) 37885b4fab2SMaxime COQUELIN return; 37985b4fab2SMaxime COQUELIN 38085b4fab2SMaxime COQUELIN tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); 38185b4fab2SMaxime COQUELIN tx_fstat &= SSC_TX_FSTAT_STATUS; 38285b4fab2SMaxime COQUELIN 38385b4fab2SMaxime COQUELIN if (c->count < (SSC_TXFIFO_SIZE - tx_fstat)) 38485b4fab2SMaxime COQUELIN i = c->count; 38585b4fab2SMaxime COQUELIN else 38685b4fab2SMaxime COQUELIN i = SSC_TXFIFO_SIZE - tx_fstat; 38785b4fab2SMaxime COQUELIN 38885b4fab2SMaxime COQUELIN for (; i > 0; i--, c->count--, c->buf++) 38985b4fab2SMaxime COQUELIN st_i2c_write_tx_fifo(i2c_dev, *c->buf); 39085b4fab2SMaxime COQUELIN } 39185b4fab2SMaxime COQUELIN 39285b4fab2SMaxime COQUELIN /** 39385b4fab2SMaxime COQUELIN * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode 39485b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 39585b4fab2SMaxime COQUELIN * 39685b4fab2SMaxime COQUELIN * This functions fills the Tx FIFO with fixed pattern when 39785b4fab2SMaxime COQUELIN * in read mode to trigger clock. 39885b4fab2SMaxime COQUELIN */ 39985b4fab2SMaxime COQUELIN static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max) 40085b4fab2SMaxime COQUELIN { 40185b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 40285b4fab2SMaxime COQUELIN u32 tx_fstat, sta; 40385b4fab2SMaxime COQUELIN int i; 40485b4fab2SMaxime COQUELIN 40585b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 40685b4fab2SMaxime COQUELIN if (sta & SSC_STA_TX_FIFO_FULL) 40785b4fab2SMaxime COQUELIN return; 40885b4fab2SMaxime COQUELIN 40985b4fab2SMaxime COQUELIN tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); 41085b4fab2SMaxime COQUELIN tx_fstat &= SSC_TX_FSTAT_STATUS; 41185b4fab2SMaxime COQUELIN 41285b4fab2SMaxime COQUELIN if (max < (SSC_TXFIFO_SIZE - tx_fstat)) 41385b4fab2SMaxime COQUELIN i = max; 41485b4fab2SMaxime COQUELIN else 41585b4fab2SMaxime COQUELIN i = SSC_TXFIFO_SIZE - tx_fstat; 41685b4fab2SMaxime COQUELIN 41785b4fab2SMaxime COQUELIN for (; i > 0; i--, c->xfered++) 41885b4fab2SMaxime COQUELIN st_i2c_write_tx_fifo(i2c_dev, 0xff); 41985b4fab2SMaxime COQUELIN } 42085b4fab2SMaxime COQUELIN 42185b4fab2SMaxime COQUELIN static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev) 42285b4fab2SMaxime COQUELIN { 42385b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 42485b4fab2SMaxime COQUELIN u32 i, sta; 42585b4fab2SMaxime COQUELIN u16 rbuf; 42685b4fab2SMaxime COQUELIN 42785b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 42885b4fab2SMaxime COQUELIN if (sta & SSC_STA_RIR) { 42985b4fab2SMaxime COQUELIN i = SSC_RXFIFO_SIZE; 43085b4fab2SMaxime COQUELIN } else { 43185b4fab2SMaxime COQUELIN i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT); 43285b4fab2SMaxime COQUELIN i &= SSC_RX_FSTAT_STATUS; 43385b4fab2SMaxime COQUELIN } 43485b4fab2SMaxime COQUELIN 43585b4fab2SMaxime COQUELIN for (; (i > 0) && (c->count > 0); i--, c->count--) { 43685b4fab2SMaxime COQUELIN rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1; 43785b4fab2SMaxime COQUELIN *c->buf++ = (u8)rbuf & 0xff; 43885b4fab2SMaxime COQUELIN } 43985b4fab2SMaxime COQUELIN 44085b4fab2SMaxime COQUELIN if (i) { 44185b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i); 44285b4fab2SMaxime COQUELIN st_i2c_flush_rx_fifo(i2c_dev); 44385b4fab2SMaxime COQUELIN } 44485b4fab2SMaxime COQUELIN } 44585b4fab2SMaxime COQUELIN 44685b4fab2SMaxime COQUELIN /** 44785b4fab2SMaxime COQUELIN * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition 44885b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 44985b4fab2SMaxime COQUELIN */ 45085b4fab2SMaxime COQUELIN static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev) 45185b4fab2SMaxime COQUELIN { 45285b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 45385b4fab2SMaxime COQUELIN 45485b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN); 45585b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); 45685b4fab2SMaxime COQUELIN 45785b4fab2SMaxime COQUELIN if (c->stop) { 45885b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN); 45985b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 46085b4fab2SMaxime COQUELIN } else { 46185b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN); 46285b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG); 46385b4fab2SMaxime COQUELIN } 46485b4fab2SMaxime COQUELIN } 46585b4fab2SMaxime COQUELIN 46685b4fab2SMaxime COQUELIN /** 46785b4fab2SMaxime COQUELIN * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write 46885b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 46985b4fab2SMaxime COQUELIN */ 47085b4fab2SMaxime COQUELIN static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev) 47185b4fab2SMaxime COQUELIN { 47285b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 47385b4fab2SMaxime COQUELIN 47485b4fab2SMaxime COQUELIN st_i2c_flush_rx_fifo(i2c_dev); 47585b4fab2SMaxime COQUELIN 47685b4fab2SMaxime COQUELIN if (!c->count) 47785b4fab2SMaxime COQUELIN /* End of xfer, send stop or repstart */ 47885b4fab2SMaxime COQUELIN st_i2c_terminate_xfer(i2c_dev); 47985b4fab2SMaxime COQUELIN else 48085b4fab2SMaxime COQUELIN st_i2c_wr_fill_tx_fifo(i2c_dev); 48185b4fab2SMaxime COQUELIN } 48285b4fab2SMaxime COQUELIN 48385b4fab2SMaxime COQUELIN /** 48485b4fab2SMaxime COQUELIN * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read 48585b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 48685b4fab2SMaxime COQUELIN */ 48785b4fab2SMaxime COQUELIN static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev) 48885b4fab2SMaxime COQUELIN { 48985b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 49085b4fab2SMaxime COQUELIN u32 ien; 49185b4fab2SMaxime COQUELIN 49285b4fab2SMaxime COQUELIN /* Trash the address read back */ 49385b4fab2SMaxime COQUELIN if (!c->xfered) { 49485b4fab2SMaxime COQUELIN readl_relaxed(i2c_dev->base + SSC_RBUF); 49585b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB); 49685b4fab2SMaxime COQUELIN } else { 49785b4fab2SMaxime COQUELIN st_i2c_read_rx_fifo(i2c_dev); 49885b4fab2SMaxime COQUELIN } 49985b4fab2SMaxime COQUELIN 50085b4fab2SMaxime COQUELIN if (!c->count) { 50185b4fab2SMaxime COQUELIN /* End of xfer, send stop or repstart */ 50285b4fab2SMaxime COQUELIN st_i2c_terminate_xfer(i2c_dev); 50385b4fab2SMaxime COQUELIN } else if (c->count == 1) { 50485b4fab2SMaxime COQUELIN /* Penultimate byte to xfer, disable ACK gen. */ 50585b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG); 50685b4fab2SMaxime COQUELIN 50785b4fab2SMaxime COQUELIN /* Last received byte is to be handled by NACK interrupt */ 50885b4fab2SMaxime COQUELIN ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN; 50985b4fab2SMaxime COQUELIN writel_relaxed(ien, i2c_dev->base + SSC_IEN); 51085b4fab2SMaxime COQUELIN 51185b4fab2SMaxime COQUELIN st_i2c_rd_fill_tx_fifo(i2c_dev, c->count); 51285b4fab2SMaxime COQUELIN } else { 51385b4fab2SMaxime COQUELIN st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1); 51485b4fab2SMaxime COQUELIN } 51585b4fab2SMaxime COQUELIN } 51685b4fab2SMaxime COQUELIN 51785b4fab2SMaxime COQUELIN /** 51885b4fab2SMaxime COQUELIN * st_i2c_isr() - Interrupt routine 51985b4fab2SMaxime COQUELIN * @irq: interrupt number 52085b4fab2SMaxime COQUELIN * @data: Controller's private data 52185b4fab2SMaxime COQUELIN */ 52285b4fab2SMaxime COQUELIN static irqreturn_t st_i2c_isr_thread(int irq, void *data) 52385b4fab2SMaxime COQUELIN { 52485b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev = data; 52585b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 52685b4fab2SMaxime COQUELIN u32 sta, ien; 52785b4fab2SMaxime COQUELIN int it; 52885b4fab2SMaxime COQUELIN 52985b4fab2SMaxime COQUELIN ien = readl_relaxed(i2c_dev->base + SSC_IEN); 53085b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 53185b4fab2SMaxime COQUELIN 53285b4fab2SMaxime COQUELIN /* Use __fls() to check error bits first */ 53385b4fab2SMaxime COQUELIN it = __fls(sta & ien); 53485b4fab2SMaxime COQUELIN if (it < 0) { 53585b4fab2SMaxime COQUELIN dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n", 53685b4fab2SMaxime COQUELIN sta, ien); 53785b4fab2SMaxime COQUELIN return IRQ_NONE; 53885b4fab2SMaxime COQUELIN } 53985b4fab2SMaxime COQUELIN 54085b4fab2SMaxime COQUELIN switch (1 << it) { 54185b4fab2SMaxime COQUELIN case SSC_STA_TE: 54285b4fab2SMaxime COQUELIN if (c->addr & I2C_M_RD) 54385b4fab2SMaxime COQUELIN st_i2c_handle_read(i2c_dev); 54485b4fab2SMaxime COQUELIN else 54585b4fab2SMaxime COQUELIN st_i2c_handle_write(i2c_dev); 54685b4fab2SMaxime COQUELIN break; 54785b4fab2SMaxime COQUELIN 54885b4fab2SMaxime COQUELIN case SSC_STA_STOP: 54985b4fab2SMaxime COQUELIN case SSC_STA_REPSTRT: 55085b4fab2SMaxime COQUELIN writel_relaxed(0, i2c_dev->base + SSC_IEN); 55185b4fab2SMaxime COQUELIN complete(&i2c_dev->complete); 55285b4fab2SMaxime COQUELIN break; 55385b4fab2SMaxime COQUELIN 55485b4fab2SMaxime COQUELIN case SSC_STA_NACK: 55585b4fab2SMaxime COQUELIN writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR); 55685b4fab2SMaxime COQUELIN 55785b4fab2SMaxime COQUELIN /* Last received byte handled by NACK interrupt */ 55885b4fab2SMaxime COQUELIN if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) { 55985b4fab2SMaxime COQUELIN st_i2c_handle_read(i2c_dev); 56085b4fab2SMaxime COQUELIN break; 56185b4fab2SMaxime COQUELIN } 56285b4fab2SMaxime COQUELIN 56385b4fab2SMaxime COQUELIN it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; 56485b4fab2SMaxime COQUELIN writel_relaxed(it, i2c_dev->base + SSC_IEN); 56585b4fab2SMaxime COQUELIN 56685b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 56785b4fab2SMaxime COQUELIN c->result = -EIO; 56885b4fab2SMaxime COQUELIN break; 56985b4fab2SMaxime COQUELIN 57085b4fab2SMaxime COQUELIN case SSC_STA_ARBL: 57185b4fab2SMaxime COQUELIN writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR); 57285b4fab2SMaxime COQUELIN 57385b4fab2SMaxime COQUELIN it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; 57485b4fab2SMaxime COQUELIN writel_relaxed(it, i2c_dev->base + SSC_IEN); 57585b4fab2SMaxime COQUELIN 57685b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 5774fda9962SMaxime COQUELIN c->result = -EAGAIN; 57885b4fab2SMaxime COQUELIN break; 57985b4fab2SMaxime COQUELIN 58085b4fab2SMaxime COQUELIN default: 58185b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, 58285b4fab2SMaxime COQUELIN "it %d unhandled (sta=0x%04x)\n", it, sta); 58385b4fab2SMaxime COQUELIN } 58485b4fab2SMaxime COQUELIN 58585b4fab2SMaxime COQUELIN /* 58685b4fab2SMaxime COQUELIN * Read IEN register to ensure interrupt mask write is effective 58785b4fab2SMaxime COQUELIN * before re-enabling interrupt at GIC level, and thus avoid spurious 58885b4fab2SMaxime COQUELIN * interrupts. 58985b4fab2SMaxime COQUELIN */ 59085b4fab2SMaxime COQUELIN readl(i2c_dev->base + SSC_IEN); 59185b4fab2SMaxime COQUELIN 59285b4fab2SMaxime COQUELIN return IRQ_HANDLED; 59385b4fab2SMaxime COQUELIN } 59485b4fab2SMaxime COQUELIN 59585b4fab2SMaxime COQUELIN /** 59685b4fab2SMaxime COQUELIN * st_i2c_xfer_msg() - Transfer a single I2C message 59785b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 59885b4fab2SMaxime COQUELIN * @msg: I2C message to transfer 59985b4fab2SMaxime COQUELIN * @is_first: first message of the sequence 60085b4fab2SMaxime COQUELIN * @is_last: last message of the sequence 60185b4fab2SMaxime COQUELIN */ 60285b4fab2SMaxime COQUELIN static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg, 60385b4fab2SMaxime COQUELIN bool is_first, bool is_last) 60485b4fab2SMaxime COQUELIN { 60585b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 60685b4fab2SMaxime COQUELIN u32 ctl, i2c, it; 60785b4fab2SMaxime COQUELIN unsigned long timeout; 60885b4fab2SMaxime COQUELIN int ret; 60985b4fab2SMaxime COQUELIN 61085b4fab2SMaxime COQUELIN c->addr = (u8)(msg->addr << 1); 61185b4fab2SMaxime COQUELIN c->addr |= (msg->flags & I2C_M_RD); 61285b4fab2SMaxime COQUELIN c->buf = msg->buf; 61385b4fab2SMaxime COQUELIN c->count = msg->len; 61485b4fab2SMaxime COQUELIN c->xfered = 0; 61585b4fab2SMaxime COQUELIN c->result = 0; 61685b4fab2SMaxime COQUELIN c->stop = is_last; 61785b4fab2SMaxime COQUELIN 61813509c3aSLinus Torvalds reinit_completion(&i2c_dev->complete); 61985b4fab2SMaxime COQUELIN 62085b4fab2SMaxime COQUELIN ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO; 62185b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); 62285b4fab2SMaxime COQUELIN 62385b4fab2SMaxime COQUELIN i2c = SSC_I2C_TXENB; 62485b4fab2SMaxime COQUELIN if (c->addr & I2C_M_RD) 62585b4fab2SMaxime COQUELIN i2c |= SSC_I2C_ACKG; 62685b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c); 62785b4fab2SMaxime COQUELIN 62885b4fab2SMaxime COQUELIN /* Write slave address */ 62985b4fab2SMaxime COQUELIN st_i2c_write_tx_fifo(i2c_dev, c->addr); 63085b4fab2SMaxime COQUELIN 63185b4fab2SMaxime COQUELIN /* Pre-fill Tx fifo with data in case of write */ 63285b4fab2SMaxime COQUELIN if (!(c->addr & I2C_M_RD)) 63385b4fab2SMaxime COQUELIN st_i2c_wr_fill_tx_fifo(i2c_dev); 63485b4fab2SMaxime COQUELIN 63585b4fab2SMaxime COQUELIN it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN; 63685b4fab2SMaxime COQUELIN writel_relaxed(it, i2c_dev->base + SSC_IEN); 63785b4fab2SMaxime COQUELIN 63885b4fab2SMaxime COQUELIN if (is_first) { 63985b4fab2SMaxime COQUELIN ret = st_i2c_wait_free_bus(i2c_dev); 64085b4fab2SMaxime COQUELIN if (ret) 64185b4fab2SMaxime COQUELIN return ret; 64285b4fab2SMaxime COQUELIN 64385b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); 64485b4fab2SMaxime COQUELIN } 64585b4fab2SMaxime COQUELIN 64685b4fab2SMaxime COQUELIN timeout = wait_for_completion_timeout(&i2c_dev->complete, 64785b4fab2SMaxime COQUELIN i2c_dev->adap.timeout); 64885b4fab2SMaxime COQUELIN ret = c->result; 64985b4fab2SMaxime COQUELIN 65085b4fab2SMaxime COQUELIN if (!timeout) { 65185b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n", 65285b4fab2SMaxime COQUELIN c->addr); 65385b4fab2SMaxime COQUELIN ret = -ETIMEDOUT; 65485b4fab2SMaxime COQUELIN } 65585b4fab2SMaxime COQUELIN 65685b4fab2SMaxime COQUELIN i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG; 65785b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c); 65885b4fab2SMaxime COQUELIN 65985b4fab2SMaxime COQUELIN writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT, 66085b4fab2SMaxime COQUELIN i2c_dev->base + SSC_CLR); 66185b4fab2SMaxime COQUELIN 66285b4fab2SMaxime COQUELIN return ret; 66385b4fab2SMaxime COQUELIN } 66485b4fab2SMaxime COQUELIN 66585b4fab2SMaxime COQUELIN /** 66685b4fab2SMaxime COQUELIN * st_i2c_xfer() - Transfer a single I2C message 66785b4fab2SMaxime COQUELIN * @i2c_adap: Adapter pointer to the controller 66885b4fab2SMaxime COQUELIN * @msgs: Pointer to data to be written. 66985b4fab2SMaxime COQUELIN * @num: Number of messages to be executed 67085b4fab2SMaxime COQUELIN */ 67185b4fab2SMaxime COQUELIN static int st_i2c_xfer(struct i2c_adapter *i2c_adap, 67285b4fab2SMaxime COQUELIN struct i2c_msg msgs[], int num) 67385b4fab2SMaxime COQUELIN { 67485b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 67585b4fab2SMaxime COQUELIN int ret, i; 67685b4fab2SMaxime COQUELIN 67785b4fab2SMaxime COQUELIN i2c_dev->busy = true; 67885b4fab2SMaxime COQUELIN 67985b4fab2SMaxime COQUELIN ret = clk_prepare_enable(i2c_dev->clk); 68085b4fab2SMaxime COQUELIN if (ret) { 68185b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); 68285b4fab2SMaxime COQUELIN return ret; 68385b4fab2SMaxime COQUELIN } 68485b4fab2SMaxime COQUELIN 68585b4fab2SMaxime COQUELIN pinctrl_pm_select_default_state(i2c_dev->dev); 68685b4fab2SMaxime COQUELIN 68785b4fab2SMaxime COQUELIN st_i2c_hw_config(i2c_dev); 68885b4fab2SMaxime COQUELIN 68985b4fab2SMaxime COQUELIN for (i = 0; (i < num) && !ret; i++) 69085b4fab2SMaxime COQUELIN ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1); 69185b4fab2SMaxime COQUELIN 69285b4fab2SMaxime COQUELIN pinctrl_pm_select_idle_state(i2c_dev->dev); 69385b4fab2SMaxime COQUELIN 69485b4fab2SMaxime COQUELIN clk_disable_unprepare(i2c_dev->clk); 69585b4fab2SMaxime COQUELIN 69685b4fab2SMaxime COQUELIN i2c_dev->busy = false; 69785b4fab2SMaxime COQUELIN 69885b4fab2SMaxime COQUELIN return (ret < 0) ? ret : i; 69985b4fab2SMaxime COQUELIN } 70085b4fab2SMaxime COQUELIN 70185b4fab2SMaxime COQUELIN #ifdef CONFIG_PM_SLEEP 70285b4fab2SMaxime COQUELIN static int st_i2c_suspend(struct device *dev) 70385b4fab2SMaxime COQUELIN { 70485b4fab2SMaxime COQUELIN struct platform_device *pdev = 70585b4fab2SMaxime COQUELIN container_of(dev, struct platform_device, dev); 70685b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 70785b4fab2SMaxime COQUELIN 70885b4fab2SMaxime COQUELIN if (i2c_dev->busy) 70985b4fab2SMaxime COQUELIN return -EBUSY; 71085b4fab2SMaxime COQUELIN 71185b4fab2SMaxime COQUELIN pinctrl_pm_select_sleep_state(dev); 71285b4fab2SMaxime COQUELIN 71385b4fab2SMaxime COQUELIN return 0; 71485b4fab2SMaxime COQUELIN } 71585b4fab2SMaxime COQUELIN 71685b4fab2SMaxime COQUELIN static int st_i2c_resume(struct device *dev) 71785b4fab2SMaxime COQUELIN { 71885b4fab2SMaxime COQUELIN pinctrl_pm_select_default_state(dev); 71985b4fab2SMaxime COQUELIN /* Go in idle state if available */ 72085b4fab2SMaxime COQUELIN pinctrl_pm_select_idle_state(dev); 72185b4fab2SMaxime COQUELIN 72285b4fab2SMaxime COQUELIN return 0; 72385b4fab2SMaxime COQUELIN } 72485b4fab2SMaxime COQUELIN 72585b4fab2SMaxime COQUELIN static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume); 72685b4fab2SMaxime COQUELIN #define ST_I2C_PM (&st_i2c_pm) 72785b4fab2SMaxime COQUELIN #else 72885b4fab2SMaxime COQUELIN #define ST_I2C_PM NULL 72985b4fab2SMaxime COQUELIN #endif 73085b4fab2SMaxime COQUELIN 73185b4fab2SMaxime COQUELIN static u32 st_i2c_func(struct i2c_adapter *adap) 73285b4fab2SMaxime COQUELIN { 73385b4fab2SMaxime COQUELIN return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 73485b4fab2SMaxime COQUELIN } 73585b4fab2SMaxime COQUELIN 73685b4fab2SMaxime COQUELIN static struct i2c_algorithm st_i2c_algo = { 73785b4fab2SMaxime COQUELIN .master_xfer = st_i2c_xfer, 73885b4fab2SMaxime COQUELIN .functionality = st_i2c_func, 73985b4fab2SMaxime COQUELIN }; 74085b4fab2SMaxime COQUELIN 74185b4fab2SMaxime COQUELIN static int st_i2c_of_get_deglitch(struct device_node *np, 74285b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev) 74385b4fab2SMaxime COQUELIN { 74485b4fab2SMaxime COQUELIN int ret; 74585b4fab2SMaxime COQUELIN 74685b4fab2SMaxime COQUELIN ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us", 74785b4fab2SMaxime COQUELIN &i2c_dev->scl_min_width_us); 74885b4fab2SMaxime COQUELIN if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { 74985b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n"); 75085b4fab2SMaxime COQUELIN return ret; 75185b4fab2SMaxime COQUELIN } 75285b4fab2SMaxime COQUELIN 75385b4fab2SMaxime COQUELIN ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us", 75485b4fab2SMaxime COQUELIN &i2c_dev->sda_min_width_us); 75585b4fab2SMaxime COQUELIN if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { 75685b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n"); 75785b4fab2SMaxime COQUELIN return ret; 75885b4fab2SMaxime COQUELIN } 75985b4fab2SMaxime COQUELIN 76085b4fab2SMaxime COQUELIN return 0; 76185b4fab2SMaxime COQUELIN } 76285b4fab2SMaxime COQUELIN 76385b4fab2SMaxime COQUELIN static int st_i2c_probe(struct platform_device *pdev) 76485b4fab2SMaxime COQUELIN { 76585b4fab2SMaxime COQUELIN struct device_node *np = pdev->dev.of_node; 76685b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev; 76785b4fab2SMaxime COQUELIN struct resource *res; 76885b4fab2SMaxime COQUELIN u32 clk_rate; 76985b4fab2SMaxime COQUELIN struct i2c_adapter *adap; 77085b4fab2SMaxime COQUELIN int ret; 77185b4fab2SMaxime COQUELIN 77285b4fab2SMaxime COQUELIN i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 77385b4fab2SMaxime COQUELIN if (!i2c_dev) 77485b4fab2SMaxime COQUELIN return -ENOMEM; 77585b4fab2SMaxime COQUELIN 77685b4fab2SMaxime COQUELIN res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 77785b4fab2SMaxime COQUELIN i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 77885b4fab2SMaxime COQUELIN if (IS_ERR(i2c_dev->base)) 77985b4fab2SMaxime COQUELIN return PTR_ERR(i2c_dev->base); 78085b4fab2SMaxime COQUELIN 78185b4fab2SMaxime COQUELIN i2c_dev->irq = irq_of_parse_and_map(np, 0); 78285b4fab2SMaxime COQUELIN if (!i2c_dev->irq) { 78385b4fab2SMaxime COQUELIN dev_err(&pdev->dev, "IRQ missing or invalid\n"); 78485b4fab2SMaxime COQUELIN return -EINVAL; 78585b4fab2SMaxime COQUELIN } 78685b4fab2SMaxime COQUELIN 78785b4fab2SMaxime COQUELIN i2c_dev->clk = of_clk_get_by_name(np, "ssc"); 78885b4fab2SMaxime COQUELIN if (IS_ERR(i2c_dev->clk)) { 78985b4fab2SMaxime COQUELIN dev_err(&pdev->dev, "Unable to request clock\n"); 79085b4fab2SMaxime COQUELIN return PTR_ERR(i2c_dev->clk); 79185b4fab2SMaxime COQUELIN } 79285b4fab2SMaxime COQUELIN 79385b4fab2SMaxime COQUELIN i2c_dev->mode = I2C_MODE_STANDARD; 79485b4fab2SMaxime COQUELIN ret = of_property_read_u32(np, "clock-frequency", &clk_rate); 79585b4fab2SMaxime COQUELIN if ((!ret) && (clk_rate == 400000)) 79685b4fab2SMaxime COQUELIN i2c_dev->mode = I2C_MODE_FAST; 79785b4fab2SMaxime COQUELIN 79885b4fab2SMaxime COQUELIN i2c_dev->dev = &pdev->dev; 79985b4fab2SMaxime COQUELIN 80085b4fab2SMaxime COQUELIN ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq, 80185b4fab2SMaxime COQUELIN NULL, st_i2c_isr_thread, 80285b4fab2SMaxime COQUELIN IRQF_ONESHOT, pdev->name, i2c_dev); 80385b4fab2SMaxime COQUELIN if (ret) { 80485b4fab2SMaxime COQUELIN dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 80585b4fab2SMaxime COQUELIN return ret; 80685b4fab2SMaxime COQUELIN } 80785b4fab2SMaxime COQUELIN 80885b4fab2SMaxime COQUELIN pinctrl_pm_select_default_state(i2c_dev->dev); 80985b4fab2SMaxime COQUELIN /* In case idle state available, select it */ 81085b4fab2SMaxime COQUELIN pinctrl_pm_select_idle_state(i2c_dev->dev); 81185b4fab2SMaxime COQUELIN 81285b4fab2SMaxime COQUELIN ret = st_i2c_of_get_deglitch(np, i2c_dev); 81385b4fab2SMaxime COQUELIN if (ret) 81485b4fab2SMaxime COQUELIN return ret; 81585b4fab2SMaxime COQUELIN 81685b4fab2SMaxime COQUELIN adap = &i2c_dev->adap; 81785b4fab2SMaxime COQUELIN i2c_set_adapdata(adap, i2c_dev); 81885b4fab2SMaxime COQUELIN snprintf(adap->name, sizeof(adap->name), "ST I2C(0x%x)", res->start); 81985b4fab2SMaxime COQUELIN adap->owner = THIS_MODULE; 82085b4fab2SMaxime COQUELIN adap->timeout = 2 * HZ; 82185b4fab2SMaxime COQUELIN adap->retries = 0; 82285b4fab2SMaxime COQUELIN adap->algo = &st_i2c_algo; 82385b4fab2SMaxime COQUELIN adap->dev.parent = &pdev->dev; 82485b4fab2SMaxime COQUELIN adap->dev.of_node = pdev->dev.of_node; 82585b4fab2SMaxime COQUELIN 82685b4fab2SMaxime COQUELIN init_completion(&i2c_dev->complete); 82785b4fab2SMaxime COQUELIN 82885b4fab2SMaxime COQUELIN ret = i2c_add_adapter(adap); 82985b4fab2SMaxime COQUELIN if (ret) { 83085b4fab2SMaxime COQUELIN dev_err(&pdev->dev, "Failed to add adapter\n"); 83185b4fab2SMaxime COQUELIN return ret; 83285b4fab2SMaxime COQUELIN } 83385b4fab2SMaxime COQUELIN 83485b4fab2SMaxime COQUELIN platform_set_drvdata(pdev, i2c_dev); 83585b4fab2SMaxime COQUELIN 83685b4fab2SMaxime COQUELIN dev_info(i2c_dev->dev, "%s initialized\n", adap->name); 83785b4fab2SMaxime COQUELIN 83885b4fab2SMaxime COQUELIN return 0; 83985b4fab2SMaxime COQUELIN } 84085b4fab2SMaxime COQUELIN 84185b4fab2SMaxime COQUELIN static int st_i2c_remove(struct platform_device *pdev) 84285b4fab2SMaxime COQUELIN { 84385b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 84485b4fab2SMaxime COQUELIN 84585b4fab2SMaxime COQUELIN i2c_del_adapter(&i2c_dev->adap); 84685b4fab2SMaxime COQUELIN 84785b4fab2SMaxime COQUELIN return 0; 84885b4fab2SMaxime COQUELIN } 84985b4fab2SMaxime COQUELIN 85085b4fab2SMaxime COQUELIN static struct of_device_id st_i2c_match[] = { 85185b4fab2SMaxime COQUELIN { .compatible = "st,comms-ssc-i2c", }, 85285b4fab2SMaxime COQUELIN { .compatible = "st,comms-ssc4-i2c", }, 85385b4fab2SMaxime COQUELIN {}, 85485b4fab2SMaxime COQUELIN }; 85585b4fab2SMaxime COQUELIN MODULE_DEVICE_TABLE(of, st_i2c_match); 85685b4fab2SMaxime COQUELIN 85785b4fab2SMaxime COQUELIN static struct platform_driver st_i2c_driver = { 85885b4fab2SMaxime COQUELIN .driver = { 85985b4fab2SMaxime COQUELIN .name = "st-i2c", 86085b4fab2SMaxime COQUELIN .owner = THIS_MODULE, 86185b4fab2SMaxime COQUELIN .of_match_table = st_i2c_match, 86285b4fab2SMaxime COQUELIN .pm = ST_I2C_PM, 86385b4fab2SMaxime COQUELIN }, 86485b4fab2SMaxime COQUELIN .probe = st_i2c_probe, 86585b4fab2SMaxime COQUELIN .remove = st_i2c_remove, 86685b4fab2SMaxime COQUELIN }; 86785b4fab2SMaxime COQUELIN 86885b4fab2SMaxime COQUELIN module_platform_driver(st_i2c_driver); 86985b4fab2SMaxime COQUELIN 87085b4fab2SMaxime COQUELIN MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>"); 87185b4fab2SMaxime COQUELIN MODULE_DESCRIPTION("STMicroelectronics I2C driver"); 87285b4fab2SMaxime COQUELIN MODULE_LICENSE("GPL v2"); 873