1 /* 2 * SuperH Mobile I2C Controller 3 * 4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> 5 * 6 * Copyright (C) 2008 Magnus Damm 7 * 8 * Portions of the code based on out-of-tree driver i2c-sh7343.c 9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/dmaengine.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/err.h> 26 #include <linux/i2c.h> 27 #include <linux/i2c/i2c-sh_mobile.h> 28 #include <linux/init.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/of_device.h> 34 #include <linux/platform_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/slab.h> 37 38 /* Transmit operation: */ 39 /* */ 40 /* 0 byte transmit */ 41 /* BUS: S A8 ACK P(*) */ 42 /* IRQ: DTE WAIT */ 43 /* ICIC: */ 44 /* ICCR: 0x94 0x90 */ 45 /* ICDR: A8 */ 46 /* */ 47 /* 1 byte transmit */ 48 /* BUS: S A8 ACK D8(1) ACK P(*) */ 49 /* IRQ: DTE WAIT WAIT */ 50 /* ICIC: -DTE */ 51 /* ICCR: 0x94 0x90 */ 52 /* ICDR: A8 D8(1) */ 53 /* */ 54 /* 2 byte transmit */ 55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ 56 /* IRQ: DTE WAIT WAIT WAIT */ 57 /* ICIC: -DTE */ 58 /* ICCR: 0x94 0x90 */ 59 /* ICDR: A8 D8(1) D8(2) */ 60 /* */ 61 /* 3 bytes or more, +---------+ gets repeated */ 62 /* */ 63 /* */ 64 /* Receive operation: */ 65 /* */ 66 /* 0 byte receive - not supported since slave may hold SDA low */ 67 /* */ 68 /* 1 byte receive [TX] | [RX] */ 69 /* BUS: S A8 ACK | D8(1) ACK P(*) */ 70 /* IRQ: DTE WAIT | WAIT DTE */ 71 /* ICIC: -DTE | +DTE */ 72 /* ICCR: 0x94 0x81 | 0xc0 */ 73 /* ICDR: A8 | D8(1) */ 74 /* */ 75 /* 2 byte receive [TX]| [RX] */ 76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ 77 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 78 /* ICIC: -DTE | +DTE */ 79 /* ICCR: 0x94 0x81 | 0xc0 */ 80 /* ICDR: A8 | D8(1) D8(2) */ 81 /* */ 82 /* 3 byte receive [TX] | [RX] (*) */ 83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 85 /* ICIC: -DTE | +DTE */ 86 /* ICCR: 0x94 0x81 | 0xc0 */ 87 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 88 /* */ 89 /* 4 bytes or more, this part is repeated +---------+ */ 90 /* */ 91 /* */ 92 /* Interrupt order and BUSY flag */ 93 /* ___ _ */ 94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 96 /* */ 97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ 98 /* ___ */ 99 /* WAIT IRQ ________________________________/ \___________ */ 100 /* TACK IRQ ____________________________________/ \_______ */ 101 /* DTE IRQ __________________________________________/ \_ */ 102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 103 /* _______________________________________________ */ 104 /* BUSY __/ \_ */ 105 /* */ 106 /* (*) The STOP condition is only sent by the master at the end of the last */ 107 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ 108 /* only cleared after the STOP condition, so, between messages we have to */ 109 /* poll for the DTE bit. */ 110 /* */ 111 112 enum sh_mobile_i2c_op { 113 OP_START = 0, 114 OP_TX_FIRST, 115 OP_TX, 116 OP_TX_STOP, 117 OP_TX_STOP_DATA, 118 OP_TX_TO_RX, 119 OP_RX, 120 OP_RX_STOP, 121 OP_RX_STOP_DATA, 122 }; 123 124 struct sh_mobile_i2c_data { 125 struct device *dev; 126 void __iomem *reg; 127 struct i2c_adapter adap; 128 unsigned long bus_speed; 129 unsigned int clks_per_count; 130 struct clk *clk; 131 u_int8_t icic; 132 u_int8_t flags; 133 u_int16_t iccl; 134 u_int16_t icch; 135 136 spinlock_t lock; 137 wait_queue_head_t wait; 138 struct i2c_msg *msg; 139 int pos; 140 int sr; 141 bool send_stop; 142 143 struct resource *res; 144 struct dma_chan *dma_tx; 145 struct dma_chan *dma_rx; 146 struct scatterlist sg; 147 enum dma_data_direction dma_direction; 148 }; 149 150 struct sh_mobile_dt_config { 151 int clks_per_count; 152 }; 153 154 #define IIC_FLAG_HAS_ICIC67 (1 << 0) 155 156 #define STANDARD_MODE 100000 157 #define FAST_MODE 400000 158 159 /* Register offsets */ 160 #define ICDR 0x00 161 #define ICCR 0x04 162 #define ICSR 0x08 163 #define ICIC 0x0c 164 #define ICCL 0x10 165 #define ICCH 0x14 166 167 /* Register bits */ 168 #define ICCR_ICE 0x80 169 #define ICCR_RACK 0x40 170 #define ICCR_TRS 0x10 171 #define ICCR_BBSY 0x04 172 #define ICCR_SCP 0x01 173 174 #define ICSR_SCLM 0x80 175 #define ICSR_SDAM 0x40 176 #define SW_DONE 0x20 177 #define ICSR_BUSY 0x10 178 #define ICSR_AL 0x08 179 #define ICSR_TACK 0x04 180 #define ICSR_WAIT 0x02 181 #define ICSR_DTE 0x01 182 183 #define ICIC_ICCLB8 0x80 184 #define ICIC_ICCHB8 0x40 185 #define ICIC_TDMAE 0x20 186 #define ICIC_RDMAE 0x10 187 #define ICIC_ALE 0x08 188 #define ICIC_TACKE 0x04 189 #define ICIC_WAITE 0x02 190 #define ICIC_DTEE 0x01 191 192 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 193 { 194 if (offs == ICIC) 195 data |= pd->icic; 196 197 iowrite8(data, pd->reg + offs); 198 } 199 200 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) 201 { 202 return ioread8(pd->reg + offs); 203 } 204 205 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, 206 unsigned char set, unsigned char clr) 207 { 208 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 209 } 210 211 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf) 212 { 213 /* 214 * Conditional expression: 215 * ICCL >= COUNT_CLK * (tLOW + tf) 216 * 217 * SH-Mobile IIC hardware starts counting the LOW period of 218 * the SCL signal (tLOW) as soon as it pulls the SCL line. 219 * In order to meet the tLOW timing spec, we need to take into 220 * account the fall time of SCL signal (tf). Default tf value 221 * should be 0.3 us, for safety. 222 */ 223 return (((count_khz * (tLOW + tf)) + 5000) / 10000); 224 } 225 226 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) 227 { 228 /* 229 * Conditional expression: 230 * ICCH >= COUNT_CLK * (tHIGH + tf) 231 * 232 * SH-Mobile IIC hardware is aware of SCL transition period 'tr', 233 * and can ignore it. SH-Mobile IIC controller starts counting 234 * the HIGH period of the SCL signal (tHIGH) after the SCL input 235 * voltage increases at VIH. 236 * 237 * Afterward it turned out calculating ICCH using only tHIGH spec 238 * will result in violation of the tHD;STA timing spec. We need 239 * to take into account the fall time of SDA signal (tf) at START 240 * condition, in order to meet both tHIGH and tHD;STA specs. 241 */ 242 return (((count_khz * (tHIGH + tf)) + 5000) / 10000); 243 } 244 245 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) 246 { 247 unsigned long i2c_clk_khz; 248 u32 tHIGH, tLOW, tf; 249 uint16_t max_val; 250 251 /* Get clock rate after clock is enabled */ 252 clk_prepare_enable(pd->clk); 253 i2c_clk_khz = clk_get_rate(pd->clk) / 1000; 254 clk_disable_unprepare(pd->clk); 255 i2c_clk_khz /= pd->clks_per_count; 256 257 if (pd->bus_speed == STANDARD_MODE) { 258 tLOW = 47; /* tLOW = 4.7 us */ 259 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ 260 tf = 3; /* tf = 0.3 us */ 261 } else if (pd->bus_speed == FAST_MODE) { 262 tLOW = 13; /* tLOW = 1.3 us */ 263 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ 264 tf = 3; /* tf = 0.3 us */ 265 } else { 266 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", 267 pd->bus_speed); 268 return -EINVAL; 269 } 270 271 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf); 272 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); 273 274 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff; 275 if (pd->iccl > max_val || pd->icch > max_val) { 276 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n", 277 pd->iccl, pd->icch); 278 return -EINVAL; 279 } 280 281 /* one more bit of ICCL in ICIC */ 282 if (pd->iccl & 0x100) 283 pd->icic |= ICIC_ICCLB8; 284 else 285 pd->icic &= ~ICIC_ICCLB8; 286 287 /* one more bit of ICCH in ICIC */ 288 if (pd->icch & 0x100) 289 pd->icic |= ICIC_ICCHB8; 290 else 291 pd->icic &= ~ICIC_ICCHB8; 292 293 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch); 294 return 0; 295 } 296 297 static void activate_ch(struct sh_mobile_i2c_data *pd) 298 { 299 /* Wake up device and enable clock */ 300 pm_runtime_get_sync(pd->dev); 301 clk_prepare_enable(pd->clk); 302 303 /* Enable channel and configure rx ack */ 304 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 305 306 /* Mask all interrupts */ 307 iic_wr(pd, ICIC, 0); 308 309 /* Set the clock */ 310 iic_wr(pd, ICCL, pd->iccl & 0xff); 311 iic_wr(pd, ICCH, pd->icch & 0xff); 312 } 313 314 static void deactivate_ch(struct sh_mobile_i2c_data *pd) 315 { 316 /* Clear/disable interrupts */ 317 iic_wr(pd, ICSR, 0); 318 iic_wr(pd, ICIC, 0); 319 320 /* Disable channel */ 321 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 322 323 /* Disable clock and mark device as idle */ 324 clk_disable_unprepare(pd->clk); 325 pm_runtime_put_sync(pd->dev); 326 } 327 328 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 329 enum sh_mobile_i2c_op op, unsigned char data) 330 { 331 unsigned char ret = 0; 332 unsigned long flags; 333 334 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 335 336 spin_lock_irqsave(&pd->lock, flags); 337 338 switch (op) { 339 case OP_START: /* issue start and trigger DTE interrupt */ 340 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); 341 break; 342 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 343 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 344 iic_wr(pd, ICDR, data); 345 break; 346 case OP_TX: /* write data */ 347 iic_wr(pd, ICDR, data); 348 break; 349 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */ 350 iic_wr(pd, ICDR, data); 351 /* fallthrough */ 352 case OP_TX_STOP: /* issue a stop */ 353 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS 354 : ICCR_ICE | ICCR_TRS | ICCR_BBSY); 355 break; 356 case OP_TX_TO_RX: /* select read mode */ 357 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); 358 break; 359 case OP_RX: /* just read data */ 360 ret = iic_rd(pd, ICDR); 361 break; 362 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 363 iic_wr(pd, ICIC, 364 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 365 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 366 break; 367 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 368 iic_wr(pd, ICIC, 369 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 370 ret = iic_rd(pd, ICDR); 371 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 372 break; 373 } 374 375 spin_unlock_irqrestore(&pd->lock, flags); 376 377 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 378 return ret; 379 } 380 381 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) 382 { 383 return pd->pos == -1; 384 } 385 386 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) 387 { 388 return pd->pos == pd->msg->len - 1; 389 } 390 391 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, 392 unsigned char *buf) 393 { 394 switch (pd->pos) { 395 case -1: 396 *buf = (pd->msg->addr & 0x7f) << 1; 397 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; 398 break; 399 default: 400 *buf = pd->msg->buf[pd->pos]; 401 } 402 } 403 404 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 405 { 406 unsigned char data; 407 408 if (pd->pos == pd->msg->len) { 409 /* Send stop if we haven't yet (DMA case) */ 410 if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY)) 411 i2c_op(pd, OP_TX_STOP, 0); 412 return 1; 413 } 414 415 sh_mobile_i2c_get_data(pd, &data); 416 417 if (sh_mobile_i2c_is_last_byte(pd)) 418 i2c_op(pd, OP_TX_STOP_DATA, data); 419 else if (sh_mobile_i2c_is_first_byte(pd)) 420 i2c_op(pd, OP_TX_FIRST, data); 421 else 422 i2c_op(pd, OP_TX, data); 423 424 pd->pos++; 425 return 0; 426 } 427 428 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 429 { 430 unsigned char data; 431 int real_pos; 432 433 do { 434 if (pd->pos <= -1) { 435 sh_mobile_i2c_get_data(pd, &data); 436 437 if (sh_mobile_i2c_is_first_byte(pd)) 438 i2c_op(pd, OP_TX_FIRST, data); 439 else 440 i2c_op(pd, OP_TX, data); 441 break; 442 } 443 444 if (pd->pos == 0) { 445 i2c_op(pd, OP_TX_TO_RX, 0); 446 break; 447 } 448 449 real_pos = pd->pos - 2; 450 451 if (pd->pos == pd->msg->len) { 452 if (real_pos < 0) { 453 i2c_op(pd, OP_RX_STOP, 0); 454 break; 455 } 456 data = i2c_op(pd, OP_RX_STOP_DATA, 0); 457 } else 458 data = i2c_op(pd, OP_RX, 0); 459 460 if (real_pos >= 0) 461 pd->msg->buf[real_pos] = data; 462 } while (0); 463 464 pd->pos++; 465 return pd->pos == (pd->msg->len + 2); 466 } 467 468 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 469 { 470 struct sh_mobile_i2c_data *pd = dev_id; 471 unsigned char sr; 472 int wakeup = 0; 473 474 sr = iic_rd(pd, ICSR); 475 pd->sr |= sr; /* remember state */ 476 477 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 478 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 479 pd->pos, pd->msg->len); 480 481 /* Kick off TxDMA after preface was done */ 482 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0) 483 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0); 484 else if (sr & (ICSR_AL | ICSR_TACK)) 485 /* don't interrupt transaction - continue to issue stop */ 486 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 487 else if (pd->msg->flags & I2C_M_RD) 488 wakeup = sh_mobile_i2c_isr_rx(pd); 489 else 490 wakeup = sh_mobile_i2c_isr_tx(pd); 491 492 /* Kick off RxDMA after preface was done */ 493 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1) 494 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0); 495 496 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 497 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 498 499 if (wakeup) { 500 pd->sr |= SW_DONE; 501 wake_up(&pd->wait); 502 } 503 504 /* defeat write posting to avoid spurious WAIT interrupts */ 505 iic_rd(pd, ICSR); 506 507 return IRQ_HANDLED; 508 } 509 510 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd) 511 { 512 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE 513 ? pd->dma_rx : pd->dma_tx; 514 515 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg), 516 pd->msg->len, pd->dma_direction); 517 518 pd->dma_direction = DMA_NONE; 519 } 520 521 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd) 522 { 523 if (pd->dma_direction == DMA_NONE) 524 return; 525 else if (pd->dma_direction == DMA_FROM_DEVICE) 526 dmaengine_terminate_all(pd->dma_rx); 527 else if (pd->dma_direction == DMA_TO_DEVICE) 528 dmaengine_terminate_all(pd->dma_tx); 529 530 sh_mobile_i2c_dma_unmap(pd); 531 } 532 533 static void sh_mobile_i2c_dma_callback(void *data) 534 { 535 struct sh_mobile_i2c_data *pd = data; 536 537 sh_mobile_i2c_dma_unmap(pd); 538 pd->pos = pd->msg->len; 539 540 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE); 541 } 542 543 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev, 544 enum dma_transfer_direction dir, dma_addr_t port_addr) 545 { 546 struct dma_chan *chan; 547 struct dma_slave_config cfg; 548 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 549 int ret; 550 551 chan = dma_request_slave_channel_reason(dev, chan_name); 552 if (IS_ERR(chan)) { 553 ret = PTR_ERR(chan); 554 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret); 555 return chan; 556 } 557 558 memset(&cfg, 0, sizeof(cfg)); 559 cfg.direction = dir; 560 if (dir == DMA_MEM_TO_DEV) { 561 cfg.dst_addr = port_addr; 562 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 563 } else { 564 cfg.src_addr = port_addr; 565 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 566 } 567 568 ret = dmaengine_slave_config(chan, &cfg); 569 if (ret) { 570 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret); 571 dma_release_channel(chan); 572 return ERR_PTR(ret); 573 } 574 575 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 576 return chan; 577 } 578 579 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd) 580 { 581 bool read = pd->msg->flags & I2C_M_RD; 582 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 583 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx; 584 struct dma_async_tx_descriptor *txdesc; 585 dma_addr_t dma_addr; 586 dma_cookie_t cookie; 587 588 if (PTR_ERR(chan) == -EPROBE_DEFER) { 589 if (read) 590 chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM, 591 pd->res->start + ICDR); 592 else 593 chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV, 594 pd->res->start + ICDR); 595 } 596 597 if (IS_ERR(chan)) 598 return; 599 600 dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir); 601 if (dma_mapping_error(pd->dev, dma_addr)) { 602 dev_dbg(pd->dev, "dma map failed, using PIO\n"); 603 return; 604 } 605 606 sg_dma_len(&pd->sg) = pd->msg->len; 607 sg_dma_address(&pd->sg) = dma_addr; 608 609 pd->dma_direction = dir; 610 611 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1, 612 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 613 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 614 if (!txdesc) { 615 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n"); 616 sh_mobile_i2c_cleanup_dma(pd); 617 return; 618 } 619 620 txdesc->callback = sh_mobile_i2c_dma_callback; 621 txdesc->callback_param = pd; 622 623 cookie = dmaengine_submit(txdesc); 624 if (dma_submit_error(cookie)) { 625 dev_dbg(pd->dev, "submitting dma failed, using PIO\n"); 626 sh_mobile_i2c_cleanup_dma(pd); 627 return; 628 } 629 630 dma_async_issue_pending(chan); 631 } 632 633 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, 634 bool do_init) 635 { 636 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 637 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 638 return -EOPNOTSUPP; 639 } 640 641 if (do_init) { 642 /* Initialize channel registers */ 643 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 644 645 /* Enable channel and configure rx ack */ 646 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 647 648 /* Set the clock */ 649 iic_wr(pd, ICCL, pd->iccl & 0xff); 650 iic_wr(pd, ICCH, pd->icch & 0xff); 651 } 652 653 pd->msg = usr_msg; 654 pd->pos = -1; 655 pd->sr = 0; 656 657 if (pd->msg->len > 8) 658 sh_mobile_i2c_xfer_dma(pd); 659 660 /* Enable all interrupts to begin with */ 661 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 662 return 0; 663 } 664 665 static int poll_dte(struct sh_mobile_i2c_data *pd) 666 { 667 int i; 668 669 for (i = 1000; i; i--) { 670 u_int8_t val = iic_rd(pd, ICSR); 671 672 if (val & ICSR_DTE) 673 break; 674 675 if (val & ICSR_TACK) 676 return -ENXIO; 677 678 udelay(10); 679 } 680 681 return i ? 0 : -ETIMEDOUT; 682 } 683 684 static int poll_busy(struct sh_mobile_i2c_data *pd) 685 { 686 int i; 687 688 for (i = 1000; i; i--) { 689 u_int8_t val = iic_rd(pd, ICSR); 690 691 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 692 693 /* the interrupt handler may wake us up before the 694 * transfer is finished, so poll the hardware 695 * until we're done. 696 */ 697 if (!(val & ICSR_BUSY)) { 698 /* handle missing acknowledge and arbitration lost */ 699 val |= pd->sr; 700 if (val & ICSR_TACK) 701 return -ENXIO; 702 if (val & ICSR_AL) 703 return -EAGAIN; 704 break; 705 } 706 707 udelay(10); 708 } 709 710 return i ? 0 : -ETIMEDOUT; 711 } 712 713 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 714 struct i2c_msg *msgs, 715 int num) 716 { 717 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 718 struct i2c_msg *msg; 719 int err = 0; 720 int i, k; 721 722 activate_ch(pd); 723 724 /* Process all messages */ 725 for (i = 0; i < num; i++) { 726 bool do_start = pd->send_stop || !i; 727 msg = &msgs[i]; 728 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; 729 730 err = start_ch(pd, msg, do_start); 731 if (err) 732 break; 733 734 if (do_start) 735 i2c_op(pd, OP_START, 0); 736 737 /* The interrupt handler takes care of the rest... */ 738 k = wait_event_timeout(pd->wait, 739 pd->sr & (ICSR_TACK | SW_DONE), 740 5 * HZ); 741 if (!k) { 742 dev_err(pd->dev, "Transfer request timed out\n"); 743 if (pd->dma_direction != DMA_NONE) 744 sh_mobile_i2c_cleanup_dma(pd); 745 746 err = -ETIMEDOUT; 747 break; 748 } 749 750 if (pd->send_stop) 751 err = poll_busy(pd); 752 else 753 err = poll_dte(pd); 754 if (err < 0) 755 break; 756 } 757 758 deactivate_ch(pd); 759 760 if (!err) 761 err = num; 762 return err; 763 } 764 765 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 766 { 767 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 768 } 769 770 static struct i2c_algorithm sh_mobile_i2c_algorithm = { 771 .functionality = sh_mobile_i2c_func, 772 .master_xfer = sh_mobile_i2c_xfer, 773 }; 774 775 static const struct sh_mobile_dt_config default_dt_config = { 776 .clks_per_count = 1, 777 }; 778 779 static const struct sh_mobile_dt_config fast_clock_dt_config = { 780 .clks_per_count = 2, 781 }; 782 783 static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 784 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, 785 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config }, 786 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config }, 787 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config }, 788 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config }, 789 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config }, 790 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config }, 791 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config }, 792 {}, 793 }; 794 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 795 796 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd) 797 { 798 if (!IS_ERR(pd->dma_tx)) { 799 dma_release_channel(pd->dma_tx); 800 pd->dma_tx = ERR_PTR(-EPROBE_DEFER); 801 } 802 803 if (!IS_ERR(pd->dma_rx)) { 804 dma_release_channel(pd->dma_rx); 805 pd->dma_rx = ERR_PTR(-EPROBE_DEFER); 806 } 807 } 808 809 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd) 810 { 811 struct resource *res; 812 resource_size_t n; 813 int k = 0, ret; 814 815 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 816 for (n = res->start; n <= res->end; n++) { 817 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, 818 0, dev_name(&dev->dev), pd); 819 if (ret) { 820 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); 821 return ret; 822 } 823 } 824 k++; 825 } 826 827 return k > 0 ? 0 : -ENOENT; 828 } 829 830 static int sh_mobile_i2c_probe(struct platform_device *dev) 831 { 832 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev); 833 struct sh_mobile_i2c_data *pd; 834 struct i2c_adapter *adap; 835 struct resource *res; 836 int ret; 837 u32 bus_speed; 838 839 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 840 if (!pd) 841 return -ENOMEM; 842 843 pd->clk = devm_clk_get(&dev->dev, NULL); 844 if (IS_ERR(pd->clk)) { 845 dev_err(&dev->dev, "cannot get clock\n"); 846 return PTR_ERR(pd->clk); 847 } 848 849 ret = sh_mobile_i2c_hook_irqs(dev, pd); 850 if (ret) 851 return ret; 852 853 pd->dev = &dev->dev; 854 platform_set_drvdata(dev, pd); 855 856 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 857 858 pd->res = res; 859 pd->reg = devm_ioremap_resource(&dev->dev, res); 860 if (IS_ERR(pd->reg)) 861 return PTR_ERR(pd->reg); 862 863 /* Use platform data bus speed or STANDARD_MODE */ 864 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed); 865 pd->bus_speed = ret ? STANDARD_MODE : bus_speed; 866 867 pd->clks_per_count = 1; 868 869 if (dev->dev.of_node) { 870 const struct of_device_id *match; 871 872 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev); 873 if (match) { 874 const struct sh_mobile_dt_config *config; 875 876 config = match->data; 877 pd->clks_per_count = config->clks_per_count; 878 } 879 } else { 880 if (pdata && pdata->bus_speed) 881 pd->bus_speed = pdata->bus_speed; 882 if (pdata && pdata->clks_per_count) 883 pd->clks_per_count = pdata->clks_per_count; 884 } 885 886 /* The IIC blocks on SH-Mobile ARM processors 887 * come with two new bits in ICIC. 888 */ 889 if (resource_size(res) > 0x17) 890 pd->flags |= IIC_FLAG_HAS_ICIC67; 891 892 ret = sh_mobile_i2c_init(pd); 893 if (ret) 894 return ret; 895 896 /* Init DMA */ 897 sg_init_table(&pd->sg, 1); 898 pd->dma_direction = DMA_NONE; 899 pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER); 900 901 /* Enable Runtime PM for this device. 902 * 903 * Also tell the Runtime PM core to ignore children 904 * for this device since it is valid for us to suspend 905 * this I2C master driver even though the slave devices 906 * on the I2C bus may not be suspended. 907 * 908 * The state of the I2C hardware bus is unaffected by 909 * the Runtime PM state. 910 */ 911 pm_suspend_ignore_children(&dev->dev, true); 912 pm_runtime_enable(&dev->dev); 913 914 /* setup the private data */ 915 adap = &pd->adap; 916 i2c_set_adapdata(adap, pd); 917 918 adap->owner = THIS_MODULE; 919 adap->algo = &sh_mobile_i2c_algorithm; 920 adap->dev.parent = &dev->dev; 921 adap->retries = 5; 922 adap->nr = dev->id; 923 adap->dev.of_node = dev->dev.of_node; 924 925 strlcpy(adap->name, dev->name, sizeof(adap->name)); 926 927 spin_lock_init(&pd->lock); 928 init_waitqueue_head(&pd->wait); 929 930 ret = i2c_add_numbered_adapter(adap); 931 if (ret < 0) { 932 sh_mobile_i2c_release_dma(pd); 933 dev_err(&dev->dev, "cannot add numbered adapter\n"); 934 return ret; 935 } 936 937 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed); 938 939 return 0; 940 } 941 942 static int sh_mobile_i2c_remove(struct platform_device *dev) 943 { 944 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 945 946 i2c_del_adapter(&pd->adap); 947 sh_mobile_i2c_release_dma(pd); 948 pm_runtime_disable(&dev->dev); 949 return 0; 950 } 951 952 static int sh_mobile_i2c_runtime_nop(struct device *dev) 953 { 954 /* Runtime PM callback shared between ->runtime_suspend() 955 * and ->runtime_resume(). Simply returns success. 956 * 957 * This driver re-initializes all registers after 958 * pm_runtime_get_sync() anyway so there is no need 959 * to save and restore registers here. 960 */ 961 return 0; 962 } 963 964 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { 965 .runtime_suspend = sh_mobile_i2c_runtime_nop, 966 .runtime_resume = sh_mobile_i2c_runtime_nop, 967 }; 968 969 static struct platform_driver sh_mobile_i2c_driver = { 970 .driver = { 971 .name = "i2c-sh_mobile", 972 .pm = &sh_mobile_i2c_dev_pm_ops, 973 .of_match_table = sh_mobile_i2c_dt_ids, 974 }, 975 .probe = sh_mobile_i2c_probe, 976 .remove = sh_mobile_i2c_remove, 977 }; 978 979 static int __init sh_mobile_i2c_adap_init(void) 980 { 981 return platform_driver_register(&sh_mobile_i2c_driver); 982 } 983 subsys_initcall(sh_mobile_i2c_adap_init); 984 985 static void __exit sh_mobile_i2c_adap_exit(void) 986 { 987 platform_driver_unregister(&sh_mobile_i2c_driver); 988 } 989 module_exit(sh_mobile_i2c_adap_exit); 990 991 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 992 MODULE_AUTHOR("Magnus Damm and Wolfram Sang"); 993 MODULE_LICENSE("GPL v2"); 994 MODULE_ALIAS("platform:i2c-sh_mobile"); 995