1 /* 2 * SuperH Mobile I2C Controller 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * Portions of the code based on out-of-tree driver i2c-sh7343.c 7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/platform_device.h> 28 #include <linux/interrupt.h> 29 #include <linux/i2c.h> 30 #include <linux/of_i2c.h> 31 #include <linux/err.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/clk.h> 34 #include <linux/io.h> 35 #include <linux/slab.h> 36 #include <linux/i2c/i2c-sh_mobile.h> 37 38 /* Transmit operation: */ 39 /* */ 40 /* 0 byte transmit */ 41 /* BUS: S A8 ACK P(*) */ 42 /* IRQ: DTE WAIT */ 43 /* ICIC: */ 44 /* ICCR: 0x94 0x90 */ 45 /* ICDR: A8 */ 46 /* */ 47 /* 1 byte transmit */ 48 /* BUS: S A8 ACK D8(1) ACK P(*) */ 49 /* IRQ: DTE WAIT WAIT */ 50 /* ICIC: -DTE */ 51 /* ICCR: 0x94 0x90 */ 52 /* ICDR: A8 D8(1) */ 53 /* */ 54 /* 2 byte transmit */ 55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ 56 /* IRQ: DTE WAIT WAIT WAIT */ 57 /* ICIC: -DTE */ 58 /* ICCR: 0x94 0x90 */ 59 /* ICDR: A8 D8(1) D8(2) */ 60 /* */ 61 /* 3 bytes or more, +---------+ gets repeated */ 62 /* */ 63 /* */ 64 /* Receive operation: */ 65 /* */ 66 /* 0 byte receive - not supported since slave may hold SDA low */ 67 /* */ 68 /* 1 byte receive [TX] | [RX] */ 69 /* BUS: S A8 ACK | D8(1) ACK P(*) */ 70 /* IRQ: DTE WAIT | WAIT DTE */ 71 /* ICIC: -DTE | +DTE */ 72 /* ICCR: 0x94 0x81 | 0xc0 */ 73 /* ICDR: A8 | D8(1) */ 74 /* */ 75 /* 2 byte receive [TX]| [RX] */ 76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ 77 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 78 /* ICIC: -DTE | +DTE */ 79 /* ICCR: 0x94 0x81 | 0xc0 */ 80 /* ICDR: A8 | D8(1) D8(2) */ 81 /* */ 82 /* 3 byte receive [TX] | [RX] (*) */ 83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 85 /* ICIC: -DTE | +DTE */ 86 /* ICCR: 0x94 0x81 | 0xc0 */ 87 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 88 /* */ 89 /* 4 bytes or more, this part is repeated +---------+ */ 90 /* */ 91 /* */ 92 /* Interrupt order and BUSY flag */ 93 /* ___ _ */ 94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 96 /* */ 97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ 98 /* ___ */ 99 /* WAIT IRQ ________________________________/ \___________ */ 100 /* TACK IRQ ____________________________________/ \_______ */ 101 /* DTE IRQ __________________________________________/ \_ */ 102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 103 /* _______________________________________________ */ 104 /* BUSY __/ \_ */ 105 /* */ 106 /* (*) The STOP condition is only sent by the master at the end of the last */ 107 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ 108 /* only cleared after the STOP condition, so, between messages we have to */ 109 /* poll for the DTE bit. */ 110 /* */ 111 112 enum sh_mobile_i2c_op { 113 OP_START = 0, 114 OP_TX_FIRST, 115 OP_TX, 116 OP_TX_STOP, 117 OP_TX_TO_RX, 118 OP_RX, 119 OP_RX_STOP, 120 OP_RX_STOP_DATA, 121 }; 122 123 struct sh_mobile_i2c_data { 124 struct device *dev; 125 void __iomem *reg; 126 struct i2c_adapter adap; 127 unsigned long bus_speed; 128 unsigned int clks_per_count; 129 struct clk *clk; 130 u_int8_t icic; 131 u_int8_t flags; 132 u_int16_t iccl; 133 u_int16_t icch; 134 135 spinlock_t lock; 136 wait_queue_head_t wait; 137 struct i2c_msg *msg; 138 int pos; 139 int sr; 140 bool send_stop; 141 }; 142 143 #define IIC_FLAG_HAS_ICIC67 (1 << 0) 144 145 #define STANDARD_MODE 100000 146 #define FAST_MODE 400000 147 148 /* Register offsets */ 149 #define ICDR 0x00 150 #define ICCR 0x04 151 #define ICSR 0x08 152 #define ICIC 0x0c 153 #define ICCL 0x10 154 #define ICCH 0x14 155 156 /* Register bits */ 157 #define ICCR_ICE 0x80 158 #define ICCR_RACK 0x40 159 #define ICCR_TRS 0x10 160 #define ICCR_BBSY 0x04 161 #define ICCR_SCP 0x01 162 163 #define ICSR_SCLM 0x80 164 #define ICSR_SDAM 0x40 165 #define SW_DONE 0x20 166 #define ICSR_BUSY 0x10 167 #define ICSR_AL 0x08 168 #define ICSR_TACK 0x04 169 #define ICSR_WAIT 0x02 170 #define ICSR_DTE 0x01 171 172 #define ICIC_ICCLB8 0x80 173 #define ICIC_ICCHB8 0x40 174 #define ICIC_ALE 0x08 175 #define ICIC_TACKE 0x04 176 #define ICIC_WAITE 0x02 177 #define ICIC_DTEE 0x01 178 179 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 180 { 181 if (offs == ICIC) 182 data |= pd->icic; 183 184 iowrite8(data, pd->reg + offs); 185 } 186 187 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) 188 { 189 return ioread8(pd->reg + offs); 190 } 191 192 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, 193 unsigned char set, unsigned char clr) 194 { 195 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 196 } 197 198 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf, int offset) 199 { 200 /* 201 * Conditional expression: 202 * ICCL >= COUNT_CLK * (tLOW + tf) 203 * 204 * SH-Mobile IIC hardware starts counting the LOW period of 205 * the SCL signal (tLOW) as soon as it pulls the SCL line. 206 * In order to meet the tLOW timing spec, we need to take into 207 * account the fall time of SCL signal (tf). Default tf value 208 * should be 0.3 us, for safety. 209 */ 210 return (((count_khz * (tLOW + tf)) + 5000) / 10000) + offset; 211 } 212 213 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf, int offset) 214 { 215 /* 216 * Conditional expression: 217 * ICCH >= COUNT_CLK * (tHIGH + tf) 218 * 219 * SH-Mobile IIC hardware is aware of SCL transition period 'tr', 220 * and can ignore it. SH-Mobile IIC controller starts counting 221 * the HIGH period of the SCL signal (tHIGH) after the SCL input 222 * voltage increases at VIH. 223 * 224 * Afterward it turned out calculating ICCH using only tHIGH spec 225 * will result in violation of the tHD;STA timing spec. We need 226 * to take into account the fall time of SDA signal (tf) at START 227 * condition, in order to meet both tHIGH and tHD;STA specs. 228 */ 229 return (((count_khz * (tHIGH + tf)) + 5000) / 10000) + offset; 230 } 231 232 static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) 233 { 234 unsigned long i2c_clk_khz; 235 u32 tHIGH, tLOW, tf; 236 int offset; 237 238 /* Get clock rate after clock is enabled */ 239 clk_enable(pd->clk); 240 i2c_clk_khz = clk_get_rate(pd->clk) / 1000; 241 i2c_clk_khz /= pd->clks_per_count; 242 243 if (pd->bus_speed == STANDARD_MODE) { 244 tLOW = 47; /* tLOW = 4.7 us */ 245 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ 246 tf = 3; /* tf = 0.3 us */ 247 offset = 0; /* No offset */ 248 } else if (pd->bus_speed == FAST_MODE) { 249 tLOW = 13; /* tLOW = 1.3 us */ 250 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ 251 tf = 3; /* tf = 0.3 us */ 252 offset = 0; /* No offset */ 253 } else { 254 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", 255 pd->bus_speed); 256 goto out; 257 } 258 259 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf, offset); 260 /* one more bit of ICCL in ICIC */ 261 if ((pd->iccl > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67)) 262 pd->icic |= ICIC_ICCLB8; 263 else 264 pd->icic &= ~ICIC_ICCLB8; 265 266 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf, offset); 267 /* one more bit of ICCH in ICIC */ 268 if ((pd->icch > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67)) 269 pd->icic |= ICIC_ICCHB8; 270 else 271 pd->icic &= ~ICIC_ICCHB8; 272 273 out: 274 clk_disable(pd->clk); 275 } 276 277 static void activate_ch(struct sh_mobile_i2c_data *pd) 278 { 279 /* Wake up device and enable clock */ 280 pm_runtime_get_sync(pd->dev); 281 clk_enable(pd->clk); 282 283 /* Enable channel and configure rx ack */ 284 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 285 286 /* Mask all interrupts */ 287 iic_wr(pd, ICIC, 0); 288 289 /* Set the clock */ 290 iic_wr(pd, ICCL, pd->iccl & 0xff); 291 iic_wr(pd, ICCH, pd->icch & 0xff); 292 } 293 294 static void deactivate_ch(struct sh_mobile_i2c_data *pd) 295 { 296 /* Clear/disable interrupts */ 297 iic_wr(pd, ICSR, 0); 298 iic_wr(pd, ICIC, 0); 299 300 /* Disable channel */ 301 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 302 303 /* Disable clock and mark device as idle */ 304 clk_disable(pd->clk); 305 pm_runtime_put_sync(pd->dev); 306 } 307 308 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 309 enum sh_mobile_i2c_op op, unsigned char data) 310 { 311 unsigned char ret = 0; 312 unsigned long flags; 313 314 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 315 316 spin_lock_irqsave(&pd->lock, flags); 317 318 switch (op) { 319 case OP_START: /* issue start and trigger DTE interrupt */ 320 iic_wr(pd, ICCR, 0x94); 321 break; 322 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 323 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 324 iic_wr(pd, ICDR, data); 325 break; 326 case OP_TX: /* write data */ 327 iic_wr(pd, ICDR, data); 328 break; 329 case OP_TX_STOP: /* write data and issue a stop afterwards */ 330 iic_wr(pd, ICDR, data); 331 iic_wr(pd, ICCR, pd->send_stop ? 0x90 : 0x94); 332 break; 333 case OP_TX_TO_RX: /* select read mode */ 334 iic_wr(pd, ICCR, 0x81); 335 break; 336 case OP_RX: /* just read data */ 337 ret = iic_rd(pd, ICDR); 338 break; 339 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 340 iic_wr(pd, ICIC, 341 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 342 iic_wr(pd, ICCR, 0xc0); 343 break; 344 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 345 iic_wr(pd, ICIC, 346 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 347 ret = iic_rd(pd, ICDR); 348 iic_wr(pd, ICCR, 0xc0); 349 break; 350 } 351 352 spin_unlock_irqrestore(&pd->lock, flags); 353 354 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 355 return ret; 356 } 357 358 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) 359 { 360 return pd->pos == -1; 361 } 362 363 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) 364 { 365 return pd->pos == pd->msg->len - 1; 366 } 367 368 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, 369 unsigned char *buf) 370 { 371 switch (pd->pos) { 372 case -1: 373 *buf = (pd->msg->addr & 0x7f) << 1; 374 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; 375 break; 376 default: 377 *buf = pd->msg->buf[pd->pos]; 378 } 379 } 380 381 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 382 { 383 unsigned char data; 384 385 if (pd->pos == pd->msg->len) 386 return 1; 387 388 sh_mobile_i2c_get_data(pd, &data); 389 390 if (sh_mobile_i2c_is_last_byte(pd)) 391 i2c_op(pd, OP_TX_STOP, data); 392 else if (sh_mobile_i2c_is_first_byte(pd)) 393 i2c_op(pd, OP_TX_FIRST, data); 394 else 395 i2c_op(pd, OP_TX, data); 396 397 pd->pos++; 398 return 0; 399 } 400 401 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 402 { 403 unsigned char data; 404 int real_pos; 405 406 do { 407 if (pd->pos <= -1) { 408 sh_mobile_i2c_get_data(pd, &data); 409 410 if (sh_mobile_i2c_is_first_byte(pd)) 411 i2c_op(pd, OP_TX_FIRST, data); 412 else 413 i2c_op(pd, OP_TX, data); 414 break; 415 } 416 417 if (pd->pos == 0) { 418 i2c_op(pd, OP_TX_TO_RX, 0); 419 break; 420 } 421 422 real_pos = pd->pos - 2; 423 424 if (pd->pos == pd->msg->len) { 425 if (real_pos < 0) { 426 i2c_op(pd, OP_RX_STOP, 0); 427 break; 428 } 429 data = i2c_op(pd, OP_RX_STOP_DATA, 0); 430 } else 431 data = i2c_op(pd, OP_RX, 0); 432 433 if (real_pos >= 0) 434 pd->msg->buf[real_pos] = data; 435 } while (0); 436 437 pd->pos++; 438 return pd->pos == (pd->msg->len + 2); 439 } 440 441 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 442 { 443 struct platform_device *dev = dev_id; 444 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 445 unsigned char sr; 446 int wakeup; 447 448 sr = iic_rd(pd, ICSR); 449 pd->sr |= sr; /* remember state */ 450 451 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 452 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 453 pd->pos, pd->msg->len); 454 455 if (sr & (ICSR_AL | ICSR_TACK)) { 456 /* don't interrupt transaction - continue to issue stop */ 457 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 458 wakeup = 0; 459 } else if (pd->msg->flags & I2C_M_RD) 460 wakeup = sh_mobile_i2c_isr_rx(pd); 461 else 462 wakeup = sh_mobile_i2c_isr_tx(pd); 463 464 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 465 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 466 467 if (wakeup) { 468 pd->sr |= SW_DONE; 469 wake_up(&pd->wait); 470 } 471 472 /* defeat write posting to avoid spurious WAIT interrupts */ 473 iic_rd(pd, ICSR); 474 475 return IRQ_HANDLED; 476 } 477 478 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, 479 bool do_init) 480 { 481 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 482 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 483 return -EIO; 484 } 485 486 if (do_init) { 487 /* Initialize channel registers */ 488 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 489 490 /* Enable channel and configure rx ack */ 491 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 492 493 /* Set the clock */ 494 iic_wr(pd, ICCL, pd->iccl & 0xff); 495 iic_wr(pd, ICCH, pd->icch & 0xff); 496 } 497 498 pd->msg = usr_msg; 499 pd->pos = -1; 500 pd->sr = 0; 501 502 /* Enable all interrupts to begin with */ 503 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 504 return 0; 505 } 506 507 static int poll_dte(struct sh_mobile_i2c_data *pd) 508 { 509 int i; 510 511 for (i = 1000; i; i--) { 512 u_int8_t val = iic_rd(pd, ICSR); 513 514 if (val & ICSR_DTE) 515 break; 516 517 if (val & ICSR_TACK) 518 return -EIO; 519 520 udelay(10); 521 } 522 523 if (!i) { 524 dev_warn(pd->dev, "Timeout polling for DTE!\n"); 525 return -ETIMEDOUT; 526 } 527 528 return 0; 529 } 530 531 static int poll_busy(struct sh_mobile_i2c_data *pd) 532 { 533 int i; 534 535 for (i = 1000; i; i--) { 536 u_int8_t val = iic_rd(pd, ICSR); 537 538 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 539 540 /* the interrupt handler may wake us up before the 541 * transfer is finished, so poll the hardware 542 * until we're done. 543 */ 544 if (!(val & ICSR_BUSY)) { 545 /* handle missing acknowledge and arbitration lost */ 546 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) 547 return -EIO; 548 break; 549 } 550 551 udelay(10); 552 } 553 554 if (!i) { 555 dev_err(pd->dev, "Polling timed out\n"); 556 return -ETIMEDOUT; 557 } 558 559 return 0; 560 } 561 562 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 563 struct i2c_msg *msgs, 564 int num) 565 { 566 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 567 struct i2c_msg *msg; 568 int err = 0; 569 int i, k; 570 571 activate_ch(pd); 572 573 /* Process all messages */ 574 for (i = 0; i < num; i++) { 575 bool do_start = pd->send_stop || !i; 576 msg = &msgs[i]; 577 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; 578 579 err = start_ch(pd, msg, do_start); 580 if (err) 581 break; 582 583 if (do_start) 584 i2c_op(pd, OP_START, 0); 585 586 /* The interrupt handler takes care of the rest... */ 587 k = wait_event_timeout(pd->wait, 588 pd->sr & (ICSR_TACK | SW_DONE), 589 5 * HZ); 590 if (!k) { 591 dev_err(pd->dev, "Transfer request timed out\n"); 592 err = -ETIMEDOUT; 593 break; 594 } 595 596 if (pd->send_stop) 597 err = poll_busy(pd); 598 else 599 err = poll_dte(pd); 600 if (err < 0) 601 break; 602 } 603 604 deactivate_ch(pd); 605 606 if (!err) 607 err = num; 608 return err; 609 } 610 611 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 612 { 613 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 614 } 615 616 static struct i2c_algorithm sh_mobile_i2c_algorithm = { 617 .functionality = sh_mobile_i2c_func, 618 .master_xfer = sh_mobile_i2c_xfer, 619 }; 620 621 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook) 622 { 623 struct resource *res; 624 int ret = -ENXIO; 625 int n, k = 0; 626 627 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 628 for (n = res->start; hook && n <= res->end; n++) { 629 if (request_irq(n, sh_mobile_i2c_isr, 0, 630 dev_name(&dev->dev), dev)) { 631 for (n--; n >= res->start; n--) 632 free_irq(n, dev); 633 634 goto rollback; 635 } 636 } 637 k++; 638 } 639 640 if (hook) 641 return k > 0 ? 0 : -ENOENT; 642 643 ret = 0; 644 645 rollback: 646 k--; 647 648 while (k >= 0) { 649 res = platform_get_resource(dev, IORESOURCE_IRQ, k); 650 for (n = res->start; n <= res->end; n++) 651 free_irq(n, dev); 652 653 k--; 654 } 655 656 return ret; 657 } 658 659 static int sh_mobile_i2c_probe(struct platform_device *dev) 660 { 661 struct i2c_sh_mobile_platform_data *pdata = dev->dev.platform_data; 662 struct sh_mobile_i2c_data *pd; 663 struct i2c_adapter *adap; 664 struct resource *res; 665 int size; 666 int ret; 667 668 pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 669 if (pd == NULL) { 670 dev_err(&dev->dev, "cannot allocate private data\n"); 671 return -ENOMEM; 672 } 673 674 pd->clk = clk_get(&dev->dev, NULL); 675 if (IS_ERR(pd->clk)) { 676 dev_err(&dev->dev, "cannot get clock\n"); 677 ret = PTR_ERR(pd->clk); 678 goto err; 679 } 680 681 ret = sh_mobile_i2c_hook_irqs(dev, 1); 682 if (ret) { 683 dev_err(&dev->dev, "cannot request IRQ\n"); 684 goto err_clk; 685 } 686 687 pd->dev = &dev->dev; 688 platform_set_drvdata(dev, pd); 689 690 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 691 if (res == NULL) { 692 dev_err(&dev->dev, "cannot find IO resource\n"); 693 ret = -ENOENT; 694 goto err_irq; 695 } 696 697 size = resource_size(res); 698 699 pd->reg = ioremap(res->start, size); 700 if (pd->reg == NULL) { 701 dev_err(&dev->dev, "cannot map IO\n"); 702 ret = -ENXIO; 703 goto err_irq; 704 } 705 706 /* Use platform data bus speed or STANDARD_MODE */ 707 pd->bus_speed = STANDARD_MODE; 708 if (pdata && pdata->bus_speed) 709 pd->bus_speed = pdata->bus_speed; 710 pd->clks_per_count = 1; 711 if (pdata && pdata->clks_per_count) 712 pd->clks_per_count = pdata->clks_per_count; 713 714 /* The IIC blocks on SH-Mobile ARM processors 715 * come with two new bits in ICIC. 716 */ 717 if (size > 0x17) 718 pd->flags |= IIC_FLAG_HAS_ICIC67; 719 720 sh_mobile_i2c_init(pd); 721 722 /* Enable Runtime PM for this device. 723 * 724 * Also tell the Runtime PM core to ignore children 725 * for this device since it is valid for us to suspend 726 * this I2C master driver even though the slave devices 727 * on the I2C bus may not be suspended. 728 * 729 * The state of the I2C hardware bus is unaffected by 730 * the Runtime PM state. 731 */ 732 pm_suspend_ignore_children(&dev->dev, true); 733 pm_runtime_enable(&dev->dev); 734 735 /* setup the private data */ 736 adap = &pd->adap; 737 i2c_set_adapdata(adap, pd); 738 739 adap->owner = THIS_MODULE; 740 adap->algo = &sh_mobile_i2c_algorithm; 741 adap->dev.parent = &dev->dev; 742 adap->retries = 5; 743 adap->nr = dev->id; 744 adap->dev.of_node = dev->dev.of_node; 745 746 strlcpy(adap->name, dev->name, sizeof(adap->name)); 747 748 spin_lock_init(&pd->lock); 749 init_waitqueue_head(&pd->wait); 750 751 ret = i2c_add_numbered_adapter(adap); 752 if (ret < 0) { 753 dev_err(&dev->dev, "cannot add numbered adapter\n"); 754 goto err_all; 755 } 756 757 dev_info(&dev->dev, 758 "I2C adapter %d with bus speed %lu Hz (L/H=%x/%x)\n", 759 adap->nr, pd->bus_speed, pd->iccl, pd->icch); 760 761 of_i2c_register_devices(adap); 762 return 0; 763 764 err_all: 765 iounmap(pd->reg); 766 err_irq: 767 sh_mobile_i2c_hook_irqs(dev, 0); 768 err_clk: 769 clk_put(pd->clk); 770 err: 771 kfree(pd); 772 return ret; 773 } 774 775 static int sh_mobile_i2c_remove(struct platform_device *dev) 776 { 777 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 778 779 i2c_del_adapter(&pd->adap); 780 iounmap(pd->reg); 781 sh_mobile_i2c_hook_irqs(dev, 0); 782 clk_put(pd->clk); 783 pm_runtime_disable(&dev->dev); 784 kfree(pd); 785 return 0; 786 } 787 788 static int sh_mobile_i2c_runtime_nop(struct device *dev) 789 { 790 /* Runtime PM callback shared between ->runtime_suspend() 791 * and ->runtime_resume(). Simply returns success. 792 * 793 * This driver re-initializes all registers after 794 * pm_runtime_get_sync() anyway so there is no need 795 * to save and restore registers here. 796 */ 797 return 0; 798 } 799 800 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { 801 .runtime_suspend = sh_mobile_i2c_runtime_nop, 802 .runtime_resume = sh_mobile_i2c_runtime_nop, 803 }; 804 805 static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 806 { .compatible = "renesas,rmobile-iic", }, 807 {}, 808 }; 809 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 810 811 static struct platform_driver sh_mobile_i2c_driver = { 812 .driver = { 813 .name = "i2c-sh_mobile", 814 .owner = THIS_MODULE, 815 .pm = &sh_mobile_i2c_dev_pm_ops, 816 .of_match_table = sh_mobile_i2c_dt_ids, 817 }, 818 .probe = sh_mobile_i2c_probe, 819 .remove = sh_mobile_i2c_remove, 820 }; 821 822 static int __init sh_mobile_i2c_adap_init(void) 823 { 824 return platform_driver_register(&sh_mobile_i2c_driver); 825 } 826 827 static void __exit sh_mobile_i2c_adap_exit(void) 828 { 829 platform_driver_unregister(&sh_mobile_i2c_driver); 830 } 831 832 subsys_initcall(sh_mobile_i2c_adap_init); 833 module_exit(sh_mobile_i2c_adap_exit); 834 835 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 836 MODULE_AUTHOR("Magnus Damm"); 837 MODULE_LICENSE("GPL v2"); 838 MODULE_ALIAS("platform:i2c-sh_mobile"); 839