1 /*
2  * SuperH Mobile I2C Controller
3  *
4  * Copyright (C) 2008 Magnus Damm
5  *
6  * Portions of the code based on out-of-tree driver i2c-sh7343.c
7  * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21  */
22 
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/err.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/clk.h>
33 #include <linux/io.h>
34 #include <linux/slab.h>
35 #include <linux/i2c/i2c-sh_mobile.h>
36 
37 /* Transmit operation:                                                      */
38 /*                                                                          */
39 /* 0 byte transmit                                                          */
40 /* BUS:     S     A8     ACK   P(*)                                         */
41 /* IRQ:       DTE   WAIT                                                    */
42 /* ICIC:                                                                    */
43 /* ICCR: 0x94 0x90                                                          */
44 /* ICDR:      A8                                                            */
45 /*                                                                          */
46 /* 1 byte transmit                                                          */
47 /* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
48 /* IRQ:       DTE   WAIT         WAIT                                       */
49 /* ICIC:      -DTE                                                          */
50 /* ICCR: 0x94       0x90                                                    */
51 /* ICDR:      A8    D8(1)                                                   */
52 /*                                                                          */
53 /* 2 byte transmit                                                          */
54 /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
55 /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
56 /* ICIC:      -DTE                                                          */
57 /* ICCR: 0x94                    0x90                                       */
58 /* ICDR:      A8    D8(1)        D8(2)                                      */
59 /*                                                                          */
60 /* 3 bytes or more, +---------+ gets repeated                               */
61 /*                                                                          */
62 /*                                                                          */
63 /* Receive operation:                                                       */
64 /*                                                                          */
65 /* 0 byte receive - not supported since slave may hold SDA low              */
66 /*                                                                          */
67 /* 1 byte receive       [TX] | [RX]                                         */
68 /* BUS:     S     A8     ACK | D8(1)   ACK   P(*)                           */
69 /* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
70 /* ICIC:      -DTE           |   +DTE                                       */
71 /* ICCR: 0x94       0x81     |   0xc0                                       */
72 /* ICDR:      A8             |            D8(1)                             */
73 /*                                                                          */
74 /* 2 byte receive        [TX]| [RX]                                         */
75 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P(*)             */
76 /* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
77 /* ICIC:      -DTE           |                 +DTE                         */
78 /* ICCR: 0x94       0x81     |                 0xc0                         */
79 /* ICDR:      A8             |                 D8(1)    D8(2)               */
80 /*                                                                          */
81 /* 3 byte receive       [TX] | [RX]                                     (*) */
82 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
83 /* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
84 /* ICIC:      -DTE           |                              +DTE            */
85 /* ICCR: 0x94       0x81     |                              0xc0            */
86 /* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
87 /*                                                                          */
88 /* 4 bytes or more, this part is repeated    +---------+                    */
89 /*                                                                          */
90 /*                                                                          */
91 /* Interrupt order and BUSY flag                                            */
92 /*     ___                                                 _                */
93 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
94 /* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
95 /*                                                                          */
96 /*        S   D7  D6  D5  D4  D3  D2  D1  D0              P(*)              */
97 /*                                           ___                            */
98 /* WAIT IRQ ________________________________/   \___________                */
99 /* TACK IRQ ____________________________________/   \_______                */
100 /* DTE  IRQ __________________________________________/   \_                */
101 /* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
102 /*         _______________________________________________                  */
103 /* BUSY __/                                               \_                */
104 /*                                                                          */
105 /* (*) The STOP condition is only sent by the master at the end of the last */
106 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
107 /* only cleared after the STOP condition, so, between messages we have to   */
108 /* poll for the DTE bit.                                                    */
109 /*                                                                          */
110 
111 enum sh_mobile_i2c_op {
112 	OP_START = 0,
113 	OP_TX_FIRST,
114 	OP_TX,
115 	OP_TX_STOP,
116 	OP_TX_TO_RX,
117 	OP_RX,
118 	OP_RX_STOP,
119 	OP_RX_STOP_DATA,
120 };
121 
122 struct sh_mobile_i2c_data {
123 	struct device *dev;
124 	void __iomem *reg;
125 	struct i2c_adapter adap;
126 	unsigned long bus_speed;
127 	unsigned int clks_per_count;
128 	struct clk *clk;
129 	u_int8_t icic;
130 	u_int8_t flags;
131 	u_int16_t iccl;
132 	u_int16_t icch;
133 
134 	spinlock_t lock;
135 	wait_queue_head_t wait;
136 	struct i2c_msg *msg;
137 	int pos;
138 	int sr;
139 	bool send_stop;
140 };
141 
142 #define IIC_FLAG_HAS_ICIC67	(1 << 0)
143 
144 #define STANDARD_MODE		100000
145 #define FAST_MODE		400000
146 
147 /* Register offsets */
148 #define ICDR			0x00
149 #define ICCR			0x04
150 #define ICSR			0x08
151 #define ICIC			0x0c
152 #define ICCL			0x10
153 #define ICCH			0x14
154 
155 /* Register bits */
156 #define ICCR_ICE		0x80
157 #define ICCR_RACK		0x40
158 #define ICCR_TRS		0x10
159 #define ICCR_BBSY		0x04
160 #define ICCR_SCP		0x01
161 
162 #define ICSR_SCLM		0x80
163 #define ICSR_SDAM		0x40
164 #define SW_DONE			0x20
165 #define ICSR_BUSY		0x10
166 #define ICSR_AL			0x08
167 #define ICSR_TACK		0x04
168 #define ICSR_WAIT		0x02
169 #define ICSR_DTE		0x01
170 
171 #define ICIC_ICCLB8		0x80
172 #define ICIC_ICCHB8		0x40
173 #define ICIC_ALE		0x08
174 #define ICIC_TACKE		0x04
175 #define ICIC_WAITE		0x02
176 #define ICIC_DTEE		0x01
177 
178 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
179 {
180 	if (offs == ICIC)
181 		data |= pd->icic;
182 
183 	iowrite8(data, pd->reg + offs);
184 }
185 
186 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
187 {
188 	return ioread8(pd->reg + offs);
189 }
190 
191 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
192 			unsigned char set, unsigned char clr)
193 {
194 	iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
195 }
196 
197 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf, int offset)
198 {
199 	/*
200 	 * Conditional expression:
201 	 *   ICCL >= COUNT_CLK * (tLOW + tf)
202 	 *
203 	 * SH-Mobile IIC hardware starts counting the LOW period of
204 	 * the SCL signal (tLOW) as soon as it pulls the SCL line.
205 	 * In order to meet the tLOW timing spec, we need to take into
206 	 * account the fall time of SCL signal (tf).  Default tf value
207 	 * should be 0.3 us, for safety.
208 	 */
209 	return (((count_khz * (tLOW + tf)) + 5000) / 10000) + offset;
210 }
211 
212 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf, int offset)
213 {
214 	/*
215 	 * Conditional expression:
216 	 *   ICCH >= COUNT_CLK * (tHIGH + tf)
217 	 *
218 	 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
219 	 * and can ignore it.  SH-Mobile IIC controller starts counting
220 	 * the HIGH period of the SCL signal (tHIGH) after the SCL input
221 	 * voltage increases at VIH.
222 	 *
223 	 * Afterward it turned out calculating ICCH using only tHIGH spec
224 	 * will result in violation of the tHD;STA timing spec.  We need
225 	 * to take into account the fall time of SDA signal (tf) at START
226 	 * condition, in order to meet both tHIGH and tHD;STA specs.
227 	 */
228 	return (((count_khz * (tHIGH + tf)) + 5000) / 10000) + offset;
229 }
230 
231 static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
232 {
233 	unsigned long i2c_clk_khz;
234 	u32 tHIGH, tLOW, tf;
235 	int offset;
236 
237 	/* Get clock rate after clock is enabled */
238 	clk_enable(pd->clk);
239 	i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
240 	i2c_clk_khz /= pd->clks_per_count;
241 
242 	if (pd->bus_speed == STANDARD_MODE) {
243 		tLOW	= 47;	/* tLOW = 4.7 us */
244 		tHIGH	= 40;	/* tHD;STA = tHIGH = 4.0 us */
245 		tf	= 3;	/* tf = 0.3 us */
246 		offset	= 0;	/* No offset */
247 	} else if (pd->bus_speed == FAST_MODE) {
248 		tLOW	= 13;	/* tLOW = 1.3 us */
249 		tHIGH	= 6;	/* tHD;STA = tHIGH = 0.6 us */
250 		tf	= 3;	/* tf = 0.3 us */
251 		offset	= 0;	/* No offset */
252 	} else {
253 		dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
254 			pd->bus_speed);
255 		goto out;
256 	}
257 
258 	pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf, offset);
259 	/* one more bit of ICCL in ICIC */
260 	if ((pd->iccl > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67))
261 		pd->icic |= ICIC_ICCLB8;
262 	else
263 		pd->icic &= ~ICIC_ICCLB8;
264 
265 	pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf, offset);
266 	/* one more bit of ICCH in ICIC */
267 	if ((pd->icch > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67))
268 		pd->icic |= ICIC_ICCHB8;
269 	else
270 		pd->icic &= ~ICIC_ICCHB8;
271 
272 out:
273 	clk_disable(pd->clk);
274 }
275 
276 static void activate_ch(struct sh_mobile_i2c_data *pd)
277 {
278 	/* Wake up device and enable clock */
279 	pm_runtime_get_sync(pd->dev);
280 	clk_enable(pd->clk);
281 
282 	/* Enable channel and configure rx ack */
283 	iic_set_clr(pd, ICCR, ICCR_ICE, 0);
284 
285 	/* Mask all interrupts */
286 	iic_wr(pd, ICIC, 0);
287 
288 	/* Set the clock */
289 	iic_wr(pd, ICCL, pd->iccl & 0xff);
290 	iic_wr(pd, ICCH, pd->icch & 0xff);
291 }
292 
293 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
294 {
295 	/* Clear/disable interrupts */
296 	iic_wr(pd, ICSR, 0);
297 	iic_wr(pd, ICIC, 0);
298 
299 	/* Disable channel */
300 	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
301 
302 	/* Disable clock and mark device as idle */
303 	clk_disable(pd->clk);
304 	pm_runtime_put_sync(pd->dev);
305 }
306 
307 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
308 			    enum sh_mobile_i2c_op op, unsigned char data)
309 {
310 	unsigned char ret = 0;
311 	unsigned long flags;
312 
313 	dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
314 
315 	spin_lock_irqsave(&pd->lock, flags);
316 
317 	switch (op) {
318 	case OP_START: /* issue start and trigger DTE interrupt */
319 		iic_wr(pd, ICCR, 0x94);
320 		break;
321 	case OP_TX_FIRST: /* disable DTE interrupt and write data */
322 		iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
323 		iic_wr(pd, ICDR, data);
324 		break;
325 	case OP_TX: /* write data */
326 		iic_wr(pd, ICDR, data);
327 		break;
328 	case OP_TX_STOP: /* write data and issue a stop afterwards */
329 		iic_wr(pd, ICDR, data);
330 		iic_wr(pd, ICCR, pd->send_stop ? 0x90 : 0x94);
331 		break;
332 	case OP_TX_TO_RX: /* select read mode */
333 		iic_wr(pd, ICCR, 0x81);
334 		break;
335 	case OP_RX: /* just read data */
336 		ret = iic_rd(pd, ICDR);
337 		break;
338 	case OP_RX_STOP: /* enable DTE interrupt, issue stop */
339 		iic_wr(pd, ICIC,
340 		       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
341 		iic_wr(pd, ICCR, 0xc0);
342 		break;
343 	case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
344 		iic_wr(pd, ICIC,
345 		       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
346 		ret = iic_rd(pd, ICDR);
347 		iic_wr(pd, ICCR, 0xc0);
348 		break;
349 	}
350 
351 	spin_unlock_irqrestore(&pd->lock, flags);
352 
353 	dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
354 	return ret;
355 }
356 
357 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
358 {
359 	return pd->pos == -1;
360 }
361 
362 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
363 {
364 	return pd->pos == pd->msg->len - 1;
365 }
366 
367 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
368 				   unsigned char *buf)
369 {
370 	switch (pd->pos) {
371 	case -1:
372 		*buf = (pd->msg->addr & 0x7f) << 1;
373 		*buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
374 		break;
375 	default:
376 		*buf = pd->msg->buf[pd->pos];
377 	}
378 }
379 
380 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
381 {
382 	unsigned char data;
383 
384 	if (pd->pos == pd->msg->len)
385 		return 1;
386 
387 	sh_mobile_i2c_get_data(pd, &data);
388 
389 	if (sh_mobile_i2c_is_last_byte(pd))
390 		i2c_op(pd, OP_TX_STOP, data);
391 	else if (sh_mobile_i2c_is_first_byte(pd))
392 		i2c_op(pd, OP_TX_FIRST, data);
393 	else
394 		i2c_op(pd, OP_TX, data);
395 
396 	pd->pos++;
397 	return 0;
398 }
399 
400 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
401 {
402 	unsigned char data;
403 	int real_pos;
404 
405 	do {
406 		if (pd->pos <= -1) {
407 			sh_mobile_i2c_get_data(pd, &data);
408 
409 			if (sh_mobile_i2c_is_first_byte(pd))
410 				i2c_op(pd, OP_TX_FIRST, data);
411 			else
412 				i2c_op(pd, OP_TX, data);
413 			break;
414 		}
415 
416 		if (pd->pos == 0) {
417 			i2c_op(pd, OP_TX_TO_RX, 0);
418 			break;
419 		}
420 
421 		real_pos = pd->pos - 2;
422 
423 		if (pd->pos == pd->msg->len) {
424 			if (real_pos < 0) {
425 				i2c_op(pd, OP_RX_STOP, 0);
426 				break;
427 			}
428 			data = i2c_op(pd, OP_RX_STOP_DATA, 0);
429 		} else
430 			data = i2c_op(pd, OP_RX, 0);
431 
432 		if (real_pos >= 0)
433 			pd->msg->buf[real_pos] = data;
434 	} while (0);
435 
436 	pd->pos++;
437 	return pd->pos == (pd->msg->len + 2);
438 }
439 
440 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
441 {
442 	struct platform_device *dev = dev_id;
443 	struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
444 	unsigned char sr;
445 	int wakeup;
446 
447 	sr = iic_rd(pd, ICSR);
448 	pd->sr |= sr; /* remember state */
449 
450 	dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
451 	       (pd->msg->flags & I2C_M_RD) ? "read" : "write",
452 	       pd->pos, pd->msg->len);
453 
454 	if (sr & (ICSR_AL | ICSR_TACK)) {
455 		/* don't interrupt transaction - continue to issue stop */
456 		iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
457 		wakeup = 0;
458 	} else if (pd->msg->flags & I2C_M_RD)
459 		wakeup = sh_mobile_i2c_isr_rx(pd);
460 	else
461 		wakeup = sh_mobile_i2c_isr_tx(pd);
462 
463 	if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
464 		iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
465 
466 	if (wakeup) {
467 		pd->sr |= SW_DONE;
468 		wake_up(&pd->wait);
469 	}
470 
471 	/* defeat write posting to avoid spurious WAIT interrupts */
472 	iic_rd(pd, ICSR);
473 
474 	return IRQ_HANDLED;
475 }
476 
477 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
478 		    bool do_init)
479 {
480 	if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
481 		dev_err(pd->dev, "Unsupported zero length i2c read\n");
482 		return -EIO;
483 	}
484 
485 	if (do_init) {
486 		/* Initialize channel registers */
487 		iic_set_clr(pd, ICCR, 0, ICCR_ICE);
488 
489 		/* Enable channel and configure rx ack */
490 		iic_set_clr(pd, ICCR, ICCR_ICE, 0);
491 
492 		/* Set the clock */
493 		iic_wr(pd, ICCL, pd->iccl & 0xff);
494 		iic_wr(pd, ICCH, pd->icch & 0xff);
495 	}
496 
497 	pd->msg = usr_msg;
498 	pd->pos = -1;
499 	pd->sr = 0;
500 
501 	/* Enable all interrupts to begin with */
502 	iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
503 	return 0;
504 }
505 
506 static int poll_dte(struct sh_mobile_i2c_data *pd)
507 {
508 	int i;
509 
510 	for (i = 1000; i; i--) {
511 		u_int8_t val = iic_rd(pd, ICSR);
512 
513 		if (val & ICSR_DTE)
514 			break;
515 
516 		if (val & ICSR_TACK)
517 			return -EIO;
518 
519 		udelay(10);
520 	}
521 
522 	if (!i) {
523 		dev_warn(pd->dev, "Timeout polling for DTE!\n");
524 		return -ETIMEDOUT;
525 	}
526 
527 	return 0;
528 }
529 
530 static int poll_busy(struct sh_mobile_i2c_data *pd)
531 {
532 	int i;
533 
534 	for (i = 1000; i; i--) {
535 		u_int8_t val = iic_rd(pd, ICSR);
536 
537 		dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
538 
539 		/* the interrupt handler may wake us up before the
540 		 * transfer is finished, so poll the hardware
541 		 * until we're done.
542 		 */
543 		if (!(val & ICSR_BUSY)) {
544 			/* handle missing acknowledge and arbitration lost */
545 			if ((val | pd->sr) & (ICSR_TACK | ICSR_AL))
546 				return -EIO;
547 			break;
548 		}
549 
550 		udelay(10);
551 	}
552 
553 	if (!i) {
554 		dev_err(pd->dev, "Polling timed out\n");
555 		return -ETIMEDOUT;
556 	}
557 
558 	return 0;
559 }
560 
561 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
562 			      struct i2c_msg *msgs,
563 			      int num)
564 {
565 	struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
566 	struct i2c_msg	*msg;
567 	int err = 0;
568 	int i, k;
569 
570 	activate_ch(pd);
571 
572 	/* Process all messages */
573 	for (i = 0; i < num; i++) {
574 		bool do_start = pd->send_stop || !i;
575 		msg = &msgs[i];
576 		pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
577 
578 		err = start_ch(pd, msg, do_start);
579 		if (err)
580 			break;
581 
582 		if (do_start)
583 			i2c_op(pd, OP_START, 0);
584 
585 		/* The interrupt handler takes care of the rest... */
586 		k = wait_event_timeout(pd->wait,
587 				       pd->sr & (ICSR_TACK | SW_DONE),
588 				       5 * HZ);
589 		if (!k) {
590 			dev_err(pd->dev, "Transfer request timed out\n");
591 			err = -ETIMEDOUT;
592 			break;
593 		}
594 
595 		if (pd->send_stop)
596 			err = poll_busy(pd);
597 		else
598 			err = poll_dte(pd);
599 		if (err < 0)
600 			break;
601 	}
602 
603 	deactivate_ch(pd);
604 
605 	if (!err)
606 		err = num;
607 	return err;
608 }
609 
610 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
611 {
612 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
613 }
614 
615 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
616 	.functionality	= sh_mobile_i2c_func,
617 	.master_xfer	= sh_mobile_i2c_xfer,
618 };
619 
620 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
621 {
622 	struct resource *res;
623 	int ret = -ENXIO;
624 	int n, k = 0;
625 
626 	while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
627 		for (n = res->start; hook && n <= res->end; n++) {
628 			if (request_irq(n, sh_mobile_i2c_isr, 0,
629 					dev_name(&dev->dev), dev)) {
630 				for (n--; n >= res->start; n--)
631 					free_irq(n, dev);
632 
633 				goto rollback;
634 			}
635 		}
636 		k++;
637 	}
638 
639 	if (hook)
640 		return k > 0 ? 0 : -ENOENT;
641 
642 	ret = 0;
643 
644  rollback:
645 	k--;
646 
647 	while (k >= 0) {
648 		res = platform_get_resource(dev, IORESOURCE_IRQ, k);
649 		for (n = res->start; n <= res->end; n++)
650 			free_irq(n, dev);
651 
652 		k--;
653 	}
654 
655 	return ret;
656 }
657 
658 static int sh_mobile_i2c_probe(struct platform_device *dev)
659 {
660 	struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
661 	struct sh_mobile_i2c_data *pd;
662 	struct i2c_adapter *adap;
663 	struct resource *res;
664 	int size;
665 	int ret;
666 
667 	pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
668 	if (pd == NULL) {
669 		dev_err(&dev->dev, "cannot allocate private data\n");
670 		return -ENOMEM;
671 	}
672 
673 	pd->clk = clk_get(&dev->dev, NULL);
674 	if (IS_ERR(pd->clk)) {
675 		dev_err(&dev->dev, "cannot get clock\n");
676 		ret = PTR_ERR(pd->clk);
677 		goto err;
678 	}
679 
680 	ret = sh_mobile_i2c_hook_irqs(dev, 1);
681 	if (ret) {
682 		dev_err(&dev->dev, "cannot request IRQ\n");
683 		goto err_clk;
684 	}
685 
686 	pd->dev = &dev->dev;
687 	platform_set_drvdata(dev, pd);
688 
689 	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
690 	if (res == NULL) {
691 		dev_err(&dev->dev, "cannot find IO resource\n");
692 		ret = -ENOENT;
693 		goto err_irq;
694 	}
695 
696 	size = resource_size(res);
697 
698 	pd->reg = ioremap(res->start, size);
699 	if (pd->reg == NULL) {
700 		dev_err(&dev->dev, "cannot map IO\n");
701 		ret = -ENXIO;
702 		goto err_irq;
703 	}
704 
705 	/* Use platform data bus speed or STANDARD_MODE */
706 	pd->bus_speed = STANDARD_MODE;
707 	if (pdata && pdata->bus_speed)
708 		pd->bus_speed = pdata->bus_speed;
709 	pd->clks_per_count = 1;
710 	if (pdata && pdata->clks_per_count)
711 		pd->clks_per_count = pdata->clks_per_count;
712 
713 	/* The IIC blocks on SH-Mobile ARM processors
714 	 * come with two new bits in ICIC.
715 	 */
716 	if (size > 0x17)
717 		pd->flags |= IIC_FLAG_HAS_ICIC67;
718 
719 	sh_mobile_i2c_init(pd);
720 
721 	/* Enable Runtime PM for this device.
722 	 *
723 	 * Also tell the Runtime PM core to ignore children
724 	 * for this device since it is valid for us to suspend
725 	 * this I2C master driver even though the slave devices
726 	 * on the I2C bus may not be suspended.
727 	 *
728 	 * The state of the I2C hardware bus is unaffected by
729 	 * the Runtime PM state.
730 	 */
731 	pm_suspend_ignore_children(&dev->dev, true);
732 	pm_runtime_enable(&dev->dev);
733 
734 	/* setup the private data */
735 	adap = &pd->adap;
736 	i2c_set_adapdata(adap, pd);
737 
738 	adap->owner = THIS_MODULE;
739 	adap->algo = &sh_mobile_i2c_algorithm;
740 	adap->dev.parent = &dev->dev;
741 	adap->retries = 5;
742 	adap->nr = dev->id;
743 	adap->dev.of_node = dev->dev.of_node;
744 
745 	strlcpy(adap->name, dev->name, sizeof(adap->name));
746 
747 	spin_lock_init(&pd->lock);
748 	init_waitqueue_head(&pd->wait);
749 
750 	ret = i2c_add_numbered_adapter(adap);
751 	if (ret < 0) {
752 		dev_err(&dev->dev, "cannot add numbered adapter\n");
753 		goto err_all;
754 	}
755 
756 	dev_info(&dev->dev,
757 		 "I2C adapter %d with bus speed %lu Hz (L/H=%x/%x)\n",
758 		 adap->nr, pd->bus_speed, pd->iccl, pd->icch);
759 
760 	return 0;
761 
762  err_all:
763 	iounmap(pd->reg);
764  err_irq:
765 	sh_mobile_i2c_hook_irqs(dev, 0);
766  err_clk:
767 	clk_put(pd->clk);
768  err:
769 	kfree(pd);
770 	return ret;
771 }
772 
773 static int sh_mobile_i2c_remove(struct platform_device *dev)
774 {
775 	struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
776 
777 	i2c_del_adapter(&pd->adap);
778 	iounmap(pd->reg);
779 	sh_mobile_i2c_hook_irqs(dev, 0);
780 	clk_put(pd->clk);
781 	pm_runtime_disable(&dev->dev);
782 	kfree(pd);
783 	return 0;
784 }
785 
786 static int sh_mobile_i2c_runtime_nop(struct device *dev)
787 {
788 	/* Runtime PM callback shared between ->runtime_suspend()
789 	 * and ->runtime_resume(). Simply returns success.
790 	 *
791 	 * This driver re-initializes all registers after
792 	 * pm_runtime_get_sync() anyway so there is no need
793 	 * to save and restore registers here.
794 	 */
795 	return 0;
796 }
797 
798 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
799 	.runtime_suspend = sh_mobile_i2c_runtime_nop,
800 	.runtime_resume = sh_mobile_i2c_runtime_nop,
801 };
802 
803 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
804 	{ .compatible = "renesas,rmobile-iic", },
805 	{},
806 };
807 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
808 
809 static struct platform_driver sh_mobile_i2c_driver = {
810 	.driver		= {
811 		.name		= "i2c-sh_mobile",
812 		.owner		= THIS_MODULE,
813 		.pm		= &sh_mobile_i2c_dev_pm_ops,
814 		.of_match_table = sh_mobile_i2c_dt_ids,
815 	},
816 	.probe		= sh_mobile_i2c_probe,
817 	.remove		= sh_mobile_i2c_remove,
818 };
819 
820 static int __init sh_mobile_i2c_adap_init(void)
821 {
822 	return platform_driver_register(&sh_mobile_i2c_driver);
823 }
824 
825 static void __exit sh_mobile_i2c_adap_exit(void)
826 {
827 	platform_driver_unregister(&sh_mobile_i2c_driver);
828 }
829 
830 subsys_initcall(sh_mobile_i2c_adap_init);
831 module_exit(sh_mobile_i2c_adap_exit);
832 
833 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
834 MODULE_AUTHOR("Magnus Damm");
835 MODULE_LICENSE("GPL v2");
836 MODULE_ALIAS("platform:i2c-sh_mobile");
837