1 /* 2 * SuperH Mobile I2C Controller 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * Portions of the code based on out-of-tree driver i2c-sh7343.c 7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/platform_device.h> 28 #include <linux/interrupt.h> 29 #include <linux/i2c.h> 30 #include <linux/of_i2c.h> 31 #include <linux/err.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/clk.h> 34 #include <linux/io.h> 35 #include <linux/slab.h> 36 #include <linux/i2c/i2c-sh_mobile.h> 37 38 /* Transmit operation: */ 39 /* */ 40 /* 0 byte transmit */ 41 /* BUS: S A8 ACK P */ 42 /* IRQ: DTE WAIT */ 43 /* ICIC: */ 44 /* ICCR: 0x94 0x90 */ 45 /* ICDR: A8 */ 46 /* */ 47 /* 1 byte transmit */ 48 /* BUS: S A8 ACK D8(1) ACK P */ 49 /* IRQ: DTE WAIT WAIT */ 50 /* ICIC: -DTE */ 51 /* ICCR: 0x94 0x90 */ 52 /* ICDR: A8 D8(1) */ 53 /* */ 54 /* 2 byte transmit */ 55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */ 56 /* IRQ: DTE WAIT WAIT WAIT */ 57 /* ICIC: -DTE */ 58 /* ICCR: 0x94 0x90 */ 59 /* ICDR: A8 D8(1) D8(2) */ 60 /* */ 61 /* 3 bytes or more, +---------+ gets repeated */ 62 /* */ 63 /* */ 64 /* Receive operation: */ 65 /* */ 66 /* 0 byte receive - not supported since slave may hold SDA low */ 67 /* */ 68 /* 1 byte receive [TX] | [RX] */ 69 /* BUS: S A8 ACK | D8(1) ACK P */ 70 /* IRQ: DTE WAIT | WAIT DTE */ 71 /* ICIC: -DTE | +DTE */ 72 /* ICCR: 0x94 0x81 | 0xc0 */ 73 /* ICDR: A8 | D8(1) */ 74 /* */ 75 /* 2 byte receive [TX]| [RX] */ 76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */ 77 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 78 /* ICIC: -DTE | +DTE */ 79 /* ICCR: 0x94 0x81 | 0xc0 */ 80 /* ICDR: A8 | D8(1) D8(2) */ 81 /* */ 82 /* 3 byte receive [TX] | [RX] */ 83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 85 /* ICIC: -DTE | +DTE */ 86 /* ICCR: 0x94 0x81 | 0xc0 */ 87 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 88 /* */ 89 /* 4 bytes or more, this part is repeated +---------+ */ 90 /* */ 91 /* */ 92 /* Interrupt order and BUSY flag */ 93 /* ___ _ */ 94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 96 /* */ 97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P */ 98 /* ___ */ 99 /* WAIT IRQ ________________________________/ \___________ */ 100 /* TACK IRQ ____________________________________/ \_______ */ 101 /* DTE IRQ __________________________________________/ \_ */ 102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 103 /* _______________________________________________ */ 104 /* BUSY __/ \_ */ 105 /* */ 106 107 enum sh_mobile_i2c_op { 108 OP_START = 0, 109 OP_TX_FIRST, 110 OP_TX, 111 OP_TX_STOP, 112 OP_TX_TO_RX, 113 OP_RX, 114 OP_RX_STOP, 115 OP_RX_STOP_DATA, 116 }; 117 118 struct sh_mobile_i2c_data { 119 struct device *dev; 120 void __iomem *reg; 121 struct i2c_adapter adap; 122 unsigned long bus_speed; 123 unsigned int clks_per_count; 124 struct clk *clk; 125 u_int8_t icic; 126 u_int8_t flags; 127 u_int16_t iccl; 128 u_int16_t icch; 129 130 spinlock_t lock; 131 wait_queue_head_t wait; 132 struct i2c_msg *msg; 133 int pos; 134 int sr; 135 }; 136 137 #define IIC_FLAG_HAS_ICIC67 (1 << 0) 138 139 #define STANDARD_MODE 100000 140 #define FAST_MODE 400000 141 142 /* Register offsets */ 143 #define ICDR 0x00 144 #define ICCR 0x04 145 #define ICSR 0x08 146 #define ICIC 0x0c 147 #define ICCL 0x10 148 #define ICCH 0x14 149 150 /* Register bits */ 151 #define ICCR_ICE 0x80 152 #define ICCR_RACK 0x40 153 #define ICCR_TRS 0x10 154 #define ICCR_BBSY 0x04 155 #define ICCR_SCP 0x01 156 157 #define ICSR_SCLM 0x80 158 #define ICSR_SDAM 0x40 159 #define SW_DONE 0x20 160 #define ICSR_BUSY 0x10 161 #define ICSR_AL 0x08 162 #define ICSR_TACK 0x04 163 #define ICSR_WAIT 0x02 164 #define ICSR_DTE 0x01 165 166 #define ICIC_ICCLB8 0x80 167 #define ICIC_ICCHB8 0x40 168 #define ICIC_ALE 0x08 169 #define ICIC_TACKE 0x04 170 #define ICIC_WAITE 0x02 171 #define ICIC_DTEE 0x01 172 173 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 174 { 175 if (offs == ICIC) 176 data |= pd->icic; 177 178 iowrite8(data, pd->reg + offs); 179 } 180 181 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) 182 { 183 return ioread8(pd->reg + offs); 184 } 185 186 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, 187 unsigned char set, unsigned char clr) 188 { 189 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 190 } 191 192 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf, int offset) 193 { 194 /* 195 * Conditional expression: 196 * ICCL >= COUNT_CLK * (tLOW + tf) 197 * 198 * SH-Mobile IIC hardware starts counting the LOW period of 199 * the SCL signal (tLOW) as soon as it pulls the SCL line. 200 * In order to meet the tLOW timing spec, we need to take into 201 * account the fall time of SCL signal (tf). Default tf value 202 * should be 0.3 us, for safety. 203 */ 204 return (((count_khz * (tLOW + tf)) + 5000) / 10000) + offset; 205 } 206 207 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf, int offset) 208 { 209 /* 210 * Conditional expression: 211 * ICCH >= COUNT_CLK * (tHIGH + tf) 212 * 213 * SH-Mobile IIC hardware is aware of SCL transition period 'tr', 214 * and can ignore it. SH-Mobile IIC controller starts counting 215 * the HIGH period of the SCL signal (tHIGH) after the SCL input 216 * voltage increases at VIH. 217 * 218 * Afterward it turned out calculating ICCH using only tHIGH spec 219 * will result in violation of the tHD;STA timing spec. We need 220 * to take into account the fall time of SDA signal (tf) at START 221 * condition, in order to meet both tHIGH and tHD;STA specs. 222 */ 223 return (((count_khz * (tHIGH + tf)) + 5000) / 10000) + offset; 224 } 225 226 static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) 227 { 228 unsigned long i2c_clk_khz; 229 u32 tHIGH, tLOW, tf; 230 int offset; 231 232 /* Get clock rate after clock is enabled */ 233 clk_enable(pd->clk); 234 i2c_clk_khz = clk_get_rate(pd->clk) / 1000; 235 i2c_clk_khz /= pd->clks_per_count; 236 237 if (pd->bus_speed == STANDARD_MODE) { 238 tLOW = 47; /* tLOW = 4.7 us */ 239 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ 240 tf = 3; /* tf = 0.3 us */ 241 offset = 0; /* No offset */ 242 } else if (pd->bus_speed == FAST_MODE) { 243 tLOW = 13; /* tLOW = 1.3 us */ 244 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ 245 tf = 3; /* tf = 0.3 us */ 246 offset = 0; /* No offset */ 247 } else { 248 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", 249 pd->bus_speed); 250 goto out; 251 } 252 253 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf, offset); 254 /* one more bit of ICCL in ICIC */ 255 if ((pd->iccl > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67)) 256 pd->icic |= ICIC_ICCLB8; 257 else 258 pd->icic &= ~ICIC_ICCLB8; 259 260 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf, offset); 261 /* one more bit of ICCH in ICIC */ 262 if ((pd->icch > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67)) 263 pd->icic |= ICIC_ICCHB8; 264 else 265 pd->icic &= ~ICIC_ICCHB8; 266 267 out: 268 clk_disable(pd->clk); 269 } 270 271 static void activate_ch(struct sh_mobile_i2c_data *pd) 272 { 273 /* Wake up device and enable clock */ 274 pm_runtime_get_sync(pd->dev); 275 clk_enable(pd->clk); 276 277 /* Enable channel and configure rx ack */ 278 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 279 280 /* Mask all interrupts */ 281 iic_wr(pd, ICIC, 0); 282 283 /* Set the clock */ 284 iic_wr(pd, ICCL, pd->iccl & 0xff); 285 iic_wr(pd, ICCH, pd->icch & 0xff); 286 } 287 288 static void deactivate_ch(struct sh_mobile_i2c_data *pd) 289 { 290 /* Clear/disable interrupts */ 291 iic_wr(pd, ICSR, 0); 292 iic_wr(pd, ICIC, 0); 293 294 /* Disable channel */ 295 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 296 297 /* Disable clock and mark device as idle */ 298 clk_disable(pd->clk); 299 pm_runtime_put_sync(pd->dev); 300 } 301 302 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 303 enum sh_mobile_i2c_op op, unsigned char data) 304 { 305 unsigned char ret = 0; 306 unsigned long flags; 307 308 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 309 310 spin_lock_irqsave(&pd->lock, flags); 311 312 switch (op) { 313 case OP_START: /* issue start and trigger DTE interrupt */ 314 iic_wr(pd, ICCR, 0x94); 315 break; 316 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 317 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 318 iic_wr(pd, ICDR, data); 319 break; 320 case OP_TX: /* write data */ 321 iic_wr(pd, ICDR, data); 322 break; 323 case OP_TX_STOP: /* write data and issue a stop afterwards */ 324 iic_wr(pd, ICDR, data); 325 iic_wr(pd, ICCR, 0x90); 326 break; 327 case OP_TX_TO_RX: /* select read mode */ 328 iic_wr(pd, ICCR, 0x81); 329 break; 330 case OP_RX: /* just read data */ 331 ret = iic_rd(pd, ICDR); 332 break; 333 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 334 iic_wr(pd, ICIC, 335 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 336 iic_wr(pd, ICCR, 0xc0); 337 break; 338 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 339 iic_wr(pd, ICIC, 340 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 341 ret = iic_rd(pd, ICDR); 342 iic_wr(pd, ICCR, 0xc0); 343 break; 344 } 345 346 spin_unlock_irqrestore(&pd->lock, flags); 347 348 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 349 return ret; 350 } 351 352 static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) 353 { 354 if (pd->pos == -1) 355 return 1; 356 357 return 0; 358 } 359 360 static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) 361 { 362 if (pd->pos == (pd->msg->len - 1)) 363 return 1; 364 365 return 0; 366 } 367 368 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, 369 unsigned char *buf) 370 { 371 switch (pd->pos) { 372 case -1: 373 *buf = (pd->msg->addr & 0x7f) << 1; 374 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; 375 break; 376 default: 377 *buf = pd->msg->buf[pd->pos]; 378 } 379 } 380 381 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 382 { 383 unsigned char data; 384 385 if (pd->pos == pd->msg->len) 386 return 1; 387 388 sh_mobile_i2c_get_data(pd, &data); 389 390 if (sh_mobile_i2c_is_last_byte(pd)) 391 i2c_op(pd, OP_TX_STOP, data); 392 else if (sh_mobile_i2c_is_first_byte(pd)) 393 i2c_op(pd, OP_TX_FIRST, data); 394 else 395 i2c_op(pd, OP_TX, data); 396 397 pd->pos++; 398 return 0; 399 } 400 401 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 402 { 403 unsigned char data; 404 int real_pos; 405 406 do { 407 if (pd->pos <= -1) { 408 sh_mobile_i2c_get_data(pd, &data); 409 410 if (sh_mobile_i2c_is_first_byte(pd)) 411 i2c_op(pd, OP_TX_FIRST, data); 412 else 413 i2c_op(pd, OP_TX, data); 414 break; 415 } 416 417 if (pd->pos == 0) { 418 i2c_op(pd, OP_TX_TO_RX, 0); 419 break; 420 } 421 422 real_pos = pd->pos - 2; 423 424 if (pd->pos == pd->msg->len) { 425 if (real_pos < 0) { 426 i2c_op(pd, OP_RX_STOP, 0); 427 break; 428 } 429 data = i2c_op(pd, OP_RX_STOP_DATA, 0); 430 } else 431 data = i2c_op(pd, OP_RX, 0); 432 433 if (real_pos >= 0) 434 pd->msg->buf[real_pos] = data; 435 } while (0); 436 437 pd->pos++; 438 return pd->pos == (pd->msg->len + 2); 439 } 440 441 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 442 { 443 struct platform_device *dev = dev_id; 444 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 445 unsigned char sr; 446 int wakeup; 447 448 sr = iic_rd(pd, ICSR); 449 pd->sr |= sr; /* remember state */ 450 451 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 452 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 453 pd->pos, pd->msg->len); 454 455 if (sr & (ICSR_AL | ICSR_TACK)) { 456 /* don't interrupt transaction - continue to issue stop */ 457 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 458 wakeup = 0; 459 } else if (pd->msg->flags & I2C_M_RD) 460 wakeup = sh_mobile_i2c_isr_rx(pd); 461 else 462 wakeup = sh_mobile_i2c_isr_tx(pd); 463 464 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 465 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 466 467 if (wakeup) { 468 pd->sr |= SW_DONE; 469 wake_up(&pd->wait); 470 } 471 472 /* defeat write posting to avoid spurious WAIT interrupts */ 473 iic_rd(pd, ICSR); 474 475 return IRQ_HANDLED; 476 } 477 478 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg) 479 { 480 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 481 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 482 return -EIO; 483 } 484 485 /* Initialize channel registers */ 486 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 487 488 /* Enable channel and configure rx ack */ 489 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 490 491 /* Set the clock */ 492 iic_wr(pd, ICCL, pd->iccl & 0xff); 493 iic_wr(pd, ICCH, pd->icch & 0xff); 494 495 pd->msg = usr_msg; 496 pd->pos = -1; 497 pd->sr = 0; 498 499 /* Enable all interrupts to begin with */ 500 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 501 return 0; 502 } 503 504 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 505 struct i2c_msg *msgs, 506 int num) 507 { 508 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 509 struct i2c_msg *msg; 510 int err = 0; 511 u_int8_t val; 512 int i, k, retry_count; 513 514 activate_ch(pd); 515 516 /* Process all messages */ 517 for (i = 0; i < num; i++) { 518 msg = &msgs[i]; 519 520 err = start_ch(pd, msg); 521 if (err) 522 break; 523 524 i2c_op(pd, OP_START, 0); 525 526 /* The interrupt handler takes care of the rest... */ 527 k = wait_event_timeout(pd->wait, 528 pd->sr & (ICSR_TACK | SW_DONE), 529 5 * HZ); 530 if (!k) 531 dev_err(pd->dev, "Transfer request timed out\n"); 532 533 retry_count = 1000; 534 again: 535 val = iic_rd(pd, ICSR); 536 537 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 538 539 /* the interrupt handler may wake us up before the 540 * transfer is finished, so poll the hardware 541 * until we're done. 542 */ 543 if (val & ICSR_BUSY) { 544 udelay(10); 545 if (retry_count--) 546 goto again; 547 548 err = -EIO; 549 dev_err(pd->dev, "Polling timed out\n"); 550 break; 551 } 552 553 /* handle missing acknowledge and arbitration lost */ 554 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) { 555 err = -EIO; 556 break; 557 } 558 } 559 560 deactivate_ch(pd); 561 562 if (!err) 563 err = num; 564 return err; 565 } 566 567 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 568 { 569 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 570 } 571 572 static struct i2c_algorithm sh_mobile_i2c_algorithm = { 573 .functionality = sh_mobile_i2c_func, 574 .master_xfer = sh_mobile_i2c_xfer, 575 }; 576 577 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook) 578 { 579 struct resource *res; 580 int ret = -ENXIO; 581 int n, k = 0; 582 583 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 584 for (n = res->start; hook && n <= res->end; n++) { 585 if (request_irq(n, sh_mobile_i2c_isr, 0, 586 dev_name(&dev->dev), dev)) { 587 for (n--; n >= res->start; n--) 588 free_irq(n, dev); 589 590 goto rollback; 591 } 592 } 593 k++; 594 } 595 596 if (hook) 597 return k > 0 ? 0 : -ENOENT; 598 599 ret = 0; 600 601 rollback: 602 k--; 603 604 while (k >= 0) { 605 res = platform_get_resource(dev, IORESOURCE_IRQ, k); 606 for (n = res->start; n <= res->end; n++) 607 free_irq(n, dev); 608 609 k--; 610 } 611 612 return ret; 613 } 614 615 static int sh_mobile_i2c_probe(struct platform_device *dev) 616 { 617 struct i2c_sh_mobile_platform_data *pdata = dev->dev.platform_data; 618 struct sh_mobile_i2c_data *pd; 619 struct i2c_adapter *adap; 620 struct resource *res; 621 int size; 622 int ret; 623 624 pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 625 if (pd == NULL) { 626 dev_err(&dev->dev, "cannot allocate private data\n"); 627 return -ENOMEM; 628 } 629 630 pd->clk = clk_get(&dev->dev, NULL); 631 if (IS_ERR(pd->clk)) { 632 dev_err(&dev->dev, "cannot get clock\n"); 633 ret = PTR_ERR(pd->clk); 634 goto err; 635 } 636 637 ret = sh_mobile_i2c_hook_irqs(dev, 1); 638 if (ret) { 639 dev_err(&dev->dev, "cannot request IRQ\n"); 640 goto err_clk; 641 } 642 643 pd->dev = &dev->dev; 644 platform_set_drvdata(dev, pd); 645 646 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 647 if (res == NULL) { 648 dev_err(&dev->dev, "cannot find IO resource\n"); 649 ret = -ENOENT; 650 goto err_irq; 651 } 652 653 size = resource_size(res); 654 655 pd->reg = ioremap(res->start, size); 656 if (pd->reg == NULL) { 657 dev_err(&dev->dev, "cannot map IO\n"); 658 ret = -ENXIO; 659 goto err_irq; 660 } 661 662 /* Use platform data bus speed or STANDARD_MODE */ 663 pd->bus_speed = STANDARD_MODE; 664 if (pdata && pdata->bus_speed) 665 pd->bus_speed = pdata->bus_speed; 666 pd->clks_per_count = 1; 667 if (pdata && pdata->clks_per_count) 668 pd->clks_per_count = pdata->clks_per_count; 669 670 /* The IIC blocks on SH-Mobile ARM processors 671 * come with two new bits in ICIC. 672 */ 673 if (size > 0x17) 674 pd->flags |= IIC_FLAG_HAS_ICIC67; 675 676 sh_mobile_i2c_init(pd); 677 678 /* Enable Runtime PM for this device. 679 * 680 * Also tell the Runtime PM core to ignore children 681 * for this device since it is valid for us to suspend 682 * this I2C master driver even though the slave devices 683 * on the I2C bus may not be suspended. 684 * 685 * The state of the I2C hardware bus is unaffected by 686 * the Runtime PM state. 687 */ 688 pm_suspend_ignore_children(&dev->dev, true); 689 pm_runtime_enable(&dev->dev); 690 691 /* setup the private data */ 692 adap = &pd->adap; 693 i2c_set_adapdata(adap, pd); 694 695 adap->owner = THIS_MODULE; 696 adap->algo = &sh_mobile_i2c_algorithm; 697 adap->dev.parent = &dev->dev; 698 adap->retries = 5; 699 adap->nr = dev->id; 700 adap->dev.of_node = dev->dev.of_node; 701 702 strlcpy(adap->name, dev->name, sizeof(adap->name)); 703 704 spin_lock_init(&pd->lock); 705 init_waitqueue_head(&pd->wait); 706 707 ret = i2c_add_numbered_adapter(adap); 708 if (ret < 0) { 709 dev_err(&dev->dev, "cannot add numbered adapter\n"); 710 goto err_all; 711 } 712 713 dev_info(&dev->dev, 714 "I2C adapter %d with bus speed %lu Hz (L/H=%x/%x)\n", 715 adap->nr, pd->bus_speed, pd->iccl, pd->icch); 716 717 of_i2c_register_devices(adap); 718 return 0; 719 720 err_all: 721 iounmap(pd->reg); 722 err_irq: 723 sh_mobile_i2c_hook_irqs(dev, 0); 724 err_clk: 725 clk_put(pd->clk); 726 err: 727 kfree(pd); 728 return ret; 729 } 730 731 static int sh_mobile_i2c_remove(struct platform_device *dev) 732 { 733 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 734 735 i2c_del_adapter(&pd->adap); 736 iounmap(pd->reg); 737 sh_mobile_i2c_hook_irqs(dev, 0); 738 clk_put(pd->clk); 739 pm_runtime_disable(&dev->dev); 740 kfree(pd); 741 return 0; 742 } 743 744 static int sh_mobile_i2c_runtime_nop(struct device *dev) 745 { 746 /* Runtime PM callback shared between ->runtime_suspend() 747 * and ->runtime_resume(). Simply returns success. 748 * 749 * This driver re-initializes all registers after 750 * pm_runtime_get_sync() anyway so there is no need 751 * to save and restore registers here. 752 */ 753 return 0; 754 } 755 756 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { 757 .runtime_suspend = sh_mobile_i2c_runtime_nop, 758 .runtime_resume = sh_mobile_i2c_runtime_nop, 759 }; 760 761 static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 762 { .compatible = "renesas,rmobile-iic", }, 763 {}, 764 }; 765 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 766 767 static struct platform_driver sh_mobile_i2c_driver = { 768 .driver = { 769 .name = "i2c-sh_mobile", 770 .owner = THIS_MODULE, 771 .pm = &sh_mobile_i2c_dev_pm_ops, 772 .of_match_table = sh_mobile_i2c_dt_ids, 773 }, 774 .probe = sh_mobile_i2c_probe, 775 .remove = sh_mobile_i2c_remove, 776 }; 777 778 static int __init sh_mobile_i2c_adap_init(void) 779 { 780 return platform_driver_register(&sh_mobile_i2c_driver); 781 } 782 783 static void __exit sh_mobile_i2c_adap_exit(void) 784 { 785 platform_driver_unregister(&sh_mobile_i2c_driver); 786 } 787 788 subsys_initcall(sh_mobile_i2c_adap_init); 789 module_exit(sh_mobile_i2c_adap_exit); 790 791 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 792 MODULE_AUTHOR("Magnus Damm"); 793 MODULE_LICENSE("GPL v2"); 794 MODULE_ALIAS("platform:i2c-sh_mobile"); 795