1 /* 2 * SuperH Mobile I2C Controller 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * Portions of the code based on out-of-tree driver i2c-sh7343.c 7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/platform_device.h> 28 #include <linux/interrupt.h> 29 #include <linux/i2c.h> 30 #include <linux/of_i2c.h> 31 #include <linux/err.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/clk.h> 34 #include <linux/io.h> 35 #include <linux/slab.h> 36 #include <linux/i2c/i2c-sh_mobile.h> 37 38 /* Transmit operation: */ 39 /* */ 40 /* 0 byte transmit */ 41 /* BUS: S A8 ACK P */ 42 /* IRQ: DTE WAIT */ 43 /* ICIC: */ 44 /* ICCR: 0x94 0x90 */ 45 /* ICDR: A8 */ 46 /* */ 47 /* 1 byte transmit */ 48 /* BUS: S A8 ACK D8(1) ACK P */ 49 /* IRQ: DTE WAIT WAIT */ 50 /* ICIC: -DTE */ 51 /* ICCR: 0x94 0x90 */ 52 /* ICDR: A8 D8(1) */ 53 /* */ 54 /* 2 byte transmit */ 55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */ 56 /* IRQ: DTE WAIT WAIT WAIT */ 57 /* ICIC: -DTE */ 58 /* ICCR: 0x94 0x90 */ 59 /* ICDR: A8 D8(1) D8(2) */ 60 /* */ 61 /* 3 bytes or more, +---------+ gets repeated */ 62 /* */ 63 /* */ 64 /* Receive operation: */ 65 /* */ 66 /* 0 byte receive - not supported since slave may hold SDA low */ 67 /* */ 68 /* 1 byte receive [TX] | [RX] */ 69 /* BUS: S A8 ACK | D8(1) ACK P */ 70 /* IRQ: DTE WAIT | WAIT DTE */ 71 /* ICIC: -DTE | +DTE */ 72 /* ICCR: 0x94 0x81 | 0xc0 */ 73 /* ICDR: A8 | D8(1) */ 74 /* */ 75 /* 2 byte receive [TX]| [RX] */ 76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */ 77 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 78 /* ICIC: -DTE | +DTE */ 79 /* ICCR: 0x94 0x81 | 0xc0 */ 80 /* ICDR: A8 | D8(1) D8(2) */ 81 /* */ 82 /* 3 byte receive [TX] | [RX] */ 83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 85 /* ICIC: -DTE | +DTE */ 86 /* ICCR: 0x94 0x81 | 0xc0 */ 87 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 88 /* */ 89 /* 4 bytes or more, this part is repeated +---------+ */ 90 /* */ 91 /* */ 92 /* Interrupt order and BUSY flag */ 93 /* ___ _ */ 94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 96 /* */ 97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P */ 98 /* ___ */ 99 /* WAIT IRQ ________________________________/ \___________ */ 100 /* TACK IRQ ____________________________________/ \_______ */ 101 /* DTE IRQ __________________________________________/ \_ */ 102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 103 /* _______________________________________________ */ 104 /* BUSY __/ \_ */ 105 /* */ 106 107 enum sh_mobile_i2c_op { 108 OP_START = 0, 109 OP_TX_FIRST, 110 OP_TX, 111 OP_TX_STOP, 112 OP_TX_TO_RX, 113 OP_RX, 114 OP_RX_STOP, 115 OP_RX_STOP_DATA, 116 }; 117 118 struct sh_mobile_i2c_data { 119 struct device *dev; 120 void __iomem *reg; 121 struct i2c_adapter adap; 122 unsigned long bus_speed; 123 struct clk *clk; 124 u_int8_t icic; 125 u_int8_t iccl; 126 u_int8_t icch; 127 u_int8_t flags; 128 129 spinlock_t lock; 130 wait_queue_head_t wait; 131 struct i2c_msg *msg; 132 int pos; 133 int sr; 134 }; 135 136 #define IIC_FLAG_HAS_ICIC67 (1 << 0) 137 138 #define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */ 139 140 /* Register offsets */ 141 #define ICDR 0x00 142 #define ICCR 0x04 143 #define ICSR 0x08 144 #define ICIC 0x0c 145 #define ICCL 0x10 146 #define ICCH 0x14 147 148 /* Register bits */ 149 #define ICCR_ICE 0x80 150 #define ICCR_RACK 0x40 151 #define ICCR_TRS 0x10 152 #define ICCR_BBSY 0x04 153 #define ICCR_SCP 0x01 154 155 #define ICSR_SCLM 0x80 156 #define ICSR_SDAM 0x40 157 #define SW_DONE 0x20 158 #define ICSR_BUSY 0x10 159 #define ICSR_AL 0x08 160 #define ICSR_TACK 0x04 161 #define ICSR_WAIT 0x02 162 #define ICSR_DTE 0x01 163 164 #define ICIC_ICCLB8 0x80 165 #define ICIC_ICCHB8 0x40 166 #define ICIC_ALE 0x08 167 #define ICIC_TACKE 0x04 168 #define ICIC_WAITE 0x02 169 #define ICIC_DTEE 0x01 170 171 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 172 { 173 if (offs == ICIC) 174 data |= pd->icic; 175 176 iowrite8(data, pd->reg + offs); 177 } 178 179 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) 180 { 181 return ioread8(pd->reg + offs); 182 } 183 184 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, 185 unsigned char set, unsigned char clr) 186 { 187 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 188 } 189 190 static void activate_ch(struct sh_mobile_i2c_data *pd) 191 { 192 unsigned long i2c_clk; 193 u_int32_t num; 194 u_int32_t denom; 195 u_int32_t tmp; 196 197 /* Wake up device and enable clock */ 198 pm_runtime_get_sync(pd->dev); 199 clk_enable(pd->clk); 200 201 /* Get clock rate after clock is enabled */ 202 i2c_clk = clk_get_rate(pd->clk); 203 204 /* Calculate the value for iccl. From the data sheet: 205 * iccl = (p clock / transfer rate) * (L / (L + H)) 206 * where L and H are the SCL low/high ratio (5/4 in this case). 207 * We also round off the result. 208 */ 209 num = i2c_clk * 5; 210 denom = pd->bus_speed * 9; 211 tmp = num * 10 / denom; 212 if (tmp % 10 >= 5) 213 pd->iccl = (u_int8_t)((num/denom) + 1); 214 else 215 pd->iccl = (u_int8_t)(num/denom); 216 217 /* one more bit of ICCL in ICIC */ 218 if (pd->flags & IIC_FLAG_HAS_ICIC67) { 219 if ((num/denom) > 0xff) 220 pd->icic |= ICIC_ICCLB8; 221 else 222 pd->icic &= ~ICIC_ICCLB8; 223 } 224 225 /* Calculate the value for icch. From the data sheet: 226 icch = (p clock / transfer rate) * (H / (L + H)) */ 227 num = i2c_clk * 4; 228 tmp = num * 10 / denom; 229 if (tmp % 10 >= 5) 230 pd->icch = (u_int8_t)((num/denom) + 1); 231 else 232 pd->icch = (u_int8_t)(num/denom); 233 234 /* one more bit of ICCH in ICIC */ 235 if (pd->flags & IIC_FLAG_HAS_ICIC67) { 236 if ((num/denom) > 0xff) 237 pd->icic |= ICIC_ICCHB8; 238 else 239 pd->icic &= ~ICIC_ICCHB8; 240 } 241 242 /* Enable channel and configure rx ack */ 243 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 244 245 /* Mask all interrupts */ 246 iic_wr(pd, ICIC, 0); 247 248 /* Set the clock */ 249 iic_wr(pd, ICCL, pd->iccl); 250 iic_wr(pd, ICCH, pd->icch); 251 } 252 253 static void deactivate_ch(struct sh_mobile_i2c_data *pd) 254 { 255 /* Clear/disable interrupts */ 256 iic_wr(pd, ICSR, 0); 257 iic_wr(pd, ICIC, 0); 258 259 /* Disable channel */ 260 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 261 262 /* Disable clock and mark device as idle */ 263 clk_disable(pd->clk); 264 pm_runtime_put_sync(pd->dev); 265 } 266 267 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 268 enum sh_mobile_i2c_op op, unsigned char data) 269 { 270 unsigned char ret = 0; 271 unsigned long flags; 272 273 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 274 275 spin_lock_irqsave(&pd->lock, flags); 276 277 switch (op) { 278 case OP_START: /* issue start and trigger DTE interrupt */ 279 iic_wr(pd, ICCR, 0x94); 280 break; 281 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 282 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 283 iic_wr(pd, ICDR, data); 284 break; 285 case OP_TX: /* write data */ 286 iic_wr(pd, ICDR, data); 287 break; 288 case OP_TX_STOP: /* write data and issue a stop afterwards */ 289 iic_wr(pd, ICDR, data); 290 iic_wr(pd, ICCR, 0x90); 291 break; 292 case OP_TX_TO_RX: /* select read mode */ 293 iic_wr(pd, ICCR, 0x81); 294 break; 295 case OP_RX: /* just read data */ 296 ret = iic_rd(pd, ICDR); 297 break; 298 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 299 iic_wr(pd, ICIC, 300 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 301 iic_wr(pd, ICCR, 0xc0); 302 break; 303 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 304 iic_wr(pd, ICIC, 305 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 306 ret = iic_rd(pd, ICDR); 307 iic_wr(pd, ICCR, 0xc0); 308 break; 309 } 310 311 spin_unlock_irqrestore(&pd->lock, flags); 312 313 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 314 return ret; 315 } 316 317 static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) 318 { 319 if (pd->pos == -1) 320 return 1; 321 322 return 0; 323 } 324 325 static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) 326 { 327 if (pd->pos == (pd->msg->len - 1)) 328 return 1; 329 330 return 0; 331 } 332 333 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, 334 unsigned char *buf) 335 { 336 switch (pd->pos) { 337 case -1: 338 *buf = (pd->msg->addr & 0x7f) << 1; 339 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; 340 break; 341 default: 342 *buf = pd->msg->buf[pd->pos]; 343 } 344 } 345 346 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 347 { 348 unsigned char data; 349 350 if (pd->pos == pd->msg->len) 351 return 1; 352 353 sh_mobile_i2c_get_data(pd, &data); 354 355 if (sh_mobile_i2c_is_last_byte(pd)) 356 i2c_op(pd, OP_TX_STOP, data); 357 else if (sh_mobile_i2c_is_first_byte(pd)) 358 i2c_op(pd, OP_TX_FIRST, data); 359 else 360 i2c_op(pd, OP_TX, data); 361 362 pd->pos++; 363 return 0; 364 } 365 366 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 367 { 368 unsigned char data; 369 int real_pos; 370 371 do { 372 if (pd->pos <= -1) { 373 sh_mobile_i2c_get_data(pd, &data); 374 375 if (sh_mobile_i2c_is_first_byte(pd)) 376 i2c_op(pd, OP_TX_FIRST, data); 377 else 378 i2c_op(pd, OP_TX, data); 379 break; 380 } 381 382 if (pd->pos == 0) { 383 i2c_op(pd, OP_TX_TO_RX, 0); 384 break; 385 } 386 387 real_pos = pd->pos - 2; 388 389 if (pd->pos == pd->msg->len) { 390 if (real_pos < 0) { 391 i2c_op(pd, OP_RX_STOP, 0); 392 break; 393 } 394 data = i2c_op(pd, OP_RX_STOP_DATA, 0); 395 } else 396 data = i2c_op(pd, OP_RX, 0); 397 398 if (real_pos >= 0) 399 pd->msg->buf[real_pos] = data; 400 } while (0); 401 402 pd->pos++; 403 return pd->pos == (pd->msg->len + 2); 404 } 405 406 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 407 { 408 struct platform_device *dev = dev_id; 409 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 410 unsigned char sr; 411 int wakeup; 412 413 sr = iic_rd(pd, ICSR); 414 pd->sr |= sr; /* remember state */ 415 416 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 417 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 418 pd->pos, pd->msg->len); 419 420 if (sr & (ICSR_AL | ICSR_TACK)) { 421 /* don't interrupt transaction - continue to issue stop */ 422 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 423 wakeup = 0; 424 } else if (pd->msg->flags & I2C_M_RD) 425 wakeup = sh_mobile_i2c_isr_rx(pd); 426 else 427 wakeup = sh_mobile_i2c_isr_tx(pd); 428 429 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 430 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 431 432 if (wakeup) { 433 pd->sr |= SW_DONE; 434 wake_up(&pd->wait); 435 } 436 437 return IRQ_HANDLED; 438 } 439 440 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg) 441 { 442 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 443 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 444 return -EIO; 445 } 446 447 /* Initialize channel registers */ 448 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 449 450 /* Enable channel and configure rx ack */ 451 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 452 453 /* Set the clock */ 454 iic_wr(pd, ICCL, pd->iccl); 455 iic_wr(pd, ICCH, pd->icch); 456 457 pd->msg = usr_msg; 458 pd->pos = -1; 459 pd->sr = 0; 460 461 /* Enable all interrupts to begin with */ 462 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 463 return 0; 464 } 465 466 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 467 struct i2c_msg *msgs, 468 int num) 469 { 470 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 471 struct i2c_msg *msg; 472 int err = 0; 473 u_int8_t val; 474 int i, k, retry_count; 475 476 activate_ch(pd); 477 478 /* Process all messages */ 479 for (i = 0; i < num; i++) { 480 msg = &msgs[i]; 481 482 err = start_ch(pd, msg); 483 if (err) 484 break; 485 486 i2c_op(pd, OP_START, 0); 487 488 /* The interrupt handler takes care of the rest... */ 489 k = wait_event_timeout(pd->wait, 490 pd->sr & (ICSR_TACK | SW_DONE), 491 5 * HZ); 492 if (!k) 493 dev_err(pd->dev, "Transfer request timed out\n"); 494 495 retry_count = 1000; 496 again: 497 val = iic_rd(pd, ICSR); 498 499 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 500 501 /* the interrupt handler may wake us up before the 502 * transfer is finished, so poll the hardware 503 * until we're done. 504 */ 505 if (val & ICSR_BUSY) { 506 udelay(10); 507 if (retry_count--) 508 goto again; 509 510 err = -EIO; 511 dev_err(pd->dev, "Polling timed out\n"); 512 break; 513 } 514 515 /* handle missing acknowledge and arbitration lost */ 516 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) { 517 err = -EIO; 518 break; 519 } 520 } 521 522 deactivate_ch(pd); 523 524 if (!err) 525 err = num; 526 return err; 527 } 528 529 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 530 { 531 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 532 } 533 534 static struct i2c_algorithm sh_mobile_i2c_algorithm = { 535 .functionality = sh_mobile_i2c_func, 536 .master_xfer = sh_mobile_i2c_xfer, 537 }; 538 539 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook) 540 { 541 struct resource *res; 542 int ret = -ENXIO; 543 int n, k = 0; 544 545 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 546 for (n = res->start; hook && n <= res->end; n++) { 547 if (request_irq(n, sh_mobile_i2c_isr, 0, 548 dev_name(&dev->dev), dev)) { 549 for (n--; n >= res->start; n--) 550 free_irq(n, dev); 551 552 goto rollback; 553 } 554 } 555 k++; 556 } 557 558 if (hook) 559 return k > 0 ? 0 : -ENOENT; 560 561 ret = 0; 562 563 rollback: 564 k--; 565 566 while (k >= 0) { 567 res = platform_get_resource(dev, IORESOURCE_IRQ, k); 568 for (n = res->start; n <= res->end; n++) 569 free_irq(n, dev); 570 571 k--; 572 } 573 574 return ret; 575 } 576 577 static int sh_mobile_i2c_probe(struct platform_device *dev) 578 { 579 struct i2c_sh_mobile_platform_data *pdata = dev->dev.platform_data; 580 struct sh_mobile_i2c_data *pd; 581 struct i2c_adapter *adap; 582 struct resource *res; 583 int size; 584 int ret; 585 586 pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 587 if (pd == NULL) { 588 dev_err(&dev->dev, "cannot allocate private data\n"); 589 return -ENOMEM; 590 } 591 592 pd->clk = clk_get(&dev->dev, NULL); 593 if (IS_ERR(pd->clk)) { 594 dev_err(&dev->dev, "cannot get clock\n"); 595 ret = PTR_ERR(pd->clk); 596 goto err; 597 } 598 599 ret = sh_mobile_i2c_hook_irqs(dev, 1); 600 if (ret) { 601 dev_err(&dev->dev, "cannot request IRQ\n"); 602 goto err_clk; 603 } 604 605 pd->dev = &dev->dev; 606 platform_set_drvdata(dev, pd); 607 608 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 609 if (res == NULL) { 610 dev_err(&dev->dev, "cannot find IO resource\n"); 611 ret = -ENOENT; 612 goto err_irq; 613 } 614 615 size = resource_size(res); 616 617 pd->reg = ioremap(res->start, size); 618 if (pd->reg == NULL) { 619 dev_err(&dev->dev, "cannot map IO\n"); 620 ret = -ENXIO; 621 goto err_irq; 622 } 623 624 /* Use platformd data bus speed or NORMAL_SPEED */ 625 pd->bus_speed = NORMAL_SPEED; 626 if (pdata && pdata->bus_speed) 627 pd->bus_speed = pdata->bus_speed; 628 629 /* The IIC blocks on SH-Mobile ARM processors 630 * come with two new bits in ICIC. 631 */ 632 if (size > 0x17) 633 pd->flags |= IIC_FLAG_HAS_ICIC67; 634 635 /* Enable Runtime PM for this device. 636 * 637 * Also tell the Runtime PM core to ignore children 638 * for this device since it is valid for us to suspend 639 * this I2C master driver even though the slave devices 640 * on the I2C bus may not be suspended. 641 * 642 * The state of the I2C hardware bus is unaffected by 643 * the Runtime PM state. 644 */ 645 pm_suspend_ignore_children(&dev->dev, true); 646 pm_runtime_enable(&dev->dev); 647 648 /* setup the private data */ 649 adap = &pd->adap; 650 i2c_set_adapdata(adap, pd); 651 652 adap->owner = THIS_MODULE; 653 adap->algo = &sh_mobile_i2c_algorithm; 654 adap->dev.parent = &dev->dev; 655 adap->retries = 5; 656 adap->nr = dev->id; 657 adap->dev.of_node = dev->dev.of_node; 658 659 strlcpy(adap->name, dev->name, sizeof(adap->name)); 660 661 spin_lock_init(&pd->lock); 662 init_waitqueue_head(&pd->wait); 663 664 ret = i2c_add_numbered_adapter(adap); 665 if (ret < 0) { 666 dev_err(&dev->dev, "cannot add numbered adapter\n"); 667 goto err_all; 668 } 669 670 dev_info(&dev->dev, "I2C adapter %d with bus speed %lu Hz\n", 671 adap->nr, pd->bus_speed); 672 673 of_i2c_register_devices(adap); 674 return 0; 675 676 err_all: 677 iounmap(pd->reg); 678 err_irq: 679 sh_mobile_i2c_hook_irqs(dev, 0); 680 err_clk: 681 clk_put(pd->clk); 682 err: 683 kfree(pd); 684 return ret; 685 } 686 687 static int sh_mobile_i2c_remove(struct platform_device *dev) 688 { 689 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 690 691 i2c_del_adapter(&pd->adap); 692 iounmap(pd->reg); 693 sh_mobile_i2c_hook_irqs(dev, 0); 694 clk_put(pd->clk); 695 pm_runtime_disable(&dev->dev); 696 kfree(pd); 697 return 0; 698 } 699 700 static int sh_mobile_i2c_runtime_nop(struct device *dev) 701 { 702 /* Runtime PM callback shared between ->runtime_suspend() 703 * and ->runtime_resume(). Simply returns success. 704 * 705 * This driver re-initializes all registers after 706 * pm_runtime_get_sync() anyway so there is no need 707 * to save and restore registers here. 708 */ 709 return 0; 710 } 711 712 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { 713 .runtime_suspend = sh_mobile_i2c_runtime_nop, 714 .runtime_resume = sh_mobile_i2c_runtime_nop, 715 }; 716 717 static const struct of_device_id sh_mobile_i2c_dt_ids[] __devinitconst = { 718 { .compatible = "renesas,rmobile-iic", }, 719 {}, 720 }; 721 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 722 723 static struct platform_driver sh_mobile_i2c_driver = { 724 .driver = { 725 .name = "i2c-sh_mobile", 726 .owner = THIS_MODULE, 727 .pm = &sh_mobile_i2c_dev_pm_ops, 728 .of_match_table = sh_mobile_i2c_dt_ids, 729 }, 730 .probe = sh_mobile_i2c_probe, 731 .remove = sh_mobile_i2c_remove, 732 }; 733 734 static int __init sh_mobile_i2c_adap_init(void) 735 { 736 return platform_driver_register(&sh_mobile_i2c_driver); 737 } 738 739 static void __exit sh_mobile_i2c_adap_exit(void) 740 { 741 platform_driver_unregister(&sh_mobile_i2c_driver); 742 } 743 744 subsys_initcall(sh_mobile_i2c_adap_init); 745 module_exit(sh_mobile_i2c_adap_exit); 746 747 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 748 MODULE_AUTHOR("Magnus Damm"); 749 MODULE_LICENSE("GPL v2"); 750 MODULE_ALIAS("platform:i2c-sh_mobile"); 751