1 /* linux/drivers/i2c/busses/i2c-s3c2410.c 2 * 3 * Copyright (C) 2004,2005,2009 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 I2C Controller 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 26 #include <linux/i2c.h> 27 #include <linux/init.h> 28 #include <linux/time.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/errno.h> 32 #include <linux/err.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clk.h> 36 #include <linux/cpufreq.h> 37 #include <linux/slab.h> 38 #include <linux/io.h> 39 #include <linux/of_i2c.h> 40 #include <linux/of_gpio.h> 41 42 #include <asm/irq.h> 43 44 #include <plat/regs-iic.h> 45 #include <linux/platform_data/i2c-s3c2410.h> 46 47 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ 48 #define QUIRK_S3C2440 (1 << 0) 49 #define QUIRK_HDMIPHY (1 << 1) 50 #define QUIRK_NO_GPIO (1 << 2) 51 52 /* i2c controller state */ 53 enum s3c24xx_i2c_state { 54 STATE_IDLE, 55 STATE_START, 56 STATE_READ, 57 STATE_WRITE, 58 STATE_STOP 59 }; 60 61 struct s3c24xx_i2c { 62 spinlock_t lock; 63 wait_queue_head_t wait; 64 unsigned int quirks; 65 unsigned int suspended:1; 66 67 struct i2c_msg *msg; 68 unsigned int msg_num; 69 unsigned int msg_idx; 70 unsigned int msg_ptr; 71 72 unsigned int tx_setup; 73 unsigned int irq; 74 75 enum s3c24xx_i2c_state state; 76 unsigned long clkrate; 77 78 void __iomem *regs; 79 struct clk *clk; 80 struct device *dev; 81 struct resource *ioarea; 82 struct i2c_adapter adap; 83 84 struct s3c2410_platform_i2c *pdata; 85 int gpios[2]; 86 #ifdef CONFIG_CPU_FREQ 87 struct notifier_block freq_transition; 88 #endif 89 }; 90 91 static struct platform_device_id s3c24xx_driver_ids[] = { 92 { 93 .name = "s3c2410-i2c", 94 .driver_data = 0, 95 }, { 96 .name = "s3c2440-i2c", 97 .driver_data = QUIRK_S3C2440, 98 }, { 99 .name = "s3c2440-hdmiphy-i2c", 100 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, 101 }, { }, 102 }; 103 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 104 105 #ifdef CONFIG_OF 106 static const struct of_device_id s3c24xx_i2c_match[] = { 107 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, 108 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, 109 { .compatible = "samsung,s3c2440-hdmiphy-i2c", 110 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, 111 {}, 112 }; 113 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); 114 #endif 115 116 /* s3c24xx_get_device_quirks 117 * 118 * Get controller type either from device tree or platform device variant. 119 */ 120 121 static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev) 122 { 123 if (pdev->dev.of_node) { 124 const struct of_device_id *match; 125 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); 126 return (unsigned int)match->data; 127 } 128 129 return platform_get_device_id(pdev)->driver_data; 130 } 131 132 /* s3c24xx_i2c_master_complete 133 * 134 * complete the message and wake up the caller, using the given return code, 135 * or zero to mean ok. 136 */ 137 138 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 139 { 140 dev_dbg(i2c->dev, "master_complete %d\n", ret); 141 142 i2c->msg_ptr = 0; 143 i2c->msg = NULL; 144 i2c->msg_idx++; 145 i2c->msg_num = 0; 146 if (ret) 147 i2c->msg_idx = ret; 148 149 wake_up(&i2c->wait); 150 } 151 152 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 153 { 154 unsigned long tmp; 155 156 tmp = readl(i2c->regs + S3C2410_IICCON); 157 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 158 } 159 160 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 161 { 162 unsigned long tmp; 163 164 tmp = readl(i2c->regs + S3C2410_IICCON); 165 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 166 } 167 168 /* irq enable/disable functions */ 169 170 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 171 { 172 unsigned long tmp; 173 174 tmp = readl(i2c->regs + S3C2410_IICCON); 175 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 176 } 177 178 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 179 { 180 unsigned long tmp; 181 182 tmp = readl(i2c->regs + S3C2410_IICCON); 183 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 184 } 185 186 187 /* s3c24xx_i2c_message_start 188 * 189 * put the start of a message onto the bus 190 */ 191 192 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 193 struct i2c_msg *msg) 194 { 195 unsigned int addr = (msg->addr & 0x7f) << 1; 196 unsigned long stat; 197 unsigned long iiccon; 198 199 stat = 0; 200 stat |= S3C2410_IICSTAT_TXRXEN; 201 202 if (msg->flags & I2C_M_RD) { 203 stat |= S3C2410_IICSTAT_MASTER_RX; 204 addr |= 1; 205 } else 206 stat |= S3C2410_IICSTAT_MASTER_TX; 207 208 if (msg->flags & I2C_M_REV_DIR_ADDR) 209 addr ^= 1; 210 211 /* todo - check for wether ack wanted or not */ 212 s3c24xx_i2c_enable_ack(i2c); 213 214 iiccon = readl(i2c->regs + S3C2410_IICCON); 215 writel(stat, i2c->regs + S3C2410_IICSTAT); 216 217 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 218 writeb(addr, i2c->regs + S3C2410_IICDS); 219 220 /* delay here to ensure the data byte has gotten onto the bus 221 * before the transaction is started */ 222 223 ndelay(i2c->tx_setup); 224 225 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 226 writel(iiccon, i2c->regs + S3C2410_IICCON); 227 228 stat |= S3C2410_IICSTAT_START; 229 writel(stat, i2c->regs + S3C2410_IICSTAT); 230 } 231 232 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 233 { 234 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 235 236 dev_dbg(i2c->dev, "STOP\n"); 237 238 /* stop the transfer */ 239 iicstat &= ~S3C2410_IICSTAT_START; 240 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 241 242 i2c->state = STATE_STOP; 243 244 s3c24xx_i2c_master_complete(i2c, ret); 245 s3c24xx_i2c_disable_irq(i2c); 246 } 247 248 /* helper functions to determine the current state in the set of 249 * messages we are sending */ 250 251 /* is_lastmsg() 252 * 253 * returns TRUE if the current message is the last in the set 254 */ 255 256 static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 257 { 258 return i2c->msg_idx >= (i2c->msg_num - 1); 259 } 260 261 /* is_msglast 262 * 263 * returns TRUE if we this is the last byte in the current message 264 */ 265 266 static inline int is_msglast(struct s3c24xx_i2c *i2c) 267 { 268 return i2c->msg_ptr == i2c->msg->len-1; 269 } 270 271 /* is_msgend 272 * 273 * returns TRUE if we reached the end of the current message 274 */ 275 276 static inline int is_msgend(struct s3c24xx_i2c *i2c) 277 { 278 return i2c->msg_ptr >= i2c->msg->len; 279 } 280 281 /* i2c_s3c_irq_nextbyte 282 * 283 * process an interrupt and work out what to do 284 */ 285 286 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 287 { 288 unsigned long tmp; 289 unsigned char byte; 290 int ret = 0; 291 292 switch (i2c->state) { 293 294 case STATE_IDLE: 295 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 296 goto out; 297 298 case STATE_STOP: 299 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 300 s3c24xx_i2c_disable_irq(i2c); 301 goto out_ack; 302 303 case STATE_START: 304 /* last thing we did was send a start condition on the 305 * bus, or started a new i2c message 306 */ 307 308 if (iicstat & S3C2410_IICSTAT_LASTBIT && 309 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 310 /* ack was not received... */ 311 312 dev_dbg(i2c->dev, "ack was not received\n"); 313 s3c24xx_i2c_stop(i2c, -ENXIO); 314 goto out_ack; 315 } 316 317 if (i2c->msg->flags & I2C_M_RD) 318 i2c->state = STATE_READ; 319 else 320 i2c->state = STATE_WRITE; 321 322 /* terminate the transfer if there is nothing to do 323 * as this is used by the i2c probe to find devices. */ 324 325 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 326 s3c24xx_i2c_stop(i2c, 0); 327 goto out_ack; 328 } 329 330 if (i2c->state == STATE_READ) 331 goto prepare_read; 332 333 /* fall through to the write state, as we will need to 334 * send a byte as well */ 335 336 case STATE_WRITE: 337 /* we are writing data to the device... check for the 338 * end of the message, and if so, work out what to do 339 */ 340 341 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 342 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 343 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 344 345 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 346 goto out_ack; 347 } 348 } 349 350 retry_write: 351 352 if (!is_msgend(i2c)) { 353 byte = i2c->msg->buf[i2c->msg_ptr++]; 354 writeb(byte, i2c->regs + S3C2410_IICDS); 355 356 /* delay after writing the byte to allow the 357 * data setup time on the bus, as writing the 358 * data to the register causes the first bit 359 * to appear on SDA, and SCL will change as 360 * soon as the interrupt is acknowledged */ 361 362 ndelay(i2c->tx_setup); 363 364 } else if (!is_lastmsg(i2c)) { 365 /* we need to go to the next i2c message */ 366 367 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 368 369 i2c->msg_ptr = 0; 370 i2c->msg_idx++; 371 i2c->msg++; 372 373 /* check to see if we need to do another message */ 374 if (i2c->msg->flags & I2C_M_NOSTART) { 375 376 if (i2c->msg->flags & I2C_M_RD) { 377 /* cannot do this, the controller 378 * forces us to send a new START 379 * when we change direction */ 380 381 s3c24xx_i2c_stop(i2c, -EINVAL); 382 } 383 384 goto retry_write; 385 } else { 386 /* send the new start */ 387 s3c24xx_i2c_message_start(i2c, i2c->msg); 388 i2c->state = STATE_START; 389 } 390 391 } else { 392 /* send stop */ 393 394 s3c24xx_i2c_stop(i2c, 0); 395 } 396 break; 397 398 case STATE_READ: 399 /* we have a byte of data in the data register, do 400 * something with it, and then work out wether we are 401 * going to do any more read/write 402 */ 403 404 byte = readb(i2c->regs + S3C2410_IICDS); 405 i2c->msg->buf[i2c->msg_ptr++] = byte; 406 407 prepare_read: 408 if (is_msglast(i2c)) { 409 /* last byte of buffer */ 410 411 if (is_lastmsg(i2c)) 412 s3c24xx_i2c_disable_ack(i2c); 413 414 } else if (is_msgend(i2c)) { 415 /* ok, we've read the entire buffer, see if there 416 * is anything else we need to do */ 417 418 if (is_lastmsg(i2c)) { 419 /* last message, send stop and complete */ 420 dev_dbg(i2c->dev, "READ: Send Stop\n"); 421 422 s3c24xx_i2c_stop(i2c, 0); 423 } else { 424 /* go to the next transfer */ 425 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 426 427 i2c->msg_ptr = 0; 428 i2c->msg_idx++; 429 i2c->msg++; 430 } 431 } 432 433 break; 434 } 435 436 /* acknowlegde the IRQ and get back on with the work */ 437 438 out_ack: 439 tmp = readl(i2c->regs + S3C2410_IICCON); 440 tmp &= ~S3C2410_IICCON_IRQPEND; 441 writel(tmp, i2c->regs + S3C2410_IICCON); 442 out: 443 return ret; 444 } 445 446 /* s3c24xx_i2c_irq 447 * 448 * top level IRQ servicing routine 449 */ 450 451 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 452 { 453 struct s3c24xx_i2c *i2c = dev_id; 454 unsigned long status; 455 unsigned long tmp; 456 457 status = readl(i2c->regs + S3C2410_IICSTAT); 458 459 if (status & S3C2410_IICSTAT_ARBITR) { 460 /* deal with arbitration loss */ 461 dev_err(i2c->dev, "deal with arbitration loss\n"); 462 } 463 464 if (i2c->state == STATE_IDLE) { 465 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 466 467 tmp = readl(i2c->regs + S3C2410_IICCON); 468 tmp &= ~S3C2410_IICCON_IRQPEND; 469 writel(tmp, i2c->regs + S3C2410_IICCON); 470 goto out; 471 } 472 473 /* pretty much this leaves us with the fact that we've 474 * transmitted or received whatever byte we last sent */ 475 476 i2c_s3c_irq_nextbyte(i2c, status); 477 478 out: 479 return IRQ_HANDLED; 480 } 481 482 483 /* s3c24xx_i2c_set_master 484 * 485 * get the i2c bus for a master transaction 486 */ 487 488 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 489 { 490 unsigned long iicstat; 491 int timeout = 400; 492 493 /* the timeout for HDMIPHY is reduced to 10 ms because 494 * the hangup is expected to happen, so waiting 400 ms 495 * causes only unnecessary system hangup 496 */ 497 if (i2c->quirks & QUIRK_HDMIPHY) 498 timeout = 10; 499 500 while (timeout-- > 0) { 501 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 502 503 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 504 return 0; 505 506 msleep(1); 507 } 508 509 /* hang-up of bus dedicated for HDMIPHY occurred, resetting */ 510 if (i2c->quirks & QUIRK_HDMIPHY) { 511 writel(0, i2c->regs + S3C2410_IICCON); 512 writel(0, i2c->regs + S3C2410_IICSTAT); 513 writel(0, i2c->regs + S3C2410_IICDS); 514 515 return 0; 516 } 517 518 return -ETIMEDOUT; 519 } 520 521 /* s3c24xx_i2c_doxfer 522 * 523 * this starts an i2c transfer 524 */ 525 526 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 527 struct i2c_msg *msgs, int num) 528 { 529 unsigned long iicstat, timeout; 530 int spins = 20; 531 int ret; 532 533 if (i2c->suspended) 534 return -EIO; 535 536 ret = s3c24xx_i2c_set_master(i2c); 537 if (ret != 0) { 538 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 539 ret = -EAGAIN; 540 goto out; 541 } 542 543 spin_lock_irq(&i2c->lock); 544 545 i2c->msg = msgs; 546 i2c->msg_num = num; 547 i2c->msg_ptr = 0; 548 i2c->msg_idx = 0; 549 i2c->state = STATE_START; 550 551 s3c24xx_i2c_enable_irq(i2c); 552 s3c24xx_i2c_message_start(i2c, msgs); 553 spin_unlock_irq(&i2c->lock); 554 555 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 556 557 ret = i2c->msg_idx; 558 559 /* having these next two as dev_err() makes life very 560 * noisy when doing an i2cdetect */ 561 562 if (timeout == 0) 563 dev_dbg(i2c->dev, "timeout\n"); 564 else if (ret != num) 565 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 566 567 /* ensure the stop has been through the bus */ 568 569 dev_dbg(i2c->dev, "waiting for bus idle\n"); 570 571 /* first, try busy waiting briefly */ 572 do { 573 cpu_relax(); 574 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 575 } while ((iicstat & S3C2410_IICSTAT_START) && --spins); 576 577 /* if that timed out sleep */ 578 if (!spins) { 579 msleep(1); 580 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 581 } 582 583 if (iicstat & S3C2410_IICSTAT_START) 584 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 585 586 out: 587 return ret; 588 } 589 590 /* s3c24xx_i2c_xfer 591 * 592 * first port of call from the i2c bus code when an message needs 593 * transferring across the i2c bus. 594 */ 595 596 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 597 struct i2c_msg *msgs, int num) 598 { 599 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 600 int retry; 601 int ret; 602 603 pm_runtime_get_sync(&adap->dev); 604 clk_prepare_enable(i2c->clk); 605 606 for (retry = 0; retry < adap->retries; retry++) { 607 608 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 609 610 if (ret != -EAGAIN) { 611 clk_disable_unprepare(i2c->clk); 612 pm_runtime_put(&adap->dev); 613 return ret; 614 } 615 616 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 617 618 udelay(100); 619 } 620 621 clk_disable_unprepare(i2c->clk); 622 pm_runtime_put(&adap->dev); 623 return -EREMOTEIO; 624 } 625 626 /* declare our i2c functionality */ 627 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 628 { 629 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | 630 I2C_FUNC_PROTOCOL_MANGLING; 631 } 632 633 /* i2c bus registration info */ 634 635 static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 636 .master_xfer = s3c24xx_i2c_xfer, 637 .functionality = s3c24xx_i2c_func, 638 }; 639 640 /* s3c24xx_i2c_calcdivisor 641 * 642 * return the divisor settings for a given frequency 643 */ 644 645 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 646 unsigned int *div1, unsigned int *divs) 647 { 648 unsigned int calc_divs = clkin / wanted; 649 unsigned int calc_div1; 650 651 if (calc_divs > (16*16)) 652 calc_div1 = 512; 653 else 654 calc_div1 = 16; 655 656 calc_divs += calc_div1-1; 657 calc_divs /= calc_div1; 658 659 if (calc_divs == 0) 660 calc_divs = 1; 661 if (calc_divs > 17) 662 calc_divs = 17; 663 664 *divs = calc_divs; 665 *div1 = calc_div1; 666 667 return clkin / (calc_divs * calc_div1); 668 } 669 670 /* s3c24xx_i2c_clockrate 671 * 672 * work out a divisor for the user requested frequency setting, 673 * either by the requested frequency, or scanning the acceptable 674 * range of frequencies until something is found 675 */ 676 677 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 678 { 679 struct s3c2410_platform_i2c *pdata = i2c->pdata; 680 unsigned long clkin = clk_get_rate(i2c->clk); 681 unsigned int divs, div1; 682 unsigned long target_frequency; 683 u32 iiccon; 684 int freq; 685 686 i2c->clkrate = clkin; 687 clkin /= 1000; /* clkin now in KHz */ 688 689 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 690 691 target_frequency = pdata->frequency ? pdata->frequency : 100000; 692 693 target_frequency /= 1000; /* Target frequency now in KHz */ 694 695 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 696 697 if (freq > target_frequency) { 698 dev_err(i2c->dev, 699 "Unable to achieve desired frequency %luKHz." \ 700 " Lowest achievable %dKHz\n", target_frequency, freq); 701 return -EINVAL; 702 } 703 704 *got = freq; 705 706 iiccon = readl(i2c->regs + S3C2410_IICCON); 707 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 708 iiccon |= (divs-1); 709 710 if (div1 == 512) 711 iiccon |= S3C2410_IICCON_TXDIV_512; 712 713 writel(iiccon, i2c->regs + S3C2410_IICCON); 714 715 if (i2c->quirks & QUIRK_S3C2440) { 716 unsigned long sda_delay; 717 718 if (pdata->sda_delay) { 719 sda_delay = clkin * pdata->sda_delay; 720 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 721 sda_delay = DIV_ROUND_UP(sda_delay, 5); 722 if (sda_delay > 3) 723 sda_delay = 3; 724 sda_delay |= S3C2410_IICLC_FILTER_ON; 725 } else 726 sda_delay = 0; 727 728 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 729 writel(sda_delay, i2c->regs + S3C2440_IICLC); 730 } 731 732 return 0; 733 } 734 735 #ifdef CONFIG_CPU_FREQ 736 737 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) 738 739 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, 740 unsigned long val, void *data) 741 { 742 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 743 unsigned long flags; 744 unsigned int got; 745 int delta_f; 746 int ret; 747 748 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; 749 750 /* if we're post-change and the input clock has slowed down 751 * or at pre-change and the clock is about to speed up, then 752 * adjust our clock rate. <0 is slow, >0 speedup. 753 */ 754 755 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 756 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 757 spin_lock_irqsave(&i2c->lock, flags); 758 ret = s3c24xx_i2c_clockrate(i2c, &got); 759 spin_unlock_irqrestore(&i2c->lock, flags); 760 761 if (ret < 0) 762 dev_err(i2c->dev, "cannot find frequency\n"); 763 else 764 dev_info(i2c->dev, "setting freq %d\n", got); 765 } 766 767 return 0; 768 } 769 770 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 771 { 772 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; 773 774 return cpufreq_register_notifier(&i2c->freq_transition, 775 CPUFREQ_TRANSITION_NOTIFIER); 776 } 777 778 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 779 { 780 cpufreq_unregister_notifier(&i2c->freq_transition, 781 CPUFREQ_TRANSITION_NOTIFIER); 782 } 783 784 #else 785 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 786 { 787 return 0; 788 } 789 790 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 791 { 792 } 793 #endif 794 795 #ifdef CONFIG_OF 796 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 797 { 798 int idx, gpio, ret; 799 800 if (i2c->quirks & QUIRK_NO_GPIO) 801 return 0; 802 803 for (idx = 0; idx < 2; idx++) { 804 gpio = of_get_gpio(i2c->dev->of_node, idx); 805 if (!gpio_is_valid(gpio)) { 806 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); 807 goto free_gpio; 808 } 809 i2c->gpios[idx] = gpio; 810 811 ret = gpio_request(gpio, "i2c-bus"); 812 if (ret) { 813 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); 814 goto free_gpio; 815 } 816 } 817 return 0; 818 819 free_gpio: 820 while (--idx >= 0) 821 gpio_free(i2c->gpios[idx]); 822 return -EINVAL; 823 } 824 825 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 826 { 827 unsigned int idx; 828 829 if (i2c->quirks & QUIRK_NO_GPIO) 830 return; 831 832 for (idx = 0; idx < 2; idx++) 833 gpio_free(i2c->gpios[idx]); 834 } 835 #else 836 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 837 { 838 return 0; 839 } 840 841 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 842 { 843 } 844 #endif 845 846 /* s3c24xx_i2c_init 847 * 848 * initialise the controller, set the IO lines and frequency 849 */ 850 851 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 852 { 853 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; 854 struct s3c2410_platform_i2c *pdata; 855 unsigned int freq; 856 857 /* get the plafrom data */ 858 859 pdata = i2c->pdata; 860 861 /* inititalise the gpio */ 862 863 if (pdata->cfg_gpio) 864 pdata->cfg_gpio(to_platform_device(i2c->dev)); 865 else 866 if (s3c24xx_i2c_parse_dt_gpio(i2c)) 867 return -EINVAL; 868 869 /* write slave address */ 870 871 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 872 873 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 874 875 writel(iicon, i2c->regs + S3C2410_IICCON); 876 877 /* we need to work out the divisors for the clock... */ 878 879 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 880 writel(0, i2c->regs + S3C2410_IICCON); 881 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 882 return -EINVAL; 883 } 884 885 /* todo - check that the i2c lines aren't being dragged anywhere */ 886 887 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 888 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); 889 890 return 0; 891 } 892 893 #ifdef CONFIG_OF 894 /* s3c24xx_i2c_parse_dt 895 * 896 * Parse the device tree node and retreive the platform data. 897 */ 898 899 static void 900 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 901 { 902 struct s3c2410_platform_i2c *pdata = i2c->pdata; 903 904 if (!np) 905 return; 906 907 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ 908 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); 909 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 910 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 911 (u32 *)&pdata->frequency); 912 } 913 #else 914 static void 915 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 916 { 917 return; 918 } 919 #endif 920 921 /* s3c24xx_i2c_probe 922 * 923 * called by the bus driver when a suitable device is found 924 */ 925 926 static int s3c24xx_i2c_probe(struct platform_device *pdev) 927 { 928 struct s3c24xx_i2c *i2c; 929 struct s3c2410_platform_i2c *pdata = NULL; 930 struct resource *res; 931 int ret; 932 933 if (!pdev->dev.of_node) { 934 pdata = pdev->dev.platform_data; 935 if (!pdata) { 936 dev_err(&pdev->dev, "no platform data\n"); 937 return -EINVAL; 938 } 939 } 940 941 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 942 if (!i2c) { 943 dev_err(&pdev->dev, "no memory for state\n"); 944 return -ENOMEM; 945 } 946 947 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 948 if (!i2c->pdata) { 949 ret = -ENOMEM; 950 goto err_noclk; 951 } 952 953 i2c->quirks = s3c24xx_get_device_quirks(pdev); 954 if (pdata) 955 memcpy(i2c->pdata, pdata, sizeof(*pdata)); 956 else 957 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); 958 959 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 960 i2c->adap.owner = THIS_MODULE; 961 i2c->adap.algo = &s3c24xx_i2c_algorithm; 962 i2c->adap.retries = 2; 963 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 964 i2c->tx_setup = 50; 965 966 spin_lock_init(&i2c->lock); 967 init_waitqueue_head(&i2c->wait); 968 969 /* find the clock and enable it */ 970 971 i2c->dev = &pdev->dev; 972 i2c->clk = clk_get(&pdev->dev, "i2c"); 973 if (IS_ERR(i2c->clk)) { 974 dev_err(&pdev->dev, "cannot get clock\n"); 975 ret = -ENOENT; 976 goto err_noclk; 977 } 978 979 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 980 981 clk_prepare_enable(i2c->clk); 982 983 /* map the registers */ 984 985 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 986 if (res == NULL) { 987 dev_err(&pdev->dev, "cannot find IO resource\n"); 988 ret = -ENOENT; 989 goto err_clk; 990 } 991 992 i2c->ioarea = request_mem_region(res->start, resource_size(res), 993 pdev->name); 994 995 if (i2c->ioarea == NULL) { 996 dev_err(&pdev->dev, "cannot request IO\n"); 997 ret = -ENXIO; 998 goto err_clk; 999 } 1000 1001 i2c->regs = ioremap(res->start, resource_size(res)); 1002 1003 if (i2c->regs == NULL) { 1004 dev_err(&pdev->dev, "cannot map IO\n"); 1005 ret = -ENXIO; 1006 goto err_ioarea; 1007 } 1008 1009 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", 1010 i2c->regs, i2c->ioarea, res); 1011 1012 /* setup info block for the i2c core */ 1013 1014 i2c->adap.algo_data = i2c; 1015 i2c->adap.dev.parent = &pdev->dev; 1016 1017 /* initialise the i2c controller */ 1018 1019 ret = s3c24xx_i2c_init(i2c); 1020 if (ret != 0) 1021 goto err_iomap; 1022 1023 /* find the IRQ for this unit (note, this relies on the init call to 1024 * ensure no current IRQs pending 1025 */ 1026 1027 i2c->irq = ret = platform_get_irq(pdev, 0); 1028 if (ret <= 0) { 1029 dev_err(&pdev->dev, "cannot find IRQ\n"); 1030 goto err_iomap; 1031 } 1032 1033 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0, 1034 dev_name(&pdev->dev), i2c); 1035 1036 if (ret != 0) { 1037 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1038 goto err_iomap; 1039 } 1040 1041 ret = s3c24xx_i2c_register_cpufreq(i2c); 1042 if (ret < 0) { 1043 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 1044 goto err_irq; 1045 } 1046 1047 /* Note, previous versions of the driver used i2c_add_adapter() 1048 * to add the bus at any number. We now pass the bus number via 1049 * the platform data, so if unset it will now default to always 1050 * being bus 0. 1051 */ 1052 1053 i2c->adap.nr = i2c->pdata->bus_num; 1054 i2c->adap.dev.of_node = pdev->dev.of_node; 1055 1056 ret = i2c_add_numbered_adapter(&i2c->adap); 1057 if (ret < 0) { 1058 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 1059 goto err_cpufreq; 1060 } 1061 1062 of_i2c_register_devices(&i2c->adap); 1063 platform_set_drvdata(pdev, i2c); 1064 1065 pm_runtime_enable(&pdev->dev); 1066 pm_runtime_enable(&i2c->adap.dev); 1067 1068 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1069 clk_disable_unprepare(i2c->clk); 1070 return 0; 1071 1072 err_cpufreq: 1073 s3c24xx_i2c_deregister_cpufreq(i2c); 1074 1075 err_irq: 1076 free_irq(i2c->irq, i2c); 1077 1078 err_iomap: 1079 iounmap(i2c->regs); 1080 1081 err_ioarea: 1082 release_resource(i2c->ioarea); 1083 kfree(i2c->ioarea); 1084 1085 err_clk: 1086 clk_disable_unprepare(i2c->clk); 1087 clk_put(i2c->clk); 1088 1089 err_noclk: 1090 return ret; 1091 } 1092 1093 /* s3c24xx_i2c_remove 1094 * 1095 * called when device is removed from the bus 1096 */ 1097 1098 static int s3c24xx_i2c_remove(struct platform_device *pdev) 1099 { 1100 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1101 1102 pm_runtime_disable(&i2c->adap.dev); 1103 pm_runtime_disable(&pdev->dev); 1104 1105 s3c24xx_i2c_deregister_cpufreq(i2c); 1106 1107 i2c_del_adapter(&i2c->adap); 1108 free_irq(i2c->irq, i2c); 1109 1110 clk_disable_unprepare(i2c->clk); 1111 clk_put(i2c->clk); 1112 1113 iounmap(i2c->regs); 1114 1115 release_resource(i2c->ioarea); 1116 s3c24xx_i2c_dt_gpio_free(i2c); 1117 kfree(i2c->ioarea); 1118 1119 return 0; 1120 } 1121 1122 #ifdef CONFIG_PM 1123 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1124 { 1125 struct platform_device *pdev = to_platform_device(dev); 1126 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1127 1128 i2c->suspended = 1; 1129 1130 return 0; 1131 } 1132 1133 static int s3c24xx_i2c_resume(struct device *dev) 1134 { 1135 struct platform_device *pdev = to_platform_device(dev); 1136 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1137 1138 i2c->suspended = 0; 1139 clk_prepare_enable(i2c->clk); 1140 s3c24xx_i2c_init(i2c); 1141 clk_disable_unprepare(i2c->clk); 1142 1143 return 0; 1144 } 1145 1146 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1147 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 1148 .resume = s3c24xx_i2c_resume, 1149 }; 1150 1151 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 1152 #else 1153 #define S3C24XX_DEV_PM_OPS NULL 1154 #endif 1155 1156 /* device driver for platform bus bits */ 1157 1158 static struct platform_driver s3c24xx_i2c_driver = { 1159 .probe = s3c24xx_i2c_probe, 1160 .remove = s3c24xx_i2c_remove, 1161 .id_table = s3c24xx_driver_ids, 1162 .driver = { 1163 .owner = THIS_MODULE, 1164 .name = "s3c-i2c", 1165 .pm = S3C24XX_DEV_PM_OPS, 1166 .of_match_table = of_match_ptr(s3c24xx_i2c_match), 1167 }, 1168 }; 1169 1170 static int __init i2c_adap_s3c_init(void) 1171 { 1172 return platform_driver_register(&s3c24xx_i2c_driver); 1173 } 1174 subsys_initcall(i2c_adap_s3c_init); 1175 1176 static void __exit i2c_adap_s3c_exit(void) 1177 { 1178 platform_driver_unregister(&s3c24xx_i2c_driver); 1179 } 1180 module_exit(i2c_adap_s3c_exit); 1181 1182 MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1183 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 1184 MODULE_LICENSE("GPL"); 1185