1 /* linux/drivers/i2c/busses/i2c-s3c2410.c 2 * 3 * Copyright (C) 2004,2005,2009 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 I2C Controller 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 26 #include <linux/i2c.h> 27 #include <linux/init.h> 28 #include <linux/time.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/errno.h> 32 #include <linux/err.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clk.h> 36 #include <linux/cpufreq.h> 37 #include <linux/slab.h> 38 #include <linux/io.h> 39 #include <linux/of.h> 40 #include <linux/of_gpio.h> 41 #include <linux/pinctrl/consumer.h> 42 43 #include <asm/irq.h> 44 45 #include <linux/platform_data/i2c-s3c2410.h> 46 47 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ 48 49 #define S3C2410_IICCON 0x00 50 #define S3C2410_IICSTAT 0x04 51 #define S3C2410_IICADD 0x08 52 #define S3C2410_IICDS 0x0C 53 #define S3C2440_IICLC 0x10 54 55 #define S3C2410_IICCON_ACKEN (1 << 7) 56 #define S3C2410_IICCON_TXDIV_16 (0 << 6) 57 #define S3C2410_IICCON_TXDIV_512 (1 << 6) 58 #define S3C2410_IICCON_IRQEN (1 << 5) 59 #define S3C2410_IICCON_IRQPEND (1 << 4) 60 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf) 61 #define S3C2410_IICCON_SCALEMASK (0xf) 62 63 #define S3C2410_IICSTAT_MASTER_RX (2 << 6) 64 #define S3C2410_IICSTAT_MASTER_TX (3 << 6) 65 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6) 66 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6) 67 #define S3C2410_IICSTAT_MODEMASK (3 << 6) 68 69 #define S3C2410_IICSTAT_START (1 << 5) 70 #define S3C2410_IICSTAT_BUSBUSY (1 << 5) 71 #define S3C2410_IICSTAT_TXRXEN (1 << 4) 72 #define S3C2410_IICSTAT_ARBITR (1 << 3) 73 #define S3C2410_IICSTAT_ASSLAVE (1 << 2) 74 #define S3C2410_IICSTAT_ADDR0 (1 << 1) 75 #define S3C2410_IICSTAT_LASTBIT (1 << 0) 76 77 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) 78 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) 79 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0) 80 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) 81 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) 82 83 #define S3C2410_IICLC_FILTER_ON (1 << 2) 84 85 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ 86 #define QUIRK_S3C2440 (1 << 0) 87 #define QUIRK_HDMIPHY (1 << 1) 88 #define QUIRK_NO_GPIO (1 << 2) 89 #define QUIRK_POLL (1 << 3) 90 91 /* Max time to wait for bus to become idle after a xfer (in us) */ 92 #define S3C2410_IDLE_TIMEOUT 5000 93 94 /* i2c controller state */ 95 enum s3c24xx_i2c_state { 96 STATE_IDLE, 97 STATE_START, 98 STATE_READ, 99 STATE_WRITE, 100 STATE_STOP 101 }; 102 103 struct s3c24xx_i2c { 104 wait_queue_head_t wait; 105 kernel_ulong_t quirks; 106 unsigned int suspended:1; 107 108 struct i2c_msg *msg; 109 unsigned int msg_num; 110 unsigned int msg_idx; 111 unsigned int msg_ptr; 112 113 unsigned int tx_setup; 114 unsigned int irq; 115 116 enum s3c24xx_i2c_state state; 117 unsigned long clkrate; 118 119 void __iomem *regs; 120 struct clk *clk; 121 struct device *dev; 122 struct i2c_adapter adap; 123 124 struct s3c2410_platform_i2c *pdata; 125 int gpios[2]; 126 struct pinctrl *pctrl; 127 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ) 128 struct notifier_block freq_transition; 129 #endif 130 }; 131 132 static struct platform_device_id s3c24xx_driver_ids[] = { 133 { 134 .name = "s3c2410-i2c", 135 .driver_data = 0, 136 }, { 137 .name = "s3c2440-i2c", 138 .driver_data = QUIRK_S3C2440, 139 }, { 140 .name = "s3c2440-hdmiphy-i2c", 141 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, 142 }, { }, 143 }; 144 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 145 146 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat); 147 148 #ifdef CONFIG_OF 149 static const struct of_device_id s3c24xx_i2c_match[] = { 150 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, 151 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, 152 { .compatible = "samsung,s3c2440-hdmiphy-i2c", 153 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, 154 { .compatible = "samsung,exynos5440-i2c", 155 .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) }, 156 { .compatible = "samsung,exynos5-sata-phy-i2c", 157 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) }, 158 {}, 159 }; 160 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); 161 #endif 162 163 /* s3c24xx_get_device_quirks 164 * 165 * Get controller type either from device tree or platform device variant. 166 */ 167 168 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev) 169 { 170 if (pdev->dev.of_node) { 171 const struct of_device_id *match; 172 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); 173 return (kernel_ulong_t)match->data; 174 } 175 176 return platform_get_device_id(pdev)->driver_data; 177 } 178 179 /* s3c24xx_i2c_master_complete 180 * 181 * complete the message and wake up the caller, using the given return code, 182 * or zero to mean ok. 183 */ 184 185 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 186 { 187 dev_dbg(i2c->dev, "master_complete %d\n", ret); 188 189 i2c->msg_ptr = 0; 190 i2c->msg = NULL; 191 i2c->msg_idx++; 192 i2c->msg_num = 0; 193 if (ret) 194 i2c->msg_idx = ret; 195 196 if (!(i2c->quirks & QUIRK_POLL)) 197 wake_up(&i2c->wait); 198 } 199 200 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 201 { 202 unsigned long tmp; 203 204 tmp = readl(i2c->regs + S3C2410_IICCON); 205 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 206 } 207 208 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 209 { 210 unsigned long tmp; 211 212 tmp = readl(i2c->regs + S3C2410_IICCON); 213 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 214 } 215 216 /* irq enable/disable functions */ 217 218 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 219 { 220 unsigned long tmp; 221 222 tmp = readl(i2c->regs + S3C2410_IICCON); 223 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 224 } 225 226 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 227 { 228 unsigned long tmp; 229 230 tmp = readl(i2c->regs + S3C2410_IICCON); 231 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 232 } 233 234 static bool is_ack(struct s3c24xx_i2c *i2c) 235 { 236 int tries; 237 238 for (tries = 50; tries; --tries) { 239 if (readl(i2c->regs + S3C2410_IICCON) 240 & S3C2410_IICCON_IRQPEND) { 241 if (!(readl(i2c->regs + S3C2410_IICSTAT) 242 & S3C2410_IICSTAT_LASTBIT)) 243 return true; 244 } 245 usleep_range(1000, 2000); 246 } 247 dev_err(i2c->dev, "ack was not recieved\n"); 248 return false; 249 } 250 251 /* s3c24xx_i2c_message_start 252 * 253 * put the start of a message onto the bus 254 */ 255 256 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 257 struct i2c_msg *msg) 258 { 259 unsigned int addr = (msg->addr & 0x7f) << 1; 260 unsigned long stat; 261 unsigned long iiccon; 262 263 stat = 0; 264 stat |= S3C2410_IICSTAT_TXRXEN; 265 266 if (msg->flags & I2C_M_RD) { 267 stat |= S3C2410_IICSTAT_MASTER_RX; 268 addr |= 1; 269 } else 270 stat |= S3C2410_IICSTAT_MASTER_TX; 271 272 if (msg->flags & I2C_M_REV_DIR_ADDR) 273 addr ^= 1; 274 275 /* todo - check for whether ack wanted or not */ 276 s3c24xx_i2c_enable_ack(i2c); 277 278 iiccon = readl(i2c->regs + S3C2410_IICCON); 279 writel(stat, i2c->regs + S3C2410_IICSTAT); 280 281 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 282 writeb(addr, i2c->regs + S3C2410_IICDS); 283 284 /* delay here to ensure the data byte has gotten onto the bus 285 * before the transaction is started */ 286 287 ndelay(i2c->tx_setup); 288 289 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 290 writel(iiccon, i2c->regs + S3C2410_IICCON); 291 292 stat |= S3C2410_IICSTAT_START; 293 writel(stat, i2c->regs + S3C2410_IICSTAT); 294 295 if (i2c->quirks & QUIRK_POLL) { 296 while ((i2c->msg_num != 0) && is_ack(i2c)) { 297 i2c_s3c_irq_nextbyte(i2c, stat); 298 stat = readl(i2c->regs + S3C2410_IICSTAT); 299 300 if (stat & S3C2410_IICSTAT_ARBITR) 301 dev_err(i2c->dev, "deal with arbitration loss\n"); 302 } 303 } 304 } 305 306 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 307 { 308 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 309 310 dev_dbg(i2c->dev, "STOP\n"); 311 312 /* 313 * The datasheet says that the STOP sequence should be: 314 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') 315 * 2) I2CCON.4 = 0 - Clear IRQPEND 316 * 3) Wait until the stop condition takes effect. 317 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN 318 * 319 * Where, step "4*" is only for buses with the "HDMIPHY" quirk. 320 * 321 * However, after much experimentation, it appears that: 322 * a) normal buses automatically clear BUSY and transition from 323 * Master->Slave when they complete generating a STOP condition. 324 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 325 * after starting the STOP generation here. 326 * b) HDMIPHY bus does neither, so there is no way to do step 3. 327 * There is no indication when this bus has finished generating 328 * STOP. 329 * 330 * In fact, we have found that as soon as the IRQPEND bit is cleared in 331 * step 2, the HDMIPHY bus generates the STOP condition, and then 332 * immediately starts transferring another data byte, even though the 333 * bus is supposedly stopped. This is presumably because the bus is 334 * still in "Master" mode, and its BUSY bit is still set. 335 * 336 * To avoid these extra post-STOP transactions on HDMI phy devices, we 337 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, 338 * instead of first generating a proper STOP condition. This should 339 * float SDA & SCK terminating the transfer. Subsequent transfers 340 * start with a proper START condition, and proceed normally. 341 * 342 * The HDMIPHY bus is an internal bus that always has exactly two 343 * devices, the host as Master and the HDMIPHY device as the slave. 344 * Skipping the STOP condition has been tested on this bus and works. 345 */ 346 if (i2c->quirks & QUIRK_HDMIPHY) { 347 /* Stop driving the I2C pins */ 348 iicstat &= ~S3C2410_IICSTAT_TXRXEN; 349 } else { 350 /* stop the transfer */ 351 iicstat &= ~S3C2410_IICSTAT_START; 352 } 353 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 354 355 i2c->state = STATE_STOP; 356 357 s3c24xx_i2c_master_complete(i2c, ret); 358 s3c24xx_i2c_disable_irq(i2c); 359 } 360 361 /* helper functions to determine the current state in the set of 362 * messages we are sending */ 363 364 /* is_lastmsg() 365 * 366 * returns TRUE if the current message is the last in the set 367 */ 368 369 static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 370 { 371 return i2c->msg_idx >= (i2c->msg_num - 1); 372 } 373 374 /* is_msglast 375 * 376 * returns TRUE if we this is the last byte in the current message 377 */ 378 379 static inline int is_msglast(struct s3c24xx_i2c *i2c) 380 { 381 /* msg->len is always 1 for the first byte of smbus block read. 382 * Actual length will be read from slave. More bytes will be 383 * read according to the length then. */ 384 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 385 return 0; 386 387 return i2c->msg_ptr == i2c->msg->len-1; 388 } 389 390 /* is_msgend 391 * 392 * returns TRUE if we reached the end of the current message 393 */ 394 395 static inline int is_msgend(struct s3c24xx_i2c *i2c) 396 { 397 return i2c->msg_ptr >= i2c->msg->len; 398 } 399 400 /* i2c_s3c_irq_nextbyte 401 * 402 * process an interrupt and work out what to do 403 */ 404 405 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 406 { 407 unsigned long tmp; 408 unsigned char byte; 409 int ret = 0; 410 411 switch (i2c->state) { 412 413 case STATE_IDLE: 414 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 415 goto out; 416 417 case STATE_STOP: 418 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 419 s3c24xx_i2c_disable_irq(i2c); 420 goto out_ack; 421 422 case STATE_START: 423 /* last thing we did was send a start condition on the 424 * bus, or started a new i2c message 425 */ 426 427 if (iicstat & S3C2410_IICSTAT_LASTBIT && 428 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 429 /* ack was not received... */ 430 431 dev_dbg(i2c->dev, "ack was not received\n"); 432 s3c24xx_i2c_stop(i2c, -ENXIO); 433 goto out_ack; 434 } 435 436 if (i2c->msg->flags & I2C_M_RD) 437 i2c->state = STATE_READ; 438 else 439 i2c->state = STATE_WRITE; 440 441 /* terminate the transfer if there is nothing to do 442 * as this is used by the i2c probe to find devices. */ 443 444 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 445 s3c24xx_i2c_stop(i2c, 0); 446 goto out_ack; 447 } 448 449 if (i2c->state == STATE_READ) 450 goto prepare_read; 451 452 /* fall through to the write state, as we will need to 453 * send a byte as well */ 454 455 case STATE_WRITE: 456 /* we are writing data to the device... check for the 457 * end of the message, and if so, work out what to do 458 */ 459 460 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 461 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 462 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 463 464 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 465 goto out_ack; 466 } 467 } 468 469 retry_write: 470 471 if (!is_msgend(i2c)) { 472 byte = i2c->msg->buf[i2c->msg_ptr++]; 473 writeb(byte, i2c->regs + S3C2410_IICDS); 474 475 /* delay after writing the byte to allow the 476 * data setup time on the bus, as writing the 477 * data to the register causes the first bit 478 * to appear on SDA, and SCL will change as 479 * soon as the interrupt is acknowledged */ 480 481 ndelay(i2c->tx_setup); 482 483 } else if (!is_lastmsg(i2c)) { 484 /* we need to go to the next i2c message */ 485 486 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 487 488 i2c->msg_ptr = 0; 489 i2c->msg_idx++; 490 i2c->msg++; 491 492 /* check to see if we need to do another message */ 493 if (i2c->msg->flags & I2C_M_NOSTART) { 494 495 if (i2c->msg->flags & I2C_M_RD) { 496 /* cannot do this, the controller 497 * forces us to send a new START 498 * when we change direction */ 499 500 s3c24xx_i2c_stop(i2c, -EINVAL); 501 } 502 503 goto retry_write; 504 } else { 505 /* send the new start */ 506 s3c24xx_i2c_message_start(i2c, i2c->msg); 507 i2c->state = STATE_START; 508 } 509 510 } else { 511 /* send stop */ 512 513 s3c24xx_i2c_stop(i2c, 0); 514 } 515 break; 516 517 case STATE_READ: 518 /* we have a byte of data in the data register, do 519 * something with it, and then work out whether we are 520 * going to do any more read/write 521 */ 522 523 byte = readb(i2c->regs + S3C2410_IICDS); 524 i2c->msg->buf[i2c->msg_ptr++] = byte; 525 526 /* Add actual length to read for smbus block read */ 527 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 528 i2c->msg->len += byte; 529 prepare_read: 530 if (is_msglast(i2c)) { 531 /* last byte of buffer */ 532 533 if (is_lastmsg(i2c)) 534 s3c24xx_i2c_disable_ack(i2c); 535 536 } else if (is_msgend(i2c)) { 537 /* ok, we've read the entire buffer, see if there 538 * is anything else we need to do */ 539 540 if (is_lastmsg(i2c)) { 541 /* last message, send stop and complete */ 542 dev_dbg(i2c->dev, "READ: Send Stop\n"); 543 544 s3c24xx_i2c_stop(i2c, 0); 545 } else { 546 /* go to the next transfer */ 547 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 548 549 i2c->msg_ptr = 0; 550 i2c->msg_idx++; 551 i2c->msg++; 552 } 553 } 554 555 break; 556 } 557 558 /* acknowlegde the IRQ and get back on with the work */ 559 560 out_ack: 561 tmp = readl(i2c->regs + S3C2410_IICCON); 562 tmp &= ~S3C2410_IICCON_IRQPEND; 563 writel(tmp, i2c->regs + S3C2410_IICCON); 564 out: 565 return ret; 566 } 567 568 /* s3c24xx_i2c_irq 569 * 570 * top level IRQ servicing routine 571 */ 572 573 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 574 { 575 struct s3c24xx_i2c *i2c = dev_id; 576 unsigned long status; 577 unsigned long tmp; 578 579 status = readl(i2c->regs + S3C2410_IICSTAT); 580 581 if (status & S3C2410_IICSTAT_ARBITR) { 582 /* deal with arbitration loss */ 583 dev_err(i2c->dev, "deal with arbitration loss\n"); 584 } 585 586 if (i2c->state == STATE_IDLE) { 587 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 588 589 tmp = readl(i2c->regs + S3C2410_IICCON); 590 tmp &= ~S3C2410_IICCON_IRQPEND; 591 writel(tmp, i2c->regs + S3C2410_IICCON); 592 goto out; 593 } 594 595 /* pretty much this leaves us with the fact that we've 596 * transmitted or received whatever byte we last sent */ 597 598 i2c_s3c_irq_nextbyte(i2c, status); 599 600 out: 601 return IRQ_HANDLED; 602 } 603 604 /* 605 * Disable the bus so that we won't get any interrupts from now on, or try 606 * to drive any lines. This is the default state when we don't have 607 * anything to send/receive. 608 * 609 * If there is an event on the bus, or we have a pre-existing event at 610 * kernel boot time, we may not notice the event and the I2C controller 611 * will lock the bus with the I2C clock line low indefinitely. 612 */ 613 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c) 614 { 615 unsigned long tmp; 616 617 /* Stop driving the I2C pins */ 618 tmp = readl(i2c->regs + S3C2410_IICSTAT); 619 tmp &= ~S3C2410_IICSTAT_TXRXEN; 620 writel(tmp, i2c->regs + S3C2410_IICSTAT); 621 622 /* We don't expect any interrupts now, and don't want send acks */ 623 tmp = readl(i2c->regs + S3C2410_IICCON); 624 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND | 625 S3C2410_IICCON_ACKEN); 626 writel(tmp, i2c->regs + S3C2410_IICCON); 627 } 628 629 630 /* s3c24xx_i2c_set_master 631 * 632 * get the i2c bus for a master transaction 633 */ 634 635 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 636 { 637 unsigned long iicstat; 638 int timeout = 400; 639 640 while (timeout-- > 0) { 641 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 642 643 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 644 return 0; 645 646 msleep(1); 647 } 648 649 return -ETIMEDOUT; 650 } 651 652 /* s3c24xx_i2c_wait_idle 653 * 654 * wait for the i2c bus to become idle. 655 */ 656 657 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) 658 { 659 unsigned long iicstat; 660 ktime_t start, now; 661 unsigned long delay; 662 int spins; 663 664 /* ensure the stop has been through the bus */ 665 666 dev_dbg(i2c->dev, "waiting for bus idle\n"); 667 668 start = now = ktime_get(); 669 670 /* 671 * Most of the time, the bus is already idle within a few usec of the 672 * end of a transaction. However, really slow i2c devices can stretch 673 * the clock, delaying STOP generation. 674 * 675 * On slower SoCs this typically happens within a very small number of 676 * instructions so busy wait briefly to avoid scheduling overhead. 677 */ 678 spins = 3; 679 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 680 while ((iicstat & S3C2410_IICSTAT_START) && --spins) { 681 cpu_relax(); 682 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 683 } 684 685 /* 686 * If we do get an appreciable delay as a compromise between idle 687 * detection latency for the normal, fast case, and system load in the 688 * slow device case, use an exponential back off in the polling loop, 689 * up to 1/10th of the total timeout, then continue to poll at a 690 * constant rate up to the timeout. 691 */ 692 delay = 1; 693 while ((iicstat & S3C2410_IICSTAT_START) && 694 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { 695 usleep_range(delay, 2 * delay); 696 if (delay < S3C2410_IDLE_TIMEOUT / 10) 697 delay <<= 1; 698 now = ktime_get(); 699 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 700 } 701 702 if (iicstat & S3C2410_IICSTAT_START) 703 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 704 } 705 706 /* s3c24xx_i2c_doxfer 707 * 708 * this starts an i2c transfer 709 */ 710 711 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 712 struct i2c_msg *msgs, int num) 713 { 714 unsigned long timeout; 715 int ret; 716 717 if (i2c->suspended) 718 return -EIO; 719 720 ret = s3c24xx_i2c_set_master(i2c); 721 if (ret != 0) { 722 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 723 ret = -EAGAIN; 724 goto out; 725 } 726 727 i2c->msg = msgs; 728 i2c->msg_num = num; 729 i2c->msg_ptr = 0; 730 i2c->msg_idx = 0; 731 i2c->state = STATE_START; 732 733 s3c24xx_i2c_enable_irq(i2c); 734 s3c24xx_i2c_message_start(i2c, msgs); 735 736 if (i2c->quirks & QUIRK_POLL) { 737 ret = i2c->msg_idx; 738 739 if (ret != num) 740 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 741 742 goto out; 743 } 744 745 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 746 747 ret = i2c->msg_idx; 748 749 /* having these next two as dev_err() makes life very 750 * noisy when doing an i2cdetect */ 751 752 if (timeout == 0) 753 dev_dbg(i2c->dev, "timeout\n"); 754 else if (ret != num) 755 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 756 757 /* For QUIRK_HDMIPHY, bus is already disabled */ 758 if (i2c->quirks & QUIRK_HDMIPHY) 759 goto out; 760 761 s3c24xx_i2c_wait_idle(i2c); 762 763 s3c24xx_i2c_disable_bus(i2c); 764 765 out: 766 i2c->state = STATE_IDLE; 767 768 return ret; 769 } 770 771 /* s3c24xx_i2c_xfer 772 * 773 * first port of call from the i2c bus code when an message needs 774 * transferring across the i2c bus. 775 */ 776 777 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 778 struct i2c_msg *msgs, int num) 779 { 780 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 781 int retry; 782 int ret; 783 784 pm_runtime_get_sync(&adap->dev); 785 clk_prepare_enable(i2c->clk); 786 787 for (retry = 0; retry < adap->retries; retry++) { 788 789 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 790 791 if (ret != -EAGAIN) { 792 clk_disable_unprepare(i2c->clk); 793 pm_runtime_put(&adap->dev); 794 return ret; 795 } 796 797 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 798 799 udelay(100); 800 } 801 802 clk_disable_unprepare(i2c->clk); 803 pm_runtime_put(&adap->dev); 804 return -EREMOTEIO; 805 } 806 807 /* declare our i2c functionality */ 808 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 809 { 810 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | 811 I2C_FUNC_PROTOCOL_MANGLING; 812 } 813 814 /* i2c bus registration info */ 815 816 static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 817 .master_xfer = s3c24xx_i2c_xfer, 818 .functionality = s3c24xx_i2c_func, 819 }; 820 821 /* s3c24xx_i2c_calcdivisor 822 * 823 * return the divisor settings for a given frequency 824 */ 825 826 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 827 unsigned int *div1, unsigned int *divs) 828 { 829 unsigned int calc_divs = clkin / wanted; 830 unsigned int calc_div1; 831 832 if (calc_divs > (16*16)) 833 calc_div1 = 512; 834 else 835 calc_div1 = 16; 836 837 calc_divs += calc_div1-1; 838 calc_divs /= calc_div1; 839 840 if (calc_divs == 0) 841 calc_divs = 1; 842 if (calc_divs > 17) 843 calc_divs = 17; 844 845 *divs = calc_divs; 846 *div1 = calc_div1; 847 848 return clkin / (calc_divs * calc_div1); 849 } 850 851 /* s3c24xx_i2c_clockrate 852 * 853 * work out a divisor for the user requested frequency setting, 854 * either by the requested frequency, or scanning the acceptable 855 * range of frequencies until something is found 856 */ 857 858 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 859 { 860 struct s3c2410_platform_i2c *pdata = i2c->pdata; 861 unsigned long clkin = clk_get_rate(i2c->clk); 862 unsigned int divs, div1; 863 unsigned long target_frequency; 864 u32 iiccon; 865 int freq; 866 867 i2c->clkrate = clkin; 868 clkin /= 1000; /* clkin now in KHz */ 869 870 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 871 872 target_frequency = pdata->frequency ? pdata->frequency : 100000; 873 874 target_frequency /= 1000; /* Target frequency now in KHz */ 875 876 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 877 878 if (freq > target_frequency) { 879 dev_err(i2c->dev, 880 "Unable to achieve desired frequency %luKHz." \ 881 " Lowest achievable %dKHz\n", target_frequency, freq); 882 return -EINVAL; 883 } 884 885 *got = freq; 886 887 iiccon = readl(i2c->regs + S3C2410_IICCON); 888 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 889 iiccon |= (divs-1); 890 891 if (div1 == 512) 892 iiccon |= S3C2410_IICCON_TXDIV_512; 893 894 if (i2c->quirks & QUIRK_POLL) 895 iiccon |= S3C2410_IICCON_SCALE(2); 896 897 writel(iiccon, i2c->regs + S3C2410_IICCON); 898 899 if (i2c->quirks & QUIRK_S3C2440) { 900 unsigned long sda_delay; 901 902 if (pdata->sda_delay) { 903 sda_delay = clkin * pdata->sda_delay; 904 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 905 sda_delay = DIV_ROUND_UP(sda_delay, 5); 906 if (sda_delay > 3) 907 sda_delay = 3; 908 sda_delay |= S3C2410_IICLC_FILTER_ON; 909 } else 910 sda_delay = 0; 911 912 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 913 writel(sda_delay, i2c->regs + S3C2440_IICLC); 914 } 915 916 return 0; 917 } 918 919 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ) 920 921 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) 922 923 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, 924 unsigned long val, void *data) 925 { 926 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 927 unsigned int got; 928 int delta_f; 929 int ret; 930 931 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; 932 933 /* if we're post-change and the input clock has slowed down 934 * or at pre-change and the clock is about to speed up, then 935 * adjust our clock rate. <0 is slow, >0 speedup. 936 */ 937 938 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 939 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 940 i2c_lock_adapter(&i2c->adap); 941 ret = s3c24xx_i2c_clockrate(i2c, &got); 942 i2c_unlock_adapter(&i2c->adap); 943 944 if (ret < 0) 945 dev_err(i2c->dev, "cannot find frequency\n"); 946 else 947 dev_info(i2c->dev, "setting freq %d\n", got); 948 } 949 950 return 0; 951 } 952 953 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 954 { 955 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; 956 957 return cpufreq_register_notifier(&i2c->freq_transition, 958 CPUFREQ_TRANSITION_NOTIFIER); 959 } 960 961 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 962 { 963 cpufreq_unregister_notifier(&i2c->freq_transition, 964 CPUFREQ_TRANSITION_NOTIFIER); 965 } 966 967 #else 968 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 969 { 970 return 0; 971 } 972 973 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 974 { 975 } 976 #endif 977 978 #ifdef CONFIG_OF 979 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 980 { 981 int idx, gpio, ret; 982 983 if (i2c->quirks & QUIRK_NO_GPIO) 984 return 0; 985 986 for (idx = 0; idx < 2; idx++) { 987 gpio = of_get_gpio(i2c->dev->of_node, idx); 988 if (!gpio_is_valid(gpio)) { 989 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); 990 goto free_gpio; 991 } 992 i2c->gpios[idx] = gpio; 993 994 ret = gpio_request(gpio, "i2c-bus"); 995 if (ret) { 996 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); 997 goto free_gpio; 998 } 999 } 1000 return 0; 1001 1002 free_gpio: 1003 while (--idx >= 0) 1004 gpio_free(i2c->gpios[idx]); 1005 return -EINVAL; 1006 } 1007 1008 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 1009 { 1010 unsigned int idx; 1011 1012 if (i2c->quirks & QUIRK_NO_GPIO) 1013 return; 1014 1015 for (idx = 0; idx < 2; idx++) 1016 gpio_free(i2c->gpios[idx]); 1017 } 1018 #else 1019 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 1020 { 1021 return 0; 1022 } 1023 1024 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 1025 { 1026 } 1027 #endif 1028 1029 /* s3c24xx_i2c_init 1030 * 1031 * initialise the controller, set the IO lines and frequency 1032 */ 1033 1034 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 1035 { 1036 struct s3c2410_platform_i2c *pdata; 1037 unsigned int freq; 1038 1039 /* get the plafrom data */ 1040 1041 pdata = i2c->pdata; 1042 1043 /* write slave address */ 1044 1045 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 1046 1047 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 1048 1049 writel(0, i2c->regs + S3C2410_IICCON); 1050 writel(0, i2c->regs + S3C2410_IICSTAT); 1051 1052 /* we need to work out the divisors for the clock... */ 1053 1054 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 1055 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 1056 return -EINVAL; 1057 } 1058 1059 /* todo - check that the i2c lines aren't being dragged anywhere */ 1060 1061 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 1062 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n", 1063 readl(i2c->regs + S3C2410_IICCON)); 1064 1065 return 0; 1066 } 1067 1068 #ifdef CONFIG_OF 1069 /* s3c24xx_i2c_parse_dt 1070 * 1071 * Parse the device tree node and retreive the platform data. 1072 */ 1073 1074 static void 1075 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 1076 { 1077 struct s3c2410_platform_i2c *pdata = i2c->pdata; 1078 1079 if (!np) 1080 return; 1081 1082 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ 1083 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); 1084 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 1085 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 1086 (u32 *)&pdata->frequency); 1087 } 1088 #else 1089 static void 1090 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 1091 { 1092 return; 1093 } 1094 #endif 1095 1096 /* s3c24xx_i2c_probe 1097 * 1098 * called by the bus driver when a suitable device is found 1099 */ 1100 1101 static int s3c24xx_i2c_probe(struct platform_device *pdev) 1102 { 1103 struct s3c24xx_i2c *i2c; 1104 struct s3c2410_platform_i2c *pdata = NULL; 1105 struct resource *res; 1106 int ret; 1107 1108 if (!pdev->dev.of_node) { 1109 pdata = dev_get_platdata(&pdev->dev); 1110 if (!pdata) { 1111 dev_err(&pdev->dev, "no platform data\n"); 1112 return -EINVAL; 1113 } 1114 } 1115 1116 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 1117 if (!i2c) { 1118 dev_err(&pdev->dev, "no memory for state\n"); 1119 return -ENOMEM; 1120 } 1121 1122 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1123 if (!i2c->pdata) { 1124 dev_err(&pdev->dev, "no memory for platform data\n"); 1125 return -ENOMEM; 1126 } 1127 1128 i2c->quirks = s3c24xx_get_device_quirks(pdev); 1129 if (pdata) 1130 memcpy(i2c->pdata, pdata, sizeof(*pdata)); 1131 else 1132 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); 1133 1134 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 1135 i2c->adap.owner = THIS_MODULE; 1136 i2c->adap.algo = &s3c24xx_i2c_algorithm; 1137 i2c->adap.retries = 2; 1138 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED; 1139 i2c->tx_setup = 50; 1140 1141 init_waitqueue_head(&i2c->wait); 1142 1143 /* find the clock and enable it */ 1144 1145 i2c->dev = &pdev->dev; 1146 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1147 if (IS_ERR(i2c->clk)) { 1148 dev_err(&pdev->dev, "cannot get clock\n"); 1149 return -ENOENT; 1150 } 1151 1152 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 1153 1154 1155 /* map the registers */ 1156 1157 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1158 i2c->regs = devm_ioremap_resource(&pdev->dev, res); 1159 1160 if (IS_ERR(i2c->regs)) 1161 return PTR_ERR(i2c->regs); 1162 1163 dev_dbg(&pdev->dev, "registers %p (%p)\n", 1164 i2c->regs, res); 1165 1166 /* setup info block for the i2c core */ 1167 1168 i2c->adap.algo_data = i2c; 1169 i2c->adap.dev.parent = &pdev->dev; 1170 1171 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); 1172 1173 /* inititalise the i2c gpio lines */ 1174 1175 if (i2c->pdata->cfg_gpio) { 1176 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); 1177 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) { 1178 return -EINVAL; 1179 } 1180 1181 /* initialise the i2c controller */ 1182 1183 clk_prepare_enable(i2c->clk); 1184 ret = s3c24xx_i2c_init(i2c); 1185 clk_disable_unprepare(i2c->clk); 1186 if (ret != 0) { 1187 dev_err(&pdev->dev, "I2C controller init failed\n"); 1188 return ret; 1189 } 1190 /* find the IRQ for this unit (note, this relies on the init call to 1191 * ensure no current IRQs pending 1192 */ 1193 1194 if (!(i2c->quirks & QUIRK_POLL)) { 1195 i2c->irq = ret = platform_get_irq(pdev, 0); 1196 if (ret <= 0) { 1197 dev_err(&pdev->dev, "cannot find IRQ\n"); 1198 return ret; 1199 } 1200 1201 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, 1202 dev_name(&pdev->dev), i2c); 1203 1204 if (ret != 0) { 1205 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1206 return ret; 1207 } 1208 } 1209 1210 ret = s3c24xx_i2c_register_cpufreq(i2c); 1211 if (ret < 0) { 1212 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 1213 return ret; 1214 } 1215 1216 /* Note, previous versions of the driver used i2c_add_adapter() 1217 * to add the bus at any number. We now pass the bus number via 1218 * the platform data, so if unset it will now default to always 1219 * being bus 0. 1220 */ 1221 1222 i2c->adap.nr = i2c->pdata->bus_num; 1223 i2c->adap.dev.of_node = pdev->dev.of_node; 1224 1225 ret = i2c_add_numbered_adapter(&i2c->adap); 1226 if (ret < 0) { 1227 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 1228 s3c24xx_i2c_deregister_cpufreq(i2c); 1229 return ret; 1230 } 1231 1232 platform_set_drvdata(pdev, i2c); 1233 1234 pm_runtime_enable(&pdev->dev); 1235 pm_runtime_enable(&i2c->adap.dev); 1236 1237 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1238 return 0; 1239 } 1240 1241 /* s3c24xx_i2c_remove 1242 * 1243 * called when device is removed from the bus 1244 */ 1245 1246 static int s3c24xx_i2c_remove(struct platform_device *pdev) 1247 { 1248 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1249 1250 pm_runtime_disable(&i2c->adap.dev); 1251 pm_runtime_disable(&pdev->dev); 1252 1253 s3c24xx_i2c_deregister_cpufreq(i2c); 1254 1255 i2c_del_adapter(&i2c->adap); 1256 1257 if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) 1258 s3c24xx_i2c_dt_gpio_free(i2c); 1259 1260 return 0; 1261 } 1262 1263 #ifdef CONFIG_PM_SLEEP 1264 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1265 { 1266 struct platform_device *pdev = to_platform_device(dev); 1267 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1268 1269 i2c->suspended = 1; 1270 1271 return 0; 1272 } 1273 1274 static int s3c24xx_i2c_resume(struct device *dev) 1275 { 1276 struct platform_device *pdev = to_platform_device(dev); 1277 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1278 1279 i2c->suspended = 0; 1280 clk_prepare_enable(i2c->clk); 1281 s3c24xx_i2c_init(i2c); 1282 clk_disable_unprepare(i2c->clk); 1283 1284 return 0; 1285 } 1286 #endif 1287 1288 #ifdef CONFIG_PM 1289 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1290 #ifdef CONFIG_PM_SLEEP 1291 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 1292 .resume = s3c24xx_i2c_resume, 1293 #endif 1294 }; 1295 1296 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 1297 #else 1298 #define S3C24XX_DEV_PM_OPS NULL 1299 #endif 1300 1301 /* device driver for platform bus bits */ 1302 1303 static struct platform_driver s3c24xx_i2c_driver = { 1304 .probe = s3c24xx_i2c_probe, 1305 .remove = s3c24xx_i2c_remove, 1306 .id_table = s3c24xx_driver_ids, 1307 .driver = { 1308 .owner = THIS_MODULE, 1309 .name = "s3c-i2c", 1310 .pm = S3C24XX_DEV_PM_OPS, 1311 .of_match_table = of_match_ptr(s3c24xx_i2c_match), 1312 }, 1313 }; 1314 1315 static int __init i2c_adap_s3c_init(void) 1316 { 1317 return platform_driver_register(&s3c24xx_i2c_driver); 1318 } 1319 subsys_initcall(i2c_adap_s3c_init); 1320 1321 static void __exit i2c_adap_s3c_exit(void) 1322 { 1323 platform_driver_unregister(&s3c24xx_i2c_driver); 1324 } 1325 module_exit(i2c_adap_s3c_exit); 1326 1327 MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1328 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 1329 MODULE_LICENSE("GPL"); 1330