1 /* linux/drivers/i2c/busses/i2c-s3c2410.c 2 * 3 * Copyright (C) 2004,2005,2009 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 I2C Controller 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 26 #include <linux/i2c.h> 27 #include <linux/i2c-id.h> 28 #include <linux/init.h> 29 #include <linux/time.h> 30 #include <linux/interrupt.h> 31 #include <linux/delay.h> 32 #include <linux/errno.h> 33 #include <linux/err.h> 34 #include <linux/platform_device.h> 35 #include <linux/clk.h> 36 #include <linux/cpufreq.h> 37 38 #include <asm/irq.h> 39 #include <asm/io.h> 40 41 #include <plat/regs-iic.h> 42 #include <plat/iic.h> 43 44 /* i2c controller state */ 45 46 enum s3c24xx_i2c_state { 47 STATE_IDLE, 48 STATE_START, 49 STATE_READ, 50 STATE_WRITE, 51 STATE_STOP 52 }; 53 54 enum s3c24xx_i2c_type { 55 TYPE_S3C2410, 56 TYPE_S3C2440, 57 }; 58 59 struct s3c24xx_i2c { 60 spinlock_t lock; 61 wait_queue_head_t wait; 62 unsigned int suspended:1; 63 64 struct i2c_msg *msg; 65 unsigned int msg_num; 66 unsigned int msg_idx; 67 unsigned int msg_ptr; 68 69 unsigned int tx_setup; 70 unsigned int irq; 71 72 enum s3c24xx_i2c_state state; 73 unsigned long clkrate; 74 75 void __iomem *regs; 76 struct clk *clk; 77 struct device *dev; 78 struct resource *ioarea; 79 struct i2c_adapter adap; 80 81 #ifdef CONFIG_CPU_FREQ 82 struct notifier_block freq_transition; 83 #endif 84 }; 85 86 /* default platform data removed, dev should always carry data. */ 87 88 /* s3c24xx_i2c_is2440() 89 * 90 * return true is this is an s3c2440 91 */ 92 93 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c) 94 { 95 struct platform_device *pdev = to_platform_device(i2c->dev); 96 enum s3c24xx_i2c_type type; 97 98 type = platform_get_device_id(pdev)->driver_data; 99 return type == TYPE_S3C2440; 100 } 101 102 /* s3c24xx_i2c_master_complete 103 * 104 * complete the message and wake up the caller, using the given return code, 105 * or zero to mean ok. 106 */ 107 108 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 109 { 110 dev_dbg(i2c->dev, "master_complete %d\n", ret); 111 112 i2c->msg_ptr = 0; 113 i2c->msg = NULL; 114 i2c->msg_idx++; 115 i2c->msg_num = 0; 116 if (ret) 117 i2c->msg_idx = ret; 118 119 wake_up(&i2c->wait); 120 } 121 122 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 123 { 124 unsigned long tmp; 125 126 tmp = readl(i2c->regs + S3C2410_IICCON); 127 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 128 } 129 130 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 131 { 132 unsigned long tmp; 133 134 tmp = readl(i2c->regs + S3C2410_IICCON); 135 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 136 } 137 138 /* irq enable/disable functions */ 139 140 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 141 { 142 unsigned long tmp; 143 144 tmp = readl(i2c->regs + S3C2410_IICCON); 145 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 146 } 147 148 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 149 { 150 unsigned long tmp; 151 152 tmp = readl(i2c->regs + S3C2410_IICCON); 153 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 154 } 155 156 157 /* s3c24xx_i2c_message_start 158 * 159 * put the start of a message onto the bus 160 */ 161 162 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 163 struct i2c_msg *msg) 164 { 165 unsigned int addr = (msg->addr & 0x7f) << 1; 166 unsigned long stat; 167 unsigned long iiccon; 168 169 stat = 0; 170 stat |= S3C2410_IICSTAT_TXRXEN; 171 172 if (msg->flags & I2C_M_RD) { 173 stat |= S3C2410_IICSTAT_MASTER_RX; 174 addr |= 1; 175 } else 176 stat |= S3C2410_IICSTAT_MASTER_TX; 177 178 if (msg->flags & I2C_M_REV_DIR_ADDR) 179 addr ^= 1; 180 181 /* todo - check for wether ack wanted or not */ 182 s3c24xx_i2c_enable_ack(i2c); 183 184 iiccon = readl(i2c->regs + S3C2410_IICCON); 185 writel(stat, i2c->regs + S3C2410_IICSTAT); 186 187 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 188 writeb(addr, i2c->regs + S3C2410_IICDS); 189 190 /* delay here to ensure the data byte has gotten onto the bus 191 * before the transaction is started */ 192 193 ndelay(i2c->tx_setup); 194 195 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 196 writel(iiccon, i2c->regs + S3C2410_IICCON); 197 198 stat |= S3C2410_IICSTAT_START; 199 writel(stat, i2c->regs + S3C2410_IICSTAT); 200 } 201 202 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 203 { 204 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 205 206 dev_dbg(i2c->dev, "STOP\n"); 207 208 /* stop the transfer */ 209 iicstat &= ~S3C2410_IICSTAT_START; 210 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 211 212 i2c->state = STATE_STOP; 213 214 s3c24xx_i2c_master_complete(i2c, ret); 215 s3c24xx_i2c_disable_irq(i2c); 216 } 217 218 /* helper functions to determine the current state in the set of 219 * messages we are sending */ 220 221 /* is_lastmsg() 222 * 223 * returns TRUE if the current message is the last in the set 224 */ 225 226 static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 227 { 228 return i2c->msg_idx >= (i2c->msg_num - 1); 229 } 230 231 /* is_msglast 232 * 233 * returns TRUE if we this is the last byte in the current message 234 */ 235 236 static inline int is_msglast(struct s3c24xx_i2c *i2c) 237 { 238 return i2c->msg_ptr == i2c->msg->len-1; 239 } 240 241 /* is_msgend 242 * 243 * returns TRUE if we reached the end of the current message 244 */ 245 246 static inline int is_msgend(struct s3c24xx_i2c *i2c) 247 { 248 return i2c->msg_ptr >= i2c->msg->len; 249 } 250 251 /* i2s_s3c_irq_nextbyte 252 * 253 * process an interrupt and work out what to do 254 */ 255 256 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 257 { 258 unsigned long tmp; 259 unsigned char byte; 260 int ret = 0; 261 262 switch (i2c->state) { 263 264 case STATE_IDLE: 265 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 266 goto out; 267 break; 268 269 case STATE_STOP: 270 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 271 s3c24xx_i2c_disable_irq(i2c); 272 goto out_ack; 273 274 case STATE_START: 275 /* last thing we did was send a start condition on the 276 * bus, or started a new i2c message 277 */ 278 279 if (iicstat & S3C2410_IICSTAT_LASTBIT && 280 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 281 /* ack was not received... */ 282 283 dev_dbg(i2c->dev, "ack was not received\n"); 284 s3c24xx_i2c_stop(i2c, -ENXIO); 285 goto out_ack; 286 } 287 288 if (i2c->msg->flags & I2C_M_RD) 289 i2c->state = STATE_READ; 290 else 291 i2c->state = STATE_WRITE; 292 293 /* terminate the transfer if there is nothing to do 294 * as this is used by the i2c probe to find devices. */ 295 296 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 297 s3c24xx_i2c_stop(i2c, 0); 298 goto out_ack; 299 } 300 301 if (i2c->state == STATE_READ) 302 goto prepare_read; 303 304 /* fall through to the write state, as we will need to 305 * send a byte as well */ 306 307 case STATE_WRITE: 308 /* we are writing data to the device... check for the 309 * end of the message, and if so, work out what to do 310 */ 311 312 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 313 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 314 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 315 316 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 317 goto out_ack; 318 } 319 } 320 321 retry_write: 322 323 if (!is_msgend(i2c)) { 324 byte = i2c->msg->buf[i2c->msg_ptr++]; 325 writeb(byte, i2c->regs + S3C2410_IICDS); 326 327 /* delay after writing the byte to allow the 328 * data setup time on the bus, as writing the 329 * data to the register causes the first bit 330 * to appear on SDA, and SCL will change as 331 * soon as the interrupt is acknowledged */ 332 333 ndelay(i2c->tx_setup); 334 335 } else if (!is_lastmsg(i2c)) { 336 /* we need to go to the next i2c message */ 337 338 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 339 340 i2c->msg_ptr = 0; 341 i2c->msg_idx++; 342 i2c->msg++; 343 344 /* check to see if we need to do another message */ 345 if (i2c->msg->flags & I2C_M_NOSTART) { 346 347 if (i2c->msg->flags & I2C_M_RD) { 348 /* cannot do this, the controller 349 * forces us to send a new START 350 * when we change direction */ 351 352 s3c24xx_i2c_stop(i2c, -EINVAL); 353 } 354 355 goto retry_write; 356 } else { 357 /* send the new start */ 358 s3c24xx_i2c_message_start(i2c, i2c->msg); 359 i2c->state = STATE_START; 360 } 361 362 } else { 363 /* send stop */ 364 365 s3c24xx_i2c_stop(i2c, 0); 366 } 367 break; 368 369 case STATE_READ: 370 /* we have a byte of data in the data register, do 371 * something with it, and then work out wether we are 372 * going to do any more read/write 373 */ 374 375 byte = readb(i2c->regs + S3C2410_IICDS); 376 i2c->msg->buf[i2c->msg_ptr++] = byte; 377 378 prepare_read: 379 if (is_msglast(i2c)) { 380 /* last byte of buffer */ 381 382 if (is_lastmsg(i2c)) 383 s3c24xx_i2c_disable_ack(i2c); 384 385 } else if (is_msgend(i2c)) { 386 /* ok, we've read the entire buffer, see if there 387 * is anything else we need to do */ 388 389 if (is_lastmsg(i2c)) { 390 /* last message, send stop and complete */ 391 dev_dbg(i2c->dev, "READ: Send Stop\n"); 392 393 s3c24xx_i2c_stop(i2c, 0); 394 } else { 395 /* go to the next transfer */ 396 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 397 398 i2c->msg_ptr = 0; 399 i2c->msg_idx++; 400 i2c->msg++; 401 } 402 } 403 404 break; 405 } 406 407 /* acknowlegde the IRQ and get back on with the work */ 408 409 out_ack: 410 tmp = readl(i2c->regs + S3C2410_IICCON); 411 tmp &= ~S3C2410_IICCON_IRQPEND; 412 writel(tmp, i2c->regs + S3C2410_IICCON); 413 out: 414 return ret; 415 } 416 417 /* s3c24xx_i2c_irq 418 * 419 * top level IRQ servicing routine 420 */ 421 422 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 423 { 424 struct s3c24xx_i2c *i2c = dev_id; 425 unsigned long status; 426 unsigned long tmp; 427 428 status = readl(i2c->regs + S3C2410_IICSTAT); 429 430 if (status & S3C2410_IICSTAT_ARBITR) { 431 /* deal with arbitration loss */ 432 dev_err(i2c->dev, "deal with arbitration loss\n"); 433 } 434 435 if (i2c->state == STATE_IDLE) { 436 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 437 438 tmp = readl(i2c->regs + S3C2410_IICCON); 439 tmp &= ~S3C2410_IICCON_IRQPEND; 440 writel(tmp, i2c->regs + S3C2410_IICCON); 441 goto out; 442 } 443 444 /* pretty much this leaves us with the fact that we've 445 * transmitted or received whatever byte we last sent */ 446 447 i2s_s3c_irq_nextbyte(i2c, status); 448 449 out: 450 return IRQ_HANDLED; 451 } 452 453 454 /* s3c24xx_i2c_set_master 455 * 456 * get the i2c bus for a master transaction 457 */ 458 459 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 460 { 461 unsigned long iicstat; 462 int timeout = 400; 463 464 while (timeout-- > 0) { 465 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 466 467 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 468 return 0; 469 470 msleep(1); 471 } 472 473 return -ETIMEDOUT; 474 } 475 476 /* s3c24xx_i2c_doxfer 477 * 478 * this starts an i2c transfer 479 */ 480 481 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 482 struct i2c_msg *msgs, int num) 483 { 484 unsigned long timeout; 485 int ret; 486 487 if (i2c->suspended) 488 return -EIO; 489 490 ret = s3c24xx_i2c_set_master(i2c); 491 if (ret != 0) { 492 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 493 ret = -EAGAIN; 494 goto out; 495 } 496 497 spin_lock_irq(&i2c->lock); 498 499 i2c->msg = msgs; 500 i2c->msg_num = num; 501 i2c->msg_ptr = 0; 502 i2c->msg_idx = 0; 503 i2c->state = STATE_START; 504 505 s3c24xx_i2c_enable_irq(i2c); 506 s3c24xx_i2c_message_start(i2c, msgs); 507 spin_unlock_irq(&i2c->lock); 508 509 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 510 511 ret = i2c->msg_idx; 512 513 /* having these next two as dev_err() makes life very 514 * noisy when doing an i2cdetect */ 515 516 if (timeout == 0) 517 dev_dbg(i2c->dev, "timeout\n"); 518 else if (ret != num) 519 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 520 521 /* ensure the stop has been through the bus */ 522 523 msleep(1); 524 525 out: 526 return ret; 527 } 528 529 /* s3c24xx_i2c_xfer 530 * 531 * first port of call from the i2c bus code when an message needs 532 * transferring across the i2c bus. 533 */ 534 535 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 536 struct i2c_msg *msgs, int num) 537 { 538 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 539 int retry; 540 int ret; 541 542 for (retry = 0; retry < adap->retries; retry++) { 543 544 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 545 546 if (ret != -EAGAIN) 547 return ret; 548 549 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 550 551 udelay(100); 552 } 553 554 return -EREMOTEIO; 555 } 556 557 /* declare our i2c functionality */ 558 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 559 { 560 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 561 } 562 563 /* i2c bus registration info */ 564 565 static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 566 .master_xfer = s3c24xx_i2c_xfer, 567 .functionality = s3c24xx_i2c_func, 568 }; 569 570 /* s3c24xx_i2c_calcdivisor 571 * 572 * return the divisor settings for a given frequency 573 */ 574 575 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 576 unsigned int *div1, unsigned int *divs) 577 { 578 unsigned int calc_divs = clkin / wanted; 579 unsigned int calc_div1; 580 581 if (calc_divs > (16*16)) 582 calc_div1 = 512; 583 else 584 calc_div1 = 16; 585 586 calc_divs += calc_div1-1; 587 calc_divs /= calc_div1; 588 589 if (calc_divs == 0) 590 calc_divs = 1; 591 if (calc_divs > 17) 592 calc_divs = 17; 593 594 *divs = calc_divs; 595 *div1 = calc_div1; 596 597 return clkin / (calc_divs * calc_div1); 598 } 599 600 /* s3c24xx_i2c_clockrate 601 * 602 * work out a divisor for the user requested frequency setting, 603 * either by the requested frequency, or scanning the acceptable 604 * range of frequencies until something is found 605 */ 606 607 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 608 { 609 struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data; 610 unsigned long clkin = clk_get_rate(i2c->clk); 611 unsigned int divs, div1; 612 unsigned long target_frequency; 613 u32 iiccon; 614 int freq; 615 616 i2c->clkrate = clkin; 617 clkin /= 1000; /* clkin now in KHz */ 618 619 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 620 621 target_frequency = pdata->frequency ? pdata->frequency : 100000; 622 623 target_frequency /= 1000; /* Target frequency now in KHz */ 624 625 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 626 627 if (freq > target_frequency) { 628 dev_err(i2c->dev, 629 "Unable to achieve desired frequency %luKHz." \ 630 " Lowest achievable %dKHz\n", target_frequency, freq); 631 return -EINVAL; 632 } 633 634 *got = freq; 635 636 iiccon = readl(i2c->regs + S3C2410_IICCON); 637 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 638 iiccon |= (divs-1); 639 640 if (div1 == 512) 641 iiccon |= S3C2410_IICCON_TXDIV_512; 642 643 writel(iiccon, i2c->regs + S3C2410_IICCON); 644 645 if (s3c24xx_i2c_is2440(i2c)) { 646 unsigned long sda_delay; 647 648 if (pdata->sda_delay) { 649 sda_delay = (freq / 1000) * pdata->sda_delay; 650 sda_delay /= 1000000; 651 sda_delay = DIV_ROUND_UP(sda_delay, 5); 652 if (sda_delay > 3) 653 sda_delay = 3; 654 sda_delay |= S3C2410_IICLC_FILTER_ON; 655 } else 656 sda_delay = 0; 657 658 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 659 writel(sda_delay, i2c->regs + S3C2440_IICLC); 660 } 661 662 return 0; 663 } 664 665 #ifdef CONFIG_CPU_FREQ 666 667 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) 668 669 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, 670 unsigned long val, void *data) 671 { 672 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 673 unsigned long flags; 674 unsigned int got; 675 int delta_f; 676 int ret; 677 678 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; 679 680 /* if we're post-change and the input clock has slowed down 681 * or at pre-change and the clock is about to speed up, then 682 * adjust our clock rate. <0 is slow, >0 speedup. 683 */ 684 685 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 686 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 687 spin_lock_irqsave(&i2c->lock, flags); 688 ret = s3c24xx_i2c_clockrate(i2c, &got); 689 spin_unlock_irqrestore(&i2c->lock, flags); 690 691 if (ret < 0) 692 dev_err(i2c->dev, "cannot find frequency\n"); 693 else 694 dev_info(i2c->dev, "setting freq %d\n", got); 695 } 696 697 return 0; 698 } 699 700 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 701 { 702 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; 703 704 return cpufreq_register_notifier(&i2c->freq_transition, 705 CPUFREQ_TRANSITION_NOTIFIER); 706 } 707 708 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 709 { 710 cpufreq_unregister_notifier(&i2c->freq_transition, 711 CPUFREQ_TRANSITION_NOTIFIER); 712 } 713 714 #else 715 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 716 { 717 return 0; 718 } 719 720 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 721 { 722 } 723 #endif 724 725 /* s3c24xx_i2c_init 726 * 727 * initialise the controller, set the IO lines and frequency 728 */ 729 730 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 731 { 732 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; 733 struct s3c2410_platform_i2c *pdata; 734 unsigned int freq; 735 736 /* get the plafrom data */ 737 738 pdata = i2c->dev->platform_data; 739 740 /* inititalise the gpio */ 741 742 if (pdata->cfg_gpio) 743 pdata->cfg_gpio(to_platform_device(i2c->dev)); 744 745 /* write slave address */ 746 747 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 748 749 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 750 751 writel(iicon, i2c->regs + S3C2410_IICCON); 752 753 /* we need to work out the divisors for the clock... */ 754 755 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 756 writel(0, i2c->regs + S3C2410_IICCON); 757 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 758 return -EINVAL; 759 } 760 761 /* todo - check that the i2c lines aren't being dragged anywhere */ 762 763 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 764 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); 765 766 return 0; 767 } 768 769 /* s3c24xx_i2c_probe 770 * 771 * called by the bus driver when a suitable device is found 772 */ 773 774 static int s3c24xx_i2c_probe(struct platform_device *pdev) 775 { 776 struct s3c24xx_i2c *i2c; 777 struct s3c2410_platform_i2c *pdata; 778 struct resource *res; 779 int ret; 780 781 pdata = pdev->dev.platform_data; 782 if (!pdata) { 783 dev_err(&pdev->dev, "no platform data\n"); 784 return -EINVAL; 785 } 786 787 i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL); 788 if (!i2c) { 789 dev_err(&pdev->dev, "no memory for state\n"); 790 return -ENOMEM; 791 } 792 793 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 794 i2c->adap.owner = THIS_MODULE; 795 i2c->adap.algo = &s3c24xx_i2c_algorithm; 796 i2c->adap.retries = 2; 797 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 798 i2c->tx_setup = 50; 799 800 spin_lock_init(&i2c->lock); 801 init_waitqueue_head(&i2c->wait); 802 803 /* find the clock and enable it */ 804 805 i2c->dev = &pdev->dev; 806 i2c->clk = clk_get(&pdev->dev, "i2c"); 807 if (IS_ERR(i2c->clk)) { 808 dev_err(&pdev->dev, "cannot get clock\n"); 809 ret = -ENOENT; 810 goto err_noclk; 811 } 812 813 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 814 815 clk_enable(i2c->clk); 816 817 /* map the registers */ 818 819 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 820 if (res == NULL) { 821 dev_err(&pdev->dev, "cannot find IO resource\n"); 822 ret = -ENOENT; 823 goto err_clk; 824 } 825 826 i2c->ioarea = request_mem_region(res->start, resource_size(res), 827 pdev->name); 828 829 if (i2c->ioarea == NULL) { 830 dev_err(&pdev->dev, "cannot request IO\n"); 831 ret = -ENXIO; 832 goto err_clk; 833 } 834 835 i2c->regs = ioremap(res->start, resource_size(res)); 836 837 if (i2c->regs == NULL) { 838 dev_err(&pdev->dev, "cannot map IO\n"); 839 ret = -ENXIO; 840 goto err_ioarea; 841 } 842 843 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", 844 i2c->regs, i2c->ioarea, res); 845 846 /* setup info block for the i2c core */ 847 848 i2c->adap.algo_data = i2c; 849 i2c->adap.dev.parent = &pdev->dev; 850 851 /* initialise the i2c controller */ 852 853 ret = s3c24xx_i2c_init(i2c); 854 if (ret != 0) 855 goto err_iomap; 856 857 /* find the IRQ for this unit (note, this relies on the init call to 858 * ensure no current IRQs pending 859 */ 860 861 i2c->irq = ret = platform_get_irq(pdev, 0); 862 if (ret <= 0) { 863 dev_err(&pdev->dev, "cannot find IRQ\n"); 864 goto err_iomap; 865 } 866 867 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED, 868 dev_name(&pdev->dev), i2c); 869 870 if (ret != 0) { 871 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 872 goto err_iomap; 873 } 874 875 ret = s3c24xx_i2c_register_cpufreq(i2c); 876 if (ret < 0) { 877 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 878 goto err_irq; 879 } 880 881 /* Note, previous versions of the driver used i2c_add_adapter() 882 * to add the bus at any number. We now pass the bus number via 883 * the platform data, so if unset it will now default to always 884 * being bus 0. 885 */ 886 887 i2c->adap.nr = pdata->bus_num; 888 889 ret = i2c_add_numbered_adapter(&i2c->adap); 890 if (ret < 0) { 891 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 892 goto err_cpufreq; 893 } 894 895 platform_set_drvdata(pdev, i2c); 896 897 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 898 return 0; 899 900 err_cpufreq: 901 s3c24xx_i2c_deregister_cpufreq(i2c); 902 903 err_irq: 904 free_irq(i2c->irq, i2c); 905 906 err_iomap: 907 iounmap(i2c->regs); 908 909 err_ioarea: 910 release_resource(i2c->ioarea); 911 kfree(i2c->ioarea); 912 913 err_clk: 914 clk_disable(i2c->clk); 915 clk_put(i2c->clk); 916 917 err_noclk: 918 kfree(i2c); 919 return ret; 920 } 921 922 /* s3c24xx_i2c_remove 923 * 924 * called when device is removed from the bus 925 */ 926 927 static int s3c24xx_i2c_remove(struct platform_device *pdev) 928 { 929 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 930 931 s3c24xx_i2c_deregister_cpufreq(i2c); 932 933 i2c_del_adapter(&i2c->adap); 934 free_irq(i2c->irq, i2c); 935 936 clk_disable(i2c->clk); 937 clk_put(i2c->clk); 938 939 iounmap(i2c->regs); 940 941 release_resource(i2c->ioarea); 942 kfree(i2c->ioarea); 943 kfree(i2c); 944 945 return 0; 946 } 947 948 #ifdef CONFIG_PM 949 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 950 { 951 struct platform_device *pdev = to_platform_device(dev); 952 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 953 954 i2c->suspended = 1; 955 956 return 0; 957 } 958 959 static int s3c24xx_i2c_resume(struct device *dev) 960 { 961 struct platform_device *pdev = to_platform_device(dev); 962 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 963 964 i2c->suspended = 0; 965 s3c24xx_i2c_init(i2c); 966 967 return 0; 968 } 969 970 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 971 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 972 .resume = s3c24xx_i2c_resume, 973 }; 974 975 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 976 #else 977 #define S3C24XX_DEV_PM_OPS NULL 978 #endif 979 980 /* device driver for platform bus bits */ 981 982 static struct platform_device_id s3c24xx_driver_ids[] = { 983 { 984 .name = "s3c2410-i2c", 985 .driver_data = TYPE_S3C2410, 986 }, { 987 .name = "s3c2440-i2c", 988 .driver_data = TYPE_S3C2440, 989 }, { }, 990 }; 991 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 992 993 static struct platform_driver s3c24xx_i2c_driver = { 994 .probe = s3c24xx_i2c_probe, 995 .remove = s3c24xx_i2c_remove, 996 .id_table = s3c24xx_driver_ids, 997 .driver = { 998 .owner = THIS_MODULE, 999 .name = "s3c-i2c", 1000 .pm = S3C24XX_DEV_PM_OPS, 1001 }, 1002 }; 1003 1004 static int __init i2c_adap_s3c_init(void) 1005 { 1006 return platform_driver_register(&s3c24xx_i2c_driver); 1007 } 1008 subsys_initcall(i2c_adap_s3c_init); 1009 1010 static void __exit i2c_adap_s3c_exit(void) 1011 { 1012 platform_driver_unregister(&s3c24xx_i2c_driver); 1013 } 1014 module_exit(i2c_adap_s3c_exit); 1015 1016 MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1017 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 1018 MODULE_LICENSE("GPL"); 1019