1 /* linux/drivers/i2c/busses/i2c-s3c2410.c 2 * 3 * Copyright (C) 2004,2005,2009 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 I2C Controller 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 26 #include <linux/i2c.h> 27 #include <linux/init.h> 28 #include <linux/time.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/errno.h> 32 #include <linux/err.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clk.h> 36 #include <linux/cpufreq.h> 37 #include <linux/slab.h> 38 #include <linux/io.h> 39 #include <linux/of_i2c.h> 40 #include <linux/of_gpio.h> 41 #include <linux/pinctrl/consumer.h> 42 43 #include <asm/irq.h> 44 45 #include <plat/regs-iic.h> 46 #include <linux/platform_data/i2c-s3c2410.h> 47 48 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ 49 #define QUIRK_S3C2440 (1 << 0) 50 #define QUIRK_HDMIPHY (1 << 1) 51 #define QUIRK_NO_GPIO (1 << 2) 52 53 /* Max time to wait for bus to become idle after a xfer (in us) */ 54 #define S3C2410_IDLE_TIMEOUT 5000 55 56 /* i2c controller state */ 57 enum s3c24xx_i2c_state { 58 STATE_IDLE, 59 STATE_START, 60 STATE_READ, 61 STATE_WRITE, 62 STATE_STOP 63 }; 64 65 struct s3c24xx_i2c { 66 wait_queue_head_t wait; 67 unsigned int quirks; 68 unsigned int suspended:1; 69 70 struct i2c_msg *msg; 71 unsigned int msg_num; 72 unsigned int msg_idx; 73 unsigned int msg_ptr; 74 75 unsigned int tx_setup; 76 unsigned int irq; 77 78 enum s3c24xx_i2c_state state; 79 unsigned long clkrate; 80 81 void __iomem *regs; 82 struct clk *clk; 83 struct device *dev; 84 struct i2c_adapter adap; 85 86 struct s3c2410_platform_i2c *pdata; 87 int gpios[2]; 88 struct pinctrl *pctrl; 89 #ifdef CONFIG_CPU_FREQ 90 struct notifier_block freq_transition; 91 #endif 92 }; 93 94 static struct platform_device_id s3c24xx_driver_ids[] = { 95 { 96 .name = "s3c2410-i2c", 97 .driver_data = 0, 98 }, { 99 .name = "s3c2440-i2c", 100 .driver_data = QUIRK_S3C2440, 101 }, { 102 .name = "s3c2440-hdmiphy-i2c", 103 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, 104 }, { }, 105 }; 106 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 107 108 #ifdef CONFIG_OF 109 static const struct of_device_id s3c24xx_i2c_match[] = { 110 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, 111 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, 112 { .compatible = "samsung,s3c2440-hdmiphy-i2c", 113 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, 114 { .compatible = "samsung,exynos5440-i2c", 115 .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) }, 116 {}, 117 }; 118 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); 119 #endif 120 121 /* s3c24xx_get_device_quirks 122 * 123 * Get controller type either from device tree or platform device variant. 124 */ 125 126 static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev) 127 { 128 if (pdev->dev.of_node) { 129 const struct of_device_id *match; 130 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); 131 return (unsigned int)match->data; 132 } 133 134 return platform_get_device_id(pdev)->driver_data; 135 } 136 137 /* s3c24xx_i2c_master_complete 138 * 139 * complete the message and wake up the caller, using the given return code, 140 * or zero to mean ok. 141 */ 142 143 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 144 { 145 dev_dbg(i2c->dev, "master_complete %d\n", ret); 146 147 i2c->msg_ptr = 0; 148 i2c->msg = NULL; 149 i2c->msg_idx++; 150 i2c->msg_num = 0; 151 if (ret) 152 i2c->msg_idx = ret; 153 154 wake_up(&i2c->wait); 155 } 156 157 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 158 { 159 unsigned long tmp; 160 161 tmp = readl(i2c->regs + S3C2410_IICCON); 162 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 163 } 164 165 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 166 { 167 unsigned long tmp; 168 169 tmp = readl(i2c->regs + S3C2410_IICCON); 170 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 171 } 172 173 /* irq enable/disable functions */ 174 175 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 176 { 177 unsigned long tmp; 178 179 tmp = readl(i2c->regs + S3C2410_IICCON); 180 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 181 } 182 183 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 184 { 185 unsigned long tmp; 186 187 tmp = readl(i2c->regs + S3C2410_IICCON); 188 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 189 } 190 191 192 /* s3c24xx_i2c_message_start 193 * 194 * put the start of a message onto the bus 195 */ 196 197 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 198 struct i2c_msg *msg) 199 { 200 unsigned int addr = (msg->addr & 0x7f) << 1; 201 unsigned long stat; 202 unsigned long iiccon; 203 204 stat = 0; 205 stat |= S3C2410_IICSTAT_TXRXEN; 206 207 if (msg->flags & I2C_M_RD) { 208 stat |= S3C2410_IICSTAT_MASTER_RX; 209 addr |= 1; 210 } else 211 stat |= S3C2410_IICSTAT_MASTER_TX; 212 213 if (msg->flags & I2C_M_REV_DIR_ADDR) 214 addr ^= 1; 215 216 /* todo - check for whether ack wanted or not */ 217 s3c24xx_i2c_enable_ack(i2c); 218 219 iiccon = readl(i2c->regs + S3C2410_IICCON); 220 writel(stat, i2c->regs + S3C2410_IICSTAT); 221 222 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 223 writeb(addr, i2c->regs + S3C2410_IICDS); 224 225 /* delay here to ensure the data byte has gotten onto the bus 226 * before the transaction is started */ 227 228 ndelay(i2c->tx_setup); 229 230 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 231 writel(iiccon, i2c->regs + S3C2410_IICCON); 232 233 stat |= S3C2410_IICSTAT_START; 234 writel(stat, i2c->regs + S3C2410_IICSTAT); 235 } 236 237 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 238 { 239 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 240 241 dev_dbg(i2c->dev, "STOP\n"); 242 243 /* 244 * The datasheet says that the STOP sequence should be: 245 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') 246 * 2) I2CCON.4 = 0 - Clear IRQPEND 247 * 3) Wait until the stop condition takes effect. 248 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN 249 * 250 * Where, step "4*" is only for buses with the "HDMIPHY" quirk. 251 * 252 * However, after much experimentation, it appears that: 253 * a) normal buses automatically clear BUSY and transition from 254 * Master->Slave when they complete generating a STOP condition. 255 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 256 * after starting the STOP generation here. 257 * b) HDMIPHY bus does neither, so there is no way to do step 3. 258 * There is no indication when this bus has finished generating 259 * STOP. 260 * 261 * In fact, we have found that as soon as the IRQPEND bit is cleared in 262 * step 2, the HDMIPHY bus generates the STOP condition, and then 263 * immediately starts transferring another data byte, even though the 264 * bus is supposedly stopped. This is presumably because the bus is 265 * still in "Master" mode, and its BUSY bit is still set. 266 * 267 * To avoid these extra post-STOP transactions on HDMI phy devices, we 268 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, 269 * instead of first generating a proper STOP condition. This should 270 * float SDA & SCK terminating the transfer. Subsequent transfers 271 * start with a proper START condition, and proceed normally. 272 * 273 * The HDMIPHY bus is an internal bus that always has exactly two 274 * devices, the host as Master and the HDMIPHY device as the slave. 275 * Skipping the STOP condition has been tested on this bus and works. 276 */ 277 if (i2c->quirks & QUIRK_HDMIPHY) { 278 /* Stop driving the I2C pins */ 279 iicstat &= ~S3C2410_IICSTAT_TXRXEN; 280 } else { 281 /* stop the transfer */ 282 iicstat &= ~S3C2410_IICSTAT_START; 283 } 284 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 285 286 i2c->state = STATE_STOP; 287 288 s3c24xx_i2c_master_complete(i2c, ret); 289 s3c24xx_i2c_disable_irq(i2c); 290 } 291 292 /* helper functions to determine the current state in the set of 293 * messages we are sending */ 294 295 /* is_lastmsg() 296 * 297 * returns TRUE if the current message is the last in the set 298 */ 299 300 static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 301 { 302 return i2c->msg_idx >= (i2c->msg_num - 1); 303 } 304 305 /* is_msglast 306 * 307 * returns TRUE if we this is the last byte in the current message 308 */ 309 310 static inline int is_msglast(struct s3c24xx_i2c *i2c) 311 { 312 return i2c->msg_ptr == i2c->msg->len-1; 313 } 314 315 /* is_msgend 316 * 317 * returns TRUE if we reached the end of the current message 318 */ 319 320 static inline int is_msgend(struct s3c24xx_i2c *i2c) 321 { 322 return i2c->msg_ptr >= i2c->msg->len; 323 } 324 325 /* i2c_s3c_irq_nextbyte 326 * 327 * process an interrupt and work out what to do 328 */ 329 330 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 331 { 332 unsigned long tmp; 333 unsigned char byte; 334 int ret = 0; 335 336 switch (i2c->state) { 337 338 case STATE_IDLE: 339 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 340 goto out; 341 342 case STATE_STOP: 343 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 344 s3c24xx_i2c_disable_irq(i2c); 345 goto out_ack; 346 347 case STATE_START: 348 /* last thing we did was send a start condition on the 349 * bus, or started a new i2c message 350 */ 351 352 if (iicstat & S3C2410_IICSTAT_LASTBIT && 353 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 354 /* ack was not received... */ 355 356 dev_dbg(i2c->dev, "ack was not received\n"); 357 s3c24xx_i2c_stop(i2c, -ENXIO); 358 goto out_ack; 359 } 360 361 if (i2c->msg->flags & I2C_M_RD) 362 i2c->state = STATE_READ; 363 else 364 i2c->state = STATE_WRITE; 365 366 /* terminate the transfer if there is nothing to do 367 * as this is used by the i2c probe to find devices. */ 368 369 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 370 s3c24xx_i2c_stop(i2c, 0); 371 goto out_ack; 372 } 373 374 if (i2c->state == STATE_READ) 375 goto prepare_read; 376 377 /* fall through to the write state, as we will need to 378 * send a byte as well */ 379 380 case STATE_WRITE: 381 /* we are writing data to the device... check for the 382 * end of the message, and if so, work out what to do 383 */ 384 385 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 386 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 387 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 388 389 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 390 goto out_ack; 391 } 392 } 393 394 retry_write: 395 396 if (!is_msgend(i2c)) { 397 byte = i2c->msg->buf[i2c->msg_ptr++]; 398 writeb(byte, i2c->regs + S3C2410_IICDS); 399 400 /* delay after writing the byte to allow the 401 * data setup time on the bus, as writing the 402 * data to the register causes the first bit 403 * to appear on SDA, and SCL will change as 404 * soon as the interrupt is acknowledged */ 405 406 ndelay(i2c->tx_setup); 407 408 } else if (!is_lastmsg(i2c)) { 409 /* we need to go to the next i2c message */ 410 411 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 412 413 i2c->msg_ptr = 0; 414 i2c->msg_idx++; 415 i2c->msg++; 416 417 /* check to see if we need to do another message */ 418 if (i2c->msg->flags & I2C_M_NOSTART) { 419 420 if (i2c->msg->flags & I2C_M_RD) { 421 /* cannot do this, the controller 422 * forces us to send a new START 423 * when we change direction */ 424 425 s3c24xx_i2c_stop(i2c, -EINVAL); 426 } 427 428 goto retry_write; 429 } else { 430 /* send the new start */ 431 s3c24xx_i2c_message_start(i2c, i2c->msg); 432 i2c->state = STATE_START; 433 } 434 435 } else { 436 /* send stop */ 437 438 s3c24xx_i2c_stop(i2c, 0); 439 } 440 break; 441 442 case STATE_READ: 443 /* we have a byte of data in the data register, do 444 * something with it, and then work out whether we are 445 * going to do any more read/write 446 */ 447 448 byte = readb(i2c->regs + S3C2410_IICDS); 449 i2c->msg->buf[i2c->msg_ptr++] = byte; 450 451 prepare_read: 452 if (is_msglast(i2c)) { 453 /* last byte of buffer */ 454 455 if (is_lastmsg(i2c)) 456 s3c24xx_i2c_disable_ack(i2c); 457 458 } else if (is_msgend(i2c)) { 459 /* ok, we've read the entire buffer, see if there 460 * is anything else we need to do */ 461 462 if (is_lastmsg(i2c)) { 463 /* last message, send stop and complete */ 464 dev_dbg(i2c->dev, "READ: Send Stop\n"); 465 466 s3c24xx_i2c_stop(i2c, 0); 467 } else { 468 /* go to the next transfer */ 469 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 470 471 i2c->msg_ptr = 0; 472 i2c->msg_idx++; 473 i2c->msg++; 474 } 475 } 476 477 break; 478 } 479 480 /* acknowlegde the IRQ and get back on with the work */ 481 482 out_ack: 483 tmp = readl(i2c->regs + S3C2410_IICCON); 484 tmp &= ~S3C2410_IICCON_IRQPEND; 485 writel(tmp, i2c->regs + S3C2410_IICCON); 486 out: 487 return ret; 488 } 489 490 /* s3c24xx_i2c_irq 491 * 492 * top level IRQ servicing routine 493 */ 494 495 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 496 { 497 struct s3c24xx_i2c *i2c = dev_id; 498 unsigned long status; 499 unsigned long tmp; 500 501 status = readl(i2c->regs + S3C2410_IICSTAT); 502 503 if (status & S3C2410_IICSTAT_ARBITR) { 504 /* deal with arbitration loss */ 505 dev_err(i2c->dev, "deal with arbitration loss\n"); 506 } 507 508 if (i2c->state == STATE_IDLE) { 509 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 510 511 tmp = readl(i2c->regs + S3C2410_IICCON); 512 tmp &= ~S3C2410_IICCON_IRQPEND; 513 writel(tmp, i2c->regs + S3C2410_IICCON); 514 goto out; 515 } 516 517 /* pretty much this leaves us with the fact that we've 518 * transmitted or received whatever byte we last sent */ 519 520 i2c_s3c_irq_nextbyte(i2c, status); 521 522 out: 523 return IRQ_HANDLED; 524 } 525 526 527 /* s3c24xx_i2c_set_master 528 * 529 * get the i2c bus for a master transaction 530 */ 531 532 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 533 { 534 unsigned long iicstat; 535 int timeout = 400; 536 537 while (timeout-- > 0) { 538 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 539 540 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 541 return 0; 542 543 msleep(1); 544 } 545 546 return -ETIMEDOUT; 547 } 548 549 /* s3c24xx_i2c_wait_idle 550 * 551 * wait for the i2c bus to become idle. 552 */ 553 554 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) 555 { 556 unsigned long iicstat; 557 ktime_t start, now; 558 unsigned long delay; 559 int spins; 560 561 /* ensure the stop has been through the bus */ 562 563 dev_dbg(i2c->dev, "waiting for bus idle\n"); 564 565 start = now = ktime_get(); 566 567 /* 568 * Most of the time, the bus is already idle within a few usec of the 569 * end of a transaction. However, really slow i2c devices can stretch 570 * the clock, delaying STOP generation. 571 * 572 * On slower SoCs this typically happens within a very small number of 573 * instructions so busy wait briefly to avoid scheduling overhead. 574 */ 575 spins = 3; 576 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 577 while ((iicstat & S3C2410_IICSTAT_START) && --spins) { 578 cpu_relax(); 579 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 580 } 581 582 /* 583 * If we do get an appreciable delay as a compromise between idle 584 * detection latency for the normal, fast case, and system load in the 585 * slow device case, use an exponential back off in the polling loop, 586 * up to 1/10th of the total timeout, then continue to poll at a 587 * constant rate up to the timeout. 588 */ 589 delay = 1; 590 while ((iicstat & S3C2410_IICSTAT_START) && 591 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { 592 usleep_range(delay, 2 * delay); 593 if (delay < S3C2410_IDLE_TIMEOUT / 10) 594 delay <<= 1; 595 now = ktime_get(); 596 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 597 } 598 599 if (iicstat & S3C2410_IICSTAT_START) 600 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 601 } 602 603 /* s3c24xx_i2c_doxfer 604 * 605 * this starts an i2c transfer 606 */ 607 608 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 609 struct i2c_msg *msgs, int num) 610 { 611 unsigned long timeout; 612 int ret; 613 614 if (i2c->suspended) 615 return -EIO; 616 617 ret = s3c24xx_i2c_set_master(i2c); 618 if (ret != 0) { 619 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 620 ret = -EAGAIN; 621 goto out; 622 } 623 624 i2c->msg = msgs; 625 i2c->msg_num = num; 626 i2c->msg_ptr = 0; 627 i2c->msg_idx = 0; 628 i2c->state = STATE_START; 629 630 s3c24xx_i2c_enable_irq(i2c); 631 s3c24xx_i2c_message_start(i2c, msgs); 632 633 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 634 635 ret = i2c->msg_idx; 636 637 /* having these next two as dev_err() makes life very 638 * noisy when doing an i2cdetect */ 639 640 if (timeout == 0) 641 dev_dbg(i2c->dev, "timeout\n"); 642 else if (ret != num) 643 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 644 645 /* For QUIRK_HDMIPHY, bus is already disabled */ 646 if (i2c->quirks & QUIRK_HDMIPHY) 647 goto out; 648 649 s3c24xx_i2c_wait_idle(i2c); 650 651 out: 652 return ret; 653 } 654 655 /* s3c24xx_i2c_xfer 656 * 657 * first port of call from the i2c bus code when an message needs 658 * transferring across the i2c bus. 659 */ 660 661 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 662 struct i2c_msg *msgs, int num) 663 { 664 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 665 int retry; 666 int ret; 667 668 pm_runtime_get_sync(&adap->dev); 669 clk_prepare_enable(i2c->clk); 670 671 for (retry = 0; retry < adap->retries; retry++) { 672 673 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 674 675 if (ret != -EAGAIN) { 676 clk_disable_unprepare(i2c->clk); 677 pm_runtime_put(&adap->dev); 678 return ret; 679 } 680 681 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 682 683 udelay(100); 684 } 685 686 clk_disable_unprepare(i2c->clk); 687 pm_runtime_put(&adap->dev); 688 return -EREMOTEIO; 689 } 690 691 /* declare our i2c functionality */ 692 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 693 { 694 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | 695 I2C_FUNC_PROTOCOL_MANGLING; 696 } 697 698 /* i2c bus registration info */ 699 700 static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 701 .master_xfer = s3c24xx_i2c_xfer, 702 .functionality = s3c24xx_i2c_func, 703 }; 704 705 /* s3c24xx_i2c_calcdivisor 706 * 707 * return the divisor settings for a given frequency 708 */ 709 710 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 711 unsigned int *div1, unsigned int *divs) 712 { 713 unsigned int calc_divs = clkin / wanted; 714 unsigned int calc_div1; 715 716 if (calc_divs > (16*16)) 717 calc_div1 = 512; 718 else 719 calc_div1 = 16; 720 721 calc_divs += calc_div1-1; 722 calc_divs /= calc_div1; 723 724 if (calc_divs == 0) 725 calc_divs = 1; 726 if (calc_divs > 17) 727 calc_divs = 17; 728 729 *divs = calc_divs; 730 *div1 = calc_div1; 731 732 return clkin / (calc_divs * calc_div1); 733 } 734 735 /* s3c24xx_i2c_clockrate 736 * 737 * work out a divisor for the user requested frequency setting, 738 * either by the requested frequency, or scanning the acceptable 739 * range of frequencies until something is found 740 */ 741 742 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 743 { 744 struct s3c2410_platform_i2c *pdata = i2c->pdata; 745 unsigned long clkin = clk_get_rate(i2c->clk); 746 unsigned int divs, div1; 747 unsigned long target_frequency; 748 u32 iiccon; 749 int freq; 750 751 i2c->clkrate = clkin; 752 clkin /= 1000; /* clkin now in KHz */ 753 754 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 755 756 target_frequency = pdata->frequency ? pdata->frequency : 100000; 757 758 target_frequency /= 1000; /* Target frequency now in KHz */ 759 760 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 761 762 if (freq > target_frequency) { 763 dev_err(i2c->dev, 764 "Unable to achieve desired frequency %luKHz." \ 765 " Lowest achievable %dKHz\n", target_frequency, freq); 766 return -EINVAL; 767 } 768 769 *got = freq; 770 771 iiccon = readl(i2c->regs + S3C2410_IICCON); 772 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 773 iiccon |= (divs-1); 774 775 if (div1 == 512) 776 iiccon |= S3C2410_IICCON_TXDIV_512; 777 778 writel(iiccon, i2c->regs + S3C2410_IICCON); 779 780 if (i2c->quirks & QUIRK_S3C2440) { 781 unsigned long sda_delay; 782 783 if (pdata->sda_delay) { 784 sda_delay = clkin * pdata->sda_delay; 785 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 786 sda_delay = DIV_ROUND_UP(sda_delay, 5); 787 if (sda_delay > 3) 788 sda_delay = 3; 789 sda_delay |= S3C2410_IICLC_FILTER_ON; 790 } else 791 sda_delay = 0; 792 793 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 794 writel(sda_delay, i2c->regs + S3C2440_IICLC); 795 } 796 797 return 0; 798 } 799 800 #ifdef CONFIG_CPU_FREQ 801 802 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) 803 804 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, 805 unsigned long val, void *data) 806 { 807 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 808 unsigned int got; 809 int delta_f; 810 int ret; 811 812 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; 813 814 /* if we're post-change and the input clock has slowed down 815 * or at pre-change and the clock is about to speed up, then 816 * adjust our clock rate. <0 is slow, >0 speedup. 817 */ 818 819 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 820 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 821 i2c_lock_adapter(&i2c->adap); 822 ret = s3c24xx_i2c_clockrate(i2c, &got); 823 i2c_unlock_adapter(&i2c->adap); 824 825 if (ret < 0) 826 dev_err(i2c->dev, "cannot find frequency\n"); 827 else 828 dev_info(i2c->dev, "setting freq %d\n", got); 829 } 830 831 return 0; 832 } 833 834 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 835 { 836 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; 837 838 return cpufreq_register_notifier(&i2c->freq_transition, 839 CPUFREQ_TRANSITION_NOTIFIER); 840 } 841 842 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 843 { 844 cpufreq_unregister_notifier(&i2c->freq_transition, 845 CPUFREQ_TRANSITION_NOTIFIER); 846 } 847 848 #else 849 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 850 { 851 return 0; 852 } 853 854 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 855 { 856 } 857 #endif 858 859 #ifdef CONFIG_OF 860 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 861 { 862 int idx, gpio, ret; 863 864 if (i2c->quirks & QUIRK_NO_GPIO) 865 return 0; 866 867 for (idx = 0; idx < 2; idx++) { 868 gpio = of_get_gpio(i2c->dev->of_node, idx); 869 if (!gpio_is_valid(gpio)) { 870 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); 871 goto free_gpio; 872 } 873 i2c->gpios[idx] = gpio; 874 875 ret = gpio_request(gpio, "i2c-bus"); 876 if (ret) { 877 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); 878 goto free_gpio; 879 } 880 } 881 return 0; 882 883 free_gpio: 884 while (--idx >= 0) 885 gpio_free(i2c->gpios[idx]); 886 return -EINVAL; 887 } 888 889 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 890 { 891 unsigned int idx; 892 893 if (i2c->quirks & QUIRK_NO_GPIO) 894 return; 895 896 for (idx = 0; idx < 2; idx++) 897 gpio_free(i2c->gpios[idx]); 898 } 899 #else 900 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 901 { 902 return 0; 903 } 904 905 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 906 { 907 } 908 #endif 909 910 /* s3c24xx_i2c_init 911 * 912 * initialise the controller, set the IO lines and frequency 913 */ 914 915 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 916 { 917 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; 918 struct s3c2410_platform_i2c *pdata; 919 unsigned int freq; 920 921 /* get the plafrom data */ 922 923 pdata = i2c->pdata; 924 925 /* write slave address */ 926 927 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 928 929 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 930 931 writel(iicon, i2c->regs + S3C2410_IICCON); 932 933 /* we need to work out the divisors for the clock... */ 934 935 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 936 writel(0, i2c->regs + S3C2410_IICCON); 937 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 938 return -EINVAL; 939 } 940 941 /* todo - check that the i2c lines aren't being dragged anywhere */ 942 943 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 944 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); 945 946 return 0; 947 } 948 949 #ifdef CONFIG_OF 950 /* s3c24xx_i2c_parse_dt 951 * 952 * Parse the device tree node and retreive the platform data. 953 */ 954 955 static void 956 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 957 { 958 struct s3c2410_platform_i2c *pdata = i2c->pdata; 959 960 if (!np) 961 return; 962 963 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ 964 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); 965 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 966 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 967 (u32 *)&pdata->frequency); 968 } 969 #else 970 static void 971 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 972 { 973 return; 974 } 975 #endif 976 977 /* s3c24xx_i2c_probe 978 * 979 * called by the bus driver when a suitable device is found 980 */ 981 982 static int s3c24xx_i2c_probe(struct platform_device *pdev) 983 { 984 struct s3c24xx_i2c *i2c; 985 struct s3c2410_platform_i2c *pdata = NULL; 986 struct resource *res; 987 int ret; 988 989 if (!pdev->dev.of_node) { 990 pdata = pdev->dev.platform_data; 991 if (!pdata) { 992 dev_err(&pdev->dev, "no platform data\n"); 993 return -EINVAL; 994 } 995 } 996 997 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 998 if (!i2c) { 999 dev_err(&pdev->dev, "no memory for state\n"); 1000 return -ENOMEM; 1001 } 1002 1003 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1004 if (!i2c->pdata) { 1005 dev_err(&pdev->dev, "no memory for platform data\n"); 1006 return -ENOMEM; 1007 } 1008 1009 i2c->quirks = s3c24xx_get_device_quirks(pdev); 1010 if (pdata) 1011 memcpy(i2c->pdata, pdata, sizeof(*pdata)); 1012 else 1013 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); 1014 1015 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 1016 i2c->adap.owner = THIS_MODULE; 1017 i2c->adap.algo = &s3c24xx_i2c_algorithm; 1018 i2c->adap.retries = 2; 1019 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1020 i2c->tx_setup = 50; 1021 1022 init_waitqueue_head(&i2c->wait); 1023 1024 /* find the clock and enable it */ 1025 1026 i2c->dev = &pdev->dev; 1027 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1028 if (IS_ERR(i2c->clk)) { 1029 dev_err(&pdev->dev, "cannot get clock\n"); 1030 return -ENOENT; 1031 } 1032 1033 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 1034 1035 1036 /* map the registers */ 1037 1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1039 if (res == NULL) { 1040 dev_err(&pdev->dev, "cannot find IO resource\n"); 1041 return -ENOENT; 1042 } 1043 1044 i2c->regs = devm_ioremap_resource(&pdev->dev, res); 1045 1046 if (IS_ERR(i2c->regs)) 1047 return PTR_ERR(i2c->regs); 1048 1049 dev_dbg(&pdev->dev, "registers %p (%p)\n", 1050 i2c->regs, res); 1051 1052 /* setup info block for the i2c core */ 1053 1054 i2c->adap.algo_data = i2c; 1055 i2c->adap.dev.parent = &pdev->dev; 1056 1057 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); 1058 1059 /* inititalise the i2c gpio lines */ 1060 1061 if (i2c->pdata->cfg_gpio) { 1062 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); 1063 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) { 1064 return -EINVAL; 1065 } 1066 1067 /* initialise the i2c controller */ 1068 1069 clk_prepare_enable(i2c->clk); 1070 ret = s3c24xx_i2c_init(i2c); 1071 clk_disable_unprepare(i2c->clk); 1072 if (ret != 0) { 1073 dev_err(&pdev->dev, "I2C controller init failed\n"); 1074 return ret; 1075 } 1076 /* find the IRQ for this unit (note, this relies on the init call to 1077 * ensure no current IRQs pending 1078 */ 1079 1080 i2c->irq = ret = platform_get_irq(pdev, 0); 1081 if (ret <= 0) { 1082 dev_err(&pdev->dev, "cannot find IRQ\n"); 1083 return ret; 1084 } 1085 1086 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, 1087 dev_name(&pdev->dev), i2c); 1088 1089 if (ret != 0) { 1090 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1091 return ret; 1092 } 1093 1094 ret = s3c24xx_i2c_register_cpufreq(i2c); 1095 if (ret < 0) { 1096 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 1097 return ret; 1098 } 1099 1100 /* Note, previous versions of the driver used i2c_add_adapter() 1101 * to add the bus at any number. We now pass the bus number via 1102 * the platform data, so if unset it will now default to always 1103 * being bus 0. 1104 */ 1105 1106 i2c->adap.nr = i2c->pdata->bus_num; 1107 i2c->adap.dev.of_node = pdev->dev.of_node; 1108 1109 ret = i2c_add_numbered_adapter(&i2c->adap); 1110 if (ret < 0) { 1111 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 1112 s3c24xx_i2c_deregister_cpufreq(i2c); 1113 return ret; 1114 } 1115 1116 of_i2c_register_devices(&i2c->adap); 1117 platform_set_drvdata(pdev, i2c); 1118 1119 pm_runtime_enable(&pdev->dev); 1120 pm_runtime_enable(&i2c->adap.dev); 1121 1122 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1123 return 0; 1124 } 1125 1126 /* s3c24xx_i2c_remove 1127 * 1128 * called when device is removed from the bus 1129 */ 1130 1131 static int s3c24xx_i2c_remove(struct platform_device *pdev) 1132 { 1133 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1134 1135 pm_runtime_disable(&i2c->adap.dev); 1136 pm_runtime_disable(&pdev->dev); 1137 1138 s3c24xx_i2c_deregister_cpufreq(i2c); 1139 1140 i2c_del_adapter(&i2c->adap); 1141 1142 clk_disable_unprepare(i2c->clk); 1143 1144 if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) 1145 s3c24xx_i2c_dt_gpio_free(i2c); 1146 1147 return 0; 1148 } 1149 1150 #ifdef CONFIG_PM_SLEEP 1151 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1152 { 1153 struct platform_device *pdev = to_platform_device(dev); 1154 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1155 1156 i2c->suspended = 1; 1157 1158 return 0; 1159 } 1160 1161 static int s3c24xx_i2c_resume(struct device *dev) 1162 { 1163 struct platform_device *pdev = to_platform_device(dev); 1164 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1165 1166 i2c->suspended = 0; 1167 clk_prepare_enable(i2c->clk); 1168 s3c24xx_i2c_init(i2c); 1169 clk_disable_unprepare(i2c->clk); 1170 1171 return 0; 1172 } 1173 #endif 1174 1175 #ifdef CONFIG_PM 1176 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1177 #ifdef CONFIG_PM_SLEEP 1178 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 1179 .resume = s3c24xx_i2c_resume, 1180 #endif 1181 }; 1182 1183 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 1184 #else 1185 #define S3C24XX_DEV_PM_OPS NULL 1186 #endif 1187 1188 /* device driver for platform bus bits */ 1189 1190 static struct platform_driver s3c24xx_i2c_driver = { 1191 .probe = s3c24xx_i2c_probe, 1192 .remove = s3c24xx_i2c_remove, 1193 .id_table = s3c24xx_driver_ids, 1194 .driver = { 1195 .owner = THIS_MODULE, 1196 .name = "s3c-i2c", 1197 .pm = S3C24XX_DEV_PM_OPS, 1198 .of_match_table = of_match_ptr(s3c24xx_i2c_match), 1199 }, 1200 }; 1201 1202 static int __init i2c_adap_s3c_init(void) 1203 { 1204 return platform_driver_register(&s3c24xx_i2c_driver); 1205 } 1206 subsys_initcall(i2c_adap_s3c_init); 1207 1208 static void __exit i2c_adap_s3c_exit(void) 1209 { 1210 platform_driver_unregister(&s3c24xx_i2c_driver); 1211 } 1212 module_exit(i2c_adap_s3c_exit); 1213 1214 MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1215 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 1216 MODULE_LICENSE("GPL"); 1217