1 /* linux/drivers/i2c/busses/i2c-s3c2410.c 2 * 3 * Copyright (C) 2004,2005,2009 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 I2C Controller 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 26 #include <linux/i2c.h> 27 #include <linux/init.h> 28 #include <linux/time.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/errno.h> 32 #include <linux/err.h> 33 #include <linux/platform_device.h> 34 #include <linux/clk.h> 35 #include <linux/cpufreq.h> 36 #include <linux/slab.h> 37 #include <linux/io.h> 38 39 #include <asm/irq.h> 40 41 #include <plat/regs-iic.h> 42 #include <plat/iic.h> 43 44 /* i2c controller state */ 45 46 enum s3c24xx_i2c_state { 47 STATE_IDLE, 48 STATE_START, 49 STATE_READ, 50 STATE_WRITE, 51 STATE_STOP 52 }; 53 54 enum s3c24xx_i2c_type { 55 TYPE_S3C2410, 56 TYPE_S3C2440, 57 }; 58 59 struct s3c24xx_i2c { 60 spinlock_t lock; 61 wait_queue_head_t wait; 62 unsigned int suspended:1; 63 64 struct i2c_msg *msg; 65 unsigned int msg_num; 66 unsigned int msg_idx; 67 unsigned int msg_ptr; 68 69 unsigned int tx_setup; 70 unsigned int irq; 71 72 enum s3c24xx_i2c_state state; 73 unsigned long clkrate; 74 75 void __iomem *regs; 76 struct clk *clk; 77 struct device *dev; 78 struct resource *ioarea; 79 struct i2c_adapter adap; 80 81 #ifdef CONFIG_CPU_FREQ 82 struct notifier_block freq_transition; 83 #endif 84 }; 85 86 /* default platform data removed, dev should always carry data. */ 87 88 /* s3c24xx_i2c_is2440() 89 * 90 * return true is this is an s3c2440 91 */ 92 93 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c) 94 { 95 struct platform_device *pdev = to_platform_device(i2c->dev); 96 enum s3c24xx_i2c_type type; 97 98 type = platform_get_device_id(pdev)->driver_data; 99 return type == TYPE_S3C2440; 100 } 101 102 /* s3c24xx_i2c_master_complete 103 * 104 * complete the message and wake up the caller, using the given return code, 105 * or zero to mean ok. 106 */ 107 108 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 109 { 110 dev_dbg(i2c->dev, "master_complete %d\n", ret); 111 112 i2c->msg_ptr = 0; 113 i2c->msg = NULL; 114 i2c->msg_idx++; 115 i2c->msg_num = 0; 116 if (ret) 117 i2c->msg_idx = ret; 118 119 wake_up(&i2c->wait); 120 } 121 122 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 123 { 124 unsigned long tmp; 125 126 tmp = readl(i2c->regs + S3C2410_IICCON); 127 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 128 } 129 130 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 131 { 132 unsigned long tmp; 133 134 tmp = readl(i2c->regs + S3C2410_IICCON); 135 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 136 } 137 138 /* irq enable/disable functions */ 139 140 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 141 { 142 unsigned long tmp; 143 144 tmp = readl(i2c->regs + S3C2410_IICCON); 145 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 146 } 147 148 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 149 { 150 unsigned long tmp; 151 152 tmp = readl(i2c->regs + S3C2410_IICCON); 153 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 154 } 155 156 157 /* s3c24xx_i2c_message_start 158 * 159 * put the start of a message onto the bus 160 */ 161 162 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 163 struct i2c_msg *msg) 164 { 165 unsigned int addr = (msg->addr & 0x7f) << 1; 166 unsigned long stat; 167 unsigned long iiccon; 168 169 stat = 0; 170 stat |= S3C2410_IICSTAT_TXRXEN; 171 172 if (msg->flags & I2C_M_RD) { 173 stat |= S3C2410_IICSTAT_MASTER_RX; 174 addr |= 1; 175 } else 176 stat |= S3C2410_IICSTAT_MASTER_TX; 177 178 if (msg->flags & I2C_M_REV_DIR_ADDR) 179 addr ^= 1; 180 181 /* todo - check for wether ack wanted or not */ 182 s3c24xx_i2c_enable_ack(i2c); 183 184 iiccon = readl(i2c->regs + S3C2410_IICCON); 185 writel(stat, i2c->regs + S3C2410_IICSTAT); 186 187 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 188 writeb(addr, i2c->regs + S3C2410_IICDS); 189 190 /* delay here to ensure the data byte has gotten onto the bus 191 * before the transaction is started */ 192 193 ndelay(i2c->tx_setup); 194 195 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 196 writel(iiccon, i2c->regs + S3C2410_IICCON); 197 198 stat |= S3C2410_IICSTAT_START; 199 writel(stat, i2c->regs + S3C2410_IICSTAT); 200 } 201 202 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 203 { 204 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 205 206 dev_dbg(i2c->dev, "STOP\n"); 207 208 /* stop the transfer */ 209 iicstat &= ~S3C2410_IICSTAT_START; 210 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 211 212 i2c->state = STATE_STOP; 213 214 s3c24xx_i2c_master_complete(i2c, ret); 215 s3c24xx_i2c_disable_irq(i2c); 216 } 217 218 /* helper functions to determine the current state in the set of 219 * messages we are sending */ 220 221 /* is_lastmsg() 222 * 223 * returns TRUE if the current message is the last in the set 224 */ 225 226 static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 227 { 228 return i2c->msg_idx >= (i2c->msg_num - 1); 229 } 230 231 /* is_msglast 232 * 233 * returns TRUE if we this is the last byte in the current message 234 */ 235 236 static inline int is_msglast(struct s3c24xx_i2c *i2c) 237 { 238 return i2c->msg_ptr == i2c->msg->len-1; 239 } 240 241 /* is_msgend 242 * 243 * returns TRUE if we reached the end of the current message 244 */ 245 246 static inline int is_msgend(struct s3c24xx_i2c *i2c) 247 { 248 return i2c->msg_ptr >= i2c->msg->len; 249 } 250 251 /* i2c_s3c_irq_nextbyte 252 * 253 * process an interrupt and work out what to do 254 */ 255 256 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 257 { 258 unsigned long tmp; 259 unsigned char byte; 260 int ret = 0; 261 262 switch (i2c->state) { 263 264 case STATE_IDLE: 265 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 266 goto out; 267 268 case STATE_STOP: 269 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 270 s3c24xx_i2c_disable_irq(i2c); 271 goto out_ack; 272 273 case STATE_START: 274 /* last thing we did was send a start condition on the 275 * bus, or started a new i2c message 276 */ 277 278 if (iicstat & S3C2410_IICSTAT_LASTBIT && 279 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 280 /* ack was not received... */ 281 282 dev_dbg(i2c->dev, "ack was not received\n"); 283 s3c24xx_i2c_stop(i2c, -ENXIO); 284 goto out_ack; 285 } 286 287 if (i2c->msg->flags & I2C_M_RD) 288 i2c->state = STATE_READ; 289 else 290 i2c->state = STATE_WRITE; 291 292 /* terminate the transfer if there is nothing to do 293 * as this is used by the i2c probe to find devices. */ 294 295 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 296 s3c24xx_i2c_stop(i2c, 0); 297 goto out_ack; 298 } 299 300 if (i2c->state == STATE_READ) 301 goto prepare_read; 302 303 /* fall through to the write state, as we will need to 304 * send a byte as well */ 305 306 case STATE_WRITE: 307 /* we are writing data to the device... check for the 308 * end of the message, and if so, work out what to do 309 */ 310 311 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 312 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 313 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 314 315 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 316 goto out_ack; 317 } 318 } 319 320 retry_write: 321 322 if (!is_msgend(i2c)) { 323 byte = i2c->msg->buf[i2c->msg_ptr++]; 324 writeb(byte, i2c->regs + S3C2410_IICDS); 325 326 /* delay after writing the byte to allow the 327 * data setup time on the bus, as writing the 328 * data to the register causes the first bit 329 * to appear on SDA, and SCL will change as 330 * soon as the interrupt is acknowledged */ 331 332 ndelay(i2c->tx_setup); 333 334 } else if (!is_lastmsg(i2c)) { 335 /* we need to go to the next i2c message */ 336 337 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 338 339 i2c->msg_ptr = 0; 340 i2c->msg_idx++; 341 i2c->msg++; 342 343 /* check to see if we need to do another message */ 344 if (i2c->msg->flags & I2C_M_NOSTART) { 345 346 if (i2c->msg->flags & I2C_M_RD) { 347 /* cannot do this, the controller 348 * forces us to send a new START 349 * when we change direction */ 350 351 s3c24xx_i2c_stop(i2c, -EINVAL); 352 } 353 354 goto retry_write; 355 } else { 356 /* send the new start */ 357 s3c24xx_i2c_message_start(i2c, i2c->msg); 358 i2c->state = STATE_START; 359 } 360 361 } else { 362 /* send stop */ 363 364 s3c24xx_i2c_stop(i2c, 0); 365 } 366 break; 367 368 case STATE_READ: 369 /* we have a byte of data in the data register, do 370 * something with it, and then work out wether we are 371 * going to do any more read/write 372 */ 373 374 byte = readb(i2c->regs + S3C2410_IICDS); 375 i2c->msg->buf[i2c->msg_ptr++] = byte; 376 377 prepare_read: 378 if (is_msglast(i2c)) { 379 /* last byte of buffer */ 380 381 if (is_lastmsg(i2c)) 382 s3c24xx_i2c_disable_ack(i2c); 383 384 } else if (is_msgend(i2c)) { 385 /* ok, we've read the entire buffer, see if there 386 * is anything else we need to do */ 387 388 if (is_lastmsg(i2c)) { 389 /* last message, send stop and complete */ 390 dev_dbg(i2c->dev, "READ: Send Stop\n"); 391 392 s3c24xx_i2c_stop(i2c, 0); 393 } else { 394 /* go to the next transfer */ 395 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 396 397 i2c->msg_ptr = 0; 398 i2c->msg_idx++; 399 i2c->msg++; 400 } 401 } 402 403 break; 404 } 405 406 /* acknowlegde the IRQ and get back on with the work */ 407 408 out_ack: 409 tmp = readl(i2c->regs + S3C2410_IICCON); 410 tmp &= ~S3C2410_IICCON_IRQPEND; 411 writel(tmp, i2c->regs + S3C2410_IICCON); 412 out: 413 return ret; 414 } 415 416 /* s3c24xx_i2c_irq 417 * 418 * top level IRQ servicing routine 419 */ 420 421 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 422 { 423 struct s3c24xx_i2c *i2c = dev_id; 424 unsigned long status; 425 unsigned long tmp; 426 427 status = readl(i2c->regs + S3C2410_IICSTAT); 428 429 if (status & S3C2410_IICSTAT_ARBITR) { 430 /* deal with arbitration loss */ 431 dev_err(i2c->dev, "deal with arbitration loss\n"); 432 } 433 434 if (i2c->state == STATE_IDLE) { 435 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 436 437 tmp = readl(i2c->regs + S3C2410_IICCON); 438 tmp &= ~S3C2410_IICCON_IRQPEND; 439 writel(tmp, i2c->regs + S3C2410_IICCON); 440 goto out; 441 } 442 443 /* pretty much this leaves us with the fact that we've 444 * transmitted or received whatever byte we last sent */ 445 446 i2c_s3c_irq_nextbyte(i2c, status); 447 448 out: 449 return IRQ_HANDLED; 450 } 451 452 453 /* s3c24xx_i2c_set_master 454 * 455 * get the i2c bus for a master transaction 456 */ 457 458 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 459 { 460 unsigned long iicstat; 461 int timeout = 400; 462 463 while (timeout-- > 0) { 464 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 465 466 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 467 return 0; 468 469 msleep(1); 470 } 471 472 return -ETIMEDOUT; 473 } 474 475 /* s3c24xx_i2c_doxfer 476 * 477 * this starts an i2c transfer 478 */ 479 480 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 481 struct i2c_msg *msgs, int num) 482 { 483 unsigned long iicstat, timeout; 484 int spins = 20; 485 int ret; 486 487 if (i2c->suspended) 488 return -EIO; 489 490 ret = s3c24xx_i2c_set_master(i2c); 491 if (ret != 0) { 492 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 493 ret = -EAGAIN; 494 goto out; 495 } 496 497 spin_lock_irq(&i2c->lock); 498 499 i2c->msg = msgs; 500 i2c->msg_num = num; 501 i2c->msg_ptr = 0; 502 i2c->msg_idx = 0; 503 i2c->state = STATE_START; 504 505 s3c24xx_i2c_enable_irq(i2c); 506 s3c24xx_i2c_message_start(i2c, msgs); 507 spin_unlock_irq(&i2c->lock); 508 509 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 510 511 ret = i2c->msg_idx; 512 513 /* having these next two as dev_err() makes life very 514 * noisy when doing an i2cdetect */ 515 516 if (timeout == 0) 517 dev_dbg(i2c->dev, "timeout\n"); 518 else if (ret != num) 519 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 520 521 /* ensure the stop has been through the bus */ 522 523 dev_dbg(i2c->dev, "waiting for bus idle\n"); 524 525 /* first, try busy waiting briefly */ 526 do { 527 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 528 } while ((iicstat & S3C2410_IICSTAT_START) && --spins); 529 530 /* if that timed out sleep */ 531 if (!spins) { 532 msleep(1); 533 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 534 } 535 536 if (iicstat & S3C2410_IICSTAT_START) 537 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 538 539 out: 540 return ret; 541 } 542 543 /* s3c24xx_i2c_xfer 544 * 545 * first port of call from the i2c bus code when an message needs 546 * transferring across the i2c bus. 547 */ 548 549 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 550 struct i2c_msg *msgs, int num) 551 { 552 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 553 int retry; 554 int ret; 555 556 clk_enable(i2c->clk); 557 558 for (retry = 0; retry < adap->retries; retry++) { 559 560 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 561 562 if (ret != -EAGAIN) { 563 clk_disable(i2c->clk); 564 return ret; 565 } 566 567 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 568 569 udelay(100); 570 } 571 572 clk_disable(i2c->clk); 573 return -EREMOTEIO; 574 } 575 576 /* declare our i2c functionality */ 577 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 578 { 579 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 580 } 581 582 /* i2c bus registration info */ 583 584 static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 585 .master_xfer = s3c24xx_i2c_xfer, 586 .functionality = s3c24xx_i2c_func, 587 }; 588 589 /* s3c24xx_i2c_calcdivisor 590 * 591 * return the divisor settings for a given frequency 592 */ 593 594 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 595 unsigned int *div1, unsigned int *divs) 596 { 597 unsigned int calc_divs = clkin / wanted; 598 unsigned int calc_div1; 599 600 if (calc_divs > (16*16)) 601 calc_div1 = 512; 602 else 603 calc_div1 = 16; 604 605 calc_divs += calc_div1-1; 606 calc_divs /= calc_div1; 607 608 if (calc_divs == 0) 609 calc_divs = 1; 610 if (calc_divs > 17) 611 calc_divs = 17; 612 613 *divs = calc_divs; 614 *div1 = calc_div1; 615 616 return clkin / (calc_divs * calc_div1); 617 } 618 619 /* s3c24xx_i2c_clockrate 620 * 621 * work out a divisor for the user requested frequency setting, 622 * either by the requested frequency, or scanning the acceptable 623 * range of frequencies until something is found 624 */ 625 626 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 627 { 628 struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data; 629 unsigned long clkin = clk_get_rate(i2c->clk); 630 unsigned int divs, div1; 631 unsigned long target_frequency; 632 u32 iiccon; 633 int freq; 634 635 i2c->clkrate = clkin; 636 clkin /= 1000; /* clkin now in KHz */ 637 638 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 639 640 target_frequency = pdata->frequency ? pdata->frequency : 100000; 641 642 target_frequency /= 1000; /* Target frequency now in KHz */ 643 644 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 645 646 if (freq > target_frequency) { 647 dev_err(i2c->dev, 648 "Unable to achieve desired frequency %luKHz." \ 649 " Lowest achievable %dKHz\n", target_frequency, freq); 650 return -EINVAL; 651 } 652 653 *got = freq; 654 655 iiccon = readl(i2c->regs + S3C2410_IICCON); 656 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 657 iiccon |= (divs-1); 658 659 if (div1 == 512) 660 iiccon |= S3C2410_IICCON_TXDIV_512; 661 662 writel(iiccon, i2c->regs + S3C2410_IICCON); 663 664 if (s3c24xx_i2c_is2440(i2c)) { 665 unsigned long sda_delay; 666 667 if (pdata->sda_delay) { 668 sda_delay = clkin * pdata->sda_delay; 669 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 670 sda_delay = DIV_ROUND_UP(sda_delay, 5); 671 if (sda_delay > 3) 672 sda_delay = 3; 673 sda_delay |= S3C2410_IICLC_FILTER_ON; 674 } else 675 sda_delay = 0; 676 677 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 678 writel(sda_delay, i2c->regs + S3C2440_IICLC); 679 } 680 681 return 0; 682 } 683 684 #ifdef CONFIG_CPU_FREQ 685 686 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) 687 688 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, 689 unsigned long val, void *data) 690 { 691 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 692 unsigned long flags; 693 unsigned int got; 694 int delta_f; 695 int ret; 696 697 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; 698 699 /* if we're post-change and the input clock has slowed down 700 * or at pre-change and the clock is about to speed up, then 701 * adjust our clock rate. <0 is slow, >0 speedup. 702 */ 703 704 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 705 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 706 spin_lock_irqsave(&i2c->lock, flags); 707 ret = s3c24xx_i2c_clockrate(i2c, &got); 708 spin_unlock_irqrestore(&i2c->lock, flags); 709 710 if (ret < 0) 711 dev_err(i2c->dev, "cannot find frequency\n"); 712 else 713 dev_info(i2c->dev, "setting freq %d\n", got); 714 } 715 716 return 0; 717 } 718 719 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 720 { 721 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; 722 723 return cpufreq_register_notifier(&i2c->freq_transition, 724 CPUFREQ_TRANSITION_NOTIFIER); 725 } 726 727 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 728 { 729 cpufreq_unregister_notifier(&i2c->freq_transition, 730 CPUFREQ_TRANSITION_NOTIFIER); 731 } 732 733 #else 734 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 735 { 736 return 0; 737 } 738 739 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 740 { 741 } 742 #endif 743 744 /* s3c24xx_i2c_init 745 * 746 * initialise the controller, set the IO lines and frequency 747 */ 748 749 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 750 { 751 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; 752 struct s3c2410_platform_i2c *pdata; 753 unsigned int freq; 754 755 /* get the plafrom data */ 756 757 pdata = i2c->dev->platform_data; 758 759 /* inititalise the gpio */ 760 761 if (pdata->cfg_gpio) 762 pdata->cfg_gpio(to_platform_device(i2c->dev)); 763 764 /* write slave address */ 765 766 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 767 768 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 769 770 writel(iicon, i2c->regs + S3C2410_IICCON); 771 772 /* we need to work out the divisors for the clock... */ 773 774 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 775 writel(0, i2c->regs + S3C2410_IICCON); 776 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 777 return -EINVAL; 778 } 779 780 /* todo - check that the i2c lines aren't being dragged anywhere */ 781 782 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 783 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); 784 785 return 0; 786 } 787 788 /* s3c24xx_i2c_probe 789 * 790 * called by the bus driver when a suitable device is found 791 */ 792 793 static int s3c24xx_i2c_probe(struct platform_device *pdev) 794 { 795 struct s3c24xx_i2c *i2c; 796 struct s3c2410_platform_i2c *pdata; 797 struct resource *res; 798 int ret; 799 800 pdata = pdev->dev.platform_data; 801 if (!pdata) { 802 dev_err(&pdev->dev, "no platform data\n"); 803 return -EINVAL; 804 } 805 806 i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL); 807 if (!i2c) { 808 dev_err(&pdev->dev, "no memory for state\n"); 809 return -ENOMEM; 810 } 811 812 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 813 i2c->adap.owner = THIS_MODULE; 814 i2c->adap.algo = &s3c24xx_i2c_algorithm; 815 i2c->adap.retries = 2; 816 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 817 i2c->tx_setup = 50; 818 819 spin_lock_init(&i2c->lock); 820 init_waitqueue_head(&i2c->wait); 821 822 /* find the clock and enable it */ 823 824 i2c->dev = &pdev->dev; 825 i2c->clk = clk_get(&pdev->dev, "i2c"); 826 if (IS_ERR(i2c->clk)) { 827 dev_err(&pdev->dev, "cannot get clock\n"); 828 ret = -ENOENT; 829 goto err_noclk; 830 } 831 832 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 833 834 clk_enable(i2c->clk); 835 836 /* map the registers */ 837 838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 839 if (res == NULL) { 840 dev_err(&pdev->dev, "cannot find IO resource\n"); 841 ret = -ENOENT; 842 goto err_clk; 843 } 844 845 i2c->ioarea = request_mem_region(res->start, resource_size(res), 846 pdev->name); 847 848 if (i2c->ioarea == NULL) { 849 dev_err(&pdev->dev, "cannot request IO\n"); 850 ret = -ENXIO; 851 goto err_clk; 852 } 853 854 i2c->regs = ioremap(res->start, resource_size(res)); 855 856 if (i2c->regs == NULL) { 857 dev_err(&pdev->dev, "cannot map IO\n"); 858 ret = -ENXIO; 859 goto err_ioarea; 860 } 861 862 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", 863 i2c->regs, i2c->ioarea, res); 864 865 /* setup info block for the i2c core */ 866 867 i2c->adap.algo_data = i2c; 868 i2c->adap.dev.parent = &pdev->dev; 869 870 /* initialise the i2c controller */ 871 872 ret = s3c24xx_i2c_init(i2c); 873 if (ret != 0) 874 goto err_iomap; 875 876 /* find the IRQ for this unit (note, this relies on the init call to 877 * ensure no current IRQs pending 878 */ 879 880 i2c->irq = ret = platform_get_irq(pdev, 0); 881 if (ret <= 0) { 882 dev_err(&pdev->dev, "cannot find IRQ\n"); 883 goto err_iomap; 884 } 885 886 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED, 887 dev_name(&pdev->dev), i2c); 888 889 if (ret != 0) { 890 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 891 goto err_iomap; 892 } 893 894 ret = s3c24xx_i2c_register_cpufreq(i2c); 895 if (ret < 0) { 896 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 897 goto err_irq; 898 } 899 900 /* Note, previous versions of the driver used i2c_add_adapter() 901 * to add the bus at any number. We now pass the bus number via 902 * the platform data, so if unset it will now default to always 903 * being bus 0. 904 */ 905 906 i2c->adap.nr = pdata->bus_num; 907 908 ret = i2c_add_numbered_adapter(&i2c->adap); 909 if (ret < 0) { 910 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 911 goto err_cpufreq; 912 } 913 914 platform_set_drvdata(pdev, i2c); 915 916 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 917 clk_disable(i2c->clk); 918 return 0; 919 920 err_cpufreq: 921 s3c24xx_i2c_deregister_cpufreq(i2c); 922 923 err_irq: 924 free_irq(i2c->irq, i2c); 925 926 err_iomap: 927 iounmap(i2c->regs); 928 929 err_ioarea: 930 release_resource(i2c->ioarea); 931 kfree(i2c->ioarea); 932 933 err_clk: 934 clk_disable(i2c->clk); 935 clk_put(i2c->clk); 936 937 err_noclk: 938 kfree(i2c); 939 return ret; 940 } 941 942 /* s3c24xx_i2c_remove 943 * 944 * called when device is removed from the bus 945 */ 946 947 static int s3c24xx_i2c_remove(struct platform_device *pdev) 948 { 949 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 950 951 s3c24xx_i2c_deregister_cpufreq(i2c); 952 953 i2c_del_adapter(&i2c->adap); 954 free_irq(i2c->irq, i2c); 955 956 clk_disable(i2c->clk); 957 clk_put(i2c->clk); 958 959 iounmap(i2c->regs); 960 961 release_resource(i2c->ioarea); 962 kfree(i2c->ioarea); 963 kfree(i2c); 964 965 return 0; 966 } 967 968 #ifdef CONFIG_PM 969 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 970 { 971 struct platform_device *pdev = to_platform_device(dev); 972 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 973 974 i2c->suspended = 1; 975 976 return 0; 977 } 978 979 static int s3c24xx_i2c_resume(struct device *dev) 980 { 981 struct platform_device *pdev = to_platform_device(dev); 982 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 983 984 i2c->suspended = 0; 985 clk_enable(i2c->clk); 986 s3c24xx_i2c_init(i2c); 987 clk_disable(i2c->clk); 988 989 return 0; 990 } 991 992 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 993 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 994 .resume = s3c24xx_i2c_resume, 995 }; 996 997 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 998 #else 999 #define S3C24XX_DEV_PM_OPS NULL 1000 #endif 1001 1002 /* device driver for platform bus bits */ 1003 1004 static struct platform_device_id s3c24xx_driver_ids[] = { 1005 { 1006 .name = "s3c2410-i2c", 1007 .driver_data = TYPE_S3C2410, 1008 }, { 1009 .name = "s3c2440-i2c", 1010 .driver_data = TYPE_S3C2440, 1011 }, { }, 1012 }; 1013 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 1014 1015 static struct platform_driver s3c24xx_i2c_driver = { 1016 .probe = s3c24xx_i2c_probe, 1017 .remove = s3c24xx_i2c_remove, 1018 .id_table = s3c24xx_driver_ids, 1019 .driver = { 1020 .owner = THIS_MODULE, 1021 .name = "s3c-i2c", 1022 .pm = S3C24XX_DEV_PM_OPS, 1023 }, 1024 }; 1025 1026 static int __init i2c_adap_s3c_init(void) 1027 { 1028 return platform_driver_register(&s3c24xx_i2c_driver); 1029 } 1030 subsys_initcall(i2c_adap_s3c_init); 1031 1032 static void __exit i2c_adap_s3c_exit(void) 1033 { 1034 platform_driver_unregister(&s3c24xx_i2c_driver); 1035 } 1036 module_exit(i2c_adap_s3c_exit); 1037 1038 MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1039 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 1040 MODULE_LICENSE("GPL"); 1041