1 /* linux/drivers/i2c/busses/i2c-s3c2410.c 2 * 3 * Copyright (C) 2004,2005,2009 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 I2C Controller 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 22 #include <linux/i2c.h> 23 #include <linux/init.h> 24 #include <linux/time.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/errno.h> 28 #include <linux/err.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/clk.h> 32 #include <linux/cpufreq.h> 33 #include <linux/slab.h> 34 #include <linux/io.h> 35 #include <linux/of.h> 36 #include <linux/of_gpio.h> 37 #include <linux/pinctrl/consumer.h> 38 39 #include <asm/irq.h> 40 41 #include <linux/platform_data/i2c-s3c2410.h> 42 43 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ 44 45 #define S3C2410_IICCON 0x00 46 #define S3C2410_IICSTAT 0x04 47 #define S3C2410_IICADD 0x08 48 #define S3C2410_IICDS 0x0C 49 #define S3C2440_IICLC 0x10 50 51 #define S3C2410_IICCON_ACKEN (1 << 7) 52 #define S3C2410_IICCON_TXDIV_16 (0 << 6) 53 #define S3C2410_IICCON_TXDIV_512 (1 << 6) 54 #define S3C2410_IICCON_IRQEN (1 << 5) 55 #define S3C2410_IICCON_IRQPEND (1 << 4) 56 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf) 57 #define S3C2410_IICCON_SCALEMASK (0xf) 58 59 #define S3C2410_IICSTAT_MASTER_RX (2 << 6) 60 #define S3C2410_IICSTAT_MASTER_TX (3 << 6) 61 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6) 62 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6) 63 #define S3C2410_IICSTAT_MODEMASK (3 << 6) 64 65 #define S3C2410_IICSTAT_START (1 << 5) 66 #define S3C2410_IICSTAT_BUSBUSY (1 << 5) 67 #define S3C2410_IICSTAT_TXRXEN (1 << 4) 68 #define S3C2410_IICSTAT_ARBITR (1 << 3) 69 #define S3C2410_IICSTAT_ASSLAVE (1 << 2) 70 #define S3C2410_IICSTAT_ADDR0 (1 << 1) 71 #define S3C2410_IICSTAT_LASTBIT (1 << 0) 72 73 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) 74 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) 75 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0) 76 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) 77 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) 78 79 #define S3C2410_IICLC_FILTER_ON (1 << 2) 80 81 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ 82 #define QUIRK_S3C2440 (1 << 0) 83 #define QUIRK_HDMIPHY (1 << 1) 84 #define QUIRK_NO_GPIO (1 << 2) 85 #define QUIRK_POLL (1 << 3) 86 87 /* Max time to wait for bus to become idle after a xfer (in us) */ 88 #define S3C2410_IDLE_TIMEOUT 5000 89 90 /* i2c controller state */ 91 enum s3c24xx_i2c_state { 92 STATE_IDLE, 93 STATE_START, 94 STATE_READ, 95 STATE_WRITE, 96 STATE_STOP 97 }; 98 99 struct s3c24xx_i2c { 100 wait_queue_head_t wait; 101 kernel_ulong_t quirks; 102 unsigned int suspended:1; 103 104 struct i2c_msg *msg; 105 unsigned int msg_num; 106 unsigned int msg_idx; 107 unsigned int msg_ptr; 108 109 unsigned int tx_setup; 110 unsigned int irq; 111 112 enum s3c24xx_i2c_state state; 113 unsigned long clkrate; 114 115 void __iomem *regs; 116 struct clk *clk; 117 struct device *dev; 118 struct i2c_adapter adap; 119 120 struct s3c2410_platform_i2c *pdata; 121 int gpios[2]; 122 struct pinctrl *pctrl; 123 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ) 124 struct notifier_block freq_transition; 125 #endif 126 }; 127 128 static struct platform_device_id s3c24xx_driver_ids[] = { 129 { 130 .name = "s3c2410-i2c", 131 .driver_data = 0, 132 }, { 133 .name = "s3c2440-i2c", 134 .driver_data = QUIRK_S3C2440, 135 }, { 136 .name = "s3c2440-hdmiphy-i2c", 137 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, 138 }, { }, 139 }; 140 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 141 142 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat); 143 144 #ifdef CONFIG_OF 145 static const struct of_device_id s3c24xx_i2c_match[] = { 146 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, 147 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, 148 { .compatible = "samsung,s3c2440-hdmiphy-i2c", 149 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, 150 { .compatible = "samsung,exynos5440-i2c", 151 .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) }, 152 { .compatible = "samsung,exynos5-sata-phy-i2c", 153 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) }, 154 {}, 155 }; 156 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); 157 #endif 158 159 /* s3c24xx_get_device_quirks 160 * 161 * Get controller type either from device tree or platform device variant. 162 */ 163 164 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev) 165 { 166 if (pdev->dev.of_node) { 167 const struct of_device_id *match; 168 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); 169 return (kernel_ulong_t)match->data; 170 } 171 172 return platform_get_device_id(pdev)->driver_data; 173 } 174 175 /* s3c24xx_i2c_master_complete 176 * 177 * complete the message and wake up the caller, using the given return code, 178 * or zero to mean ok. 179 */ 180 181 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 182 { 183 dev_dbg(i2c->dev, "master_complete %d\n", ret); 184 185 i2c->msg_ptr = 0; 186 i2c->msg = NULL; 187 i2c->msg_idx++; 188 i2c->msg_num = 0; 189 if (ret) 190 i2c->msg_idx = ret; 191 192 if (!(i2c->quirks & QUIRK_POLL)) 193 wake_up(&i2c->wait); 194 } 195 196 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 197 { 198 unsigned long tmp; 199 200 tmp = readl(i2c->regs + S3C2410_IICCON); 201 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 202 } 203 204 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 205 { 206 unsigned long tmp; 207 208 tmp = readl(i2c->regs + S3C2410_IICCON); 209 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 210 } 211 212 /* irq enable/disable functions */ 213 214 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 215 { 216 unsigned long tmp; 217 218 tmp = readl(i2c->regs + S3C2410_IICCON); 219 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 220 } 221 222 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 223 { 224 unsigned long tmp; 225 226 tmp = readl(i2c->regs + S3C2410_IICCON); 227 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 228 } 229 230 static bool is_ack(struct s3c24xx_i2c *i2c) 231 { 232 int tries; 233 234 for (tries = 50; tries; --tries) { 235 if (readl(i2c->regs + S3C2410_IICCON) 236 & S3C2410_IICCON_IRQPEND) { 237 if (!(readl(i2c->regs + S3C2410_IICSTAT) 238 & S3C2410_IICSTAT_LASTBIT)) 239 return true; 240 } 241 usleep_range(1000, 2000); 242 } 243 dev_err(i2c->dev, "ack was not received\n"); 244 return false; 245 } 246 247 /* s3c24xx_i2c_message_start 248 * 249 * put the start of a message onto the bus 250 */ 251 252 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 253 struct i2c_msg *msg) 254 { 255 unsigned int addr = (msg->addr & 0x7f) << 1; 256 unsigned long stat; 257 unsigned long iiccon; 258 259 stat = 0; 260 stat |= S3C2410_IICSTAT_TXRXEN; 261 262 if (msg->flags & I2C_M_RD) { 263 stat |= S3C2410_IICSTAT_MASTER_RX; 264 addr |= 1; 265 } else 266 stat |= S3C2410_IICSTAT_MASTER_TX; 267 268 if (msg->flags & I2C_M_REV_DIR_ADDR) 269 addr ^= 1; 270 271 /* todo - check for whether ack wanted or not */ 272 s3c24xx_i2c_enable_ack(i2c); 273 274 iiccon = readl(i2c->regs + S3C2410_IICCON); 275 writel(stat, i2c->regs + S3C2410_IICSTAT); 276 277 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 278 writeb(addr, i2c->regs + S3C2410_IICDS); 279 280 /* delay here to ensure the data byte has gotten onto the bus 281 * before the transaction is started */ 282 283 ndelay(i2c->tx_setup); 284 285 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 286 writel(iiccon, i2c->regs + S3C2410_IICCON); 287 288 stat |= S3C2410_IICSTAT_START; 289 writel(stat, i2c->regs + S3C2410_IICSTAT); 290 291 if (i2c->quirks & QUIRK_POLL) { 292 while ((i2c->msg_num != 0) && is_ack(i2c)) { 293 i2c_s3c_irq_nextbyte(i2c, stat); 294 stat = readl(i2c->regs + S3C2410_IICSTAT); 295 296 if (stat & S3C2410_IICSTAT_ARBITR) 297 dev_err(i2c->dev, "deal with arbitration loss\n"); 298 } 299 } 300 } 301 302 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 303 { 304 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 305 306 dev_dbg(i2c->dev, "STOP\n"); 307 308 /* 309 * The datasheet says that the STOP sequence should be: 310 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') 311 * 2) I2CCON.4 = 0 - Clear IRQPEND 312 * 3) Wait until the stop condition takes effect. 313 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN 314 * 315 * Where, step "4*" is only for buses with the "HDMIPHY" quirk. 316 * 317 * However, after much experimentation, it appears that: 318 * a) normal buses automatically clear BUSY and transition from 319 * Master->Slave when they complete generating a STOP condition. 320 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 321 * after starting the STOP generation here. 322 * b) HDMIPHY bus does neither, so there is no way to do step 3. 323 * There is no indication when this bus has finished generating 324 * STOP. 325 * 326 * In fact, we have found that as soon as the IRQPEND bit is cleared in 327 * step 2, the HDMIPHY bus generates the STOP condition, and then 328 * immediately starts transferring another data byte, even though the 329 * bus is supposedly stopped. This is presumably because the bus is 330 * still in "Master" mode, and its BUSY bit is still set. 331 * 332 * To avoid these extra post-STOP transactions on HDMI phy devices, we 333 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, 334 * instead of first generating a proper STOP condition. This should 335 * float SDA & SCK terminating the transfer. Subsequent transfers 336 * start with a proper START condition, and proceed normally. 337 * 338 * The HDMIPHY bus is an internal bus that always has exactly two 339 * devices, the host as Master and the HDMIPHY device as the slave. 340 * Skipping the STOP condition has been tested on this bus and works. 341 */ 342 if (i2c->quirks & QUIRK_HDMIPHY) { 343 /* Stop driving the I2C pins */ 344 iicstat &= ~S3C2410_IICSTAT_TXRXEN; 345 } else { 346 /* stop the transfer */ 347 iicstat &= ~S3C2410_IICSTAT_START; 348 } 349 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 350 351 i2c->state = STATE_STOP; 352 353 s3c24xx_i2c_master_complete(i2c, ret); 354 s3c24xx_i2c_disable_irq(i2c); 355 } 356 357 /* helper functions to determine the current state in the set of 358 * messages we are sending */ 359 360 /* is_lastmsg() 361 * 362 * returns TRUE if the current message is the last in the set 363 */ 364 365 static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 366 { 367 return i2c->msg_idx >= (i2c->msg_num - 1); 368 } 369 370 /* is_msglast 371 * 372 * returns TRUE if we this is the last byte in the current message 373 */ 374 375 static inline int is_msglast(struct s3c24xx_i2c *i2c) 376 { 377 /* msg->len is always 1 for the first byte of smbus block read. 378 * Actual length will be read from slave. More bytes will be 379 * read according to the length then. */ 380 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 381 return 0; 382 383 return i2c->msg_ptr == i2c->msg->len-1; 384 } 385 386 /* is_msgend 387 * 388 * returns TRUE if we reached the end of the current message 389 */ 390 391 static inline int is_msgend(struct s3c24xx_i2c *i2c) 392 { 393 return i2c->msg_ptr >= i2c->msg->len; 394 } 395 396 /* i2c_s3c_irq_nextbyte 397 * 398 * process an interrupt and work out what to do 399 */ 400 401 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 402 { 403 unsigned long tmp; 404 unsigned char byte; 405 int ret = 0; 406 407 switch (i2c->state) { 408 409 case STATE_IDLE: 410 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 411 goto out; 412 413 case STATE_STOP: 414 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 415 s3c24xx_i2c_disable_irq(i2c); 416 goto out_ack; 417 418 case STATE_START: 419 /* last thing we did was send a start condition on the 420 * bus, or started a new i2c message 421 */ 422 423 if (iicstat & S3C2410_IICSTAT_LASTBIT && 424 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 425 /* ack was not received... */ 426 427 dev_dbg(i2c->dev, "ack was not received\n"); 428 s3c24xx_i2c_stop(i2c, -ENXIO); 429 goto out_ack; 430 } 431 432 if (i2c->msg->flags & I2C_M_RD) 433 i2c->state = STATE_READ; 434 else 435 i2c->state = STATE_WRITE; 436 437 /* terminate the transfer if there is nothing to do 438 * as this is used by the i2c probe to find devices. */ 439 440 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 441 s3c24xx_i2c_stop(i2c, 0); 442 goto out_ack; 443 } 444 445 if (i2c->state == STATE_READ) 446 goto prepare_read; 447 448 /* fall through to the write state, as we will need to 449 * send a byte as well */ 450 451 case STATE_WRITE: 452 /* we are writing data to the device... check for the 453 * end of the message, and if so, work out what to do 454 */ 455 456 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 457 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 458 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 459 460 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 461 goto out_ack; 462 } 463 } 464 465 retry_write: 466 467 if (!is_msgend(i2c)) { 468 byte = i2c->msg->buf[i2c->msg_ptr++]; 469 writeb(byte, i2c->regs + S3C2410_IICDS); 470 471 /* delay after writing the byte to allow the 472 * data setup time on the bus, as writing the 473 * data to the register causes the first bit 474 * to appear on SDA, and SCL will change as 475 * soon as the interrupt is acknowledged */ 476 477 ndelay(i2c->tx_setup); 478 479 } else if (!is_lastmsg(i2c)) { 480 /* we need to go to the next i2c message */ 481 482 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 483 484 i2c->msg_ptr = 0; 485 i2c->msg_idx++; 486 i2c->msg++; 487 488 /* check to see if we need to do another message */ 489 if (i2c->msg->flags & I2C_M_NOSTART) { 490 491 if (i2c->msg->flags & I2C_M_RD) { 492 /* cannot do this, the controller 493 * forces us to send a new START 494 * when we change direction */ 495 496 s3c24xx_i2c_stop(i2c, -EINVAL); 497 } 498 499 goto retry_write; 500 } else { 501 /* send the new start */ 502 s3c24xx_i2c_message_start(i2c, i2c->msg); 503 i2c->state = STATE_START; 504 } 505 506 } else { 507 /* send stop */ 508 509 s3c24xx_i2c_stop(i2c, 0); 510 } 511 break; 512 513 case STATE_READ: 514 /* we have a byte of data in the data register, do 515 * something with it, and then work out whether we are 516 * going to do any more read/write 517 */ 518 519 byte = readb(i2c->regs + S3C2410_IICDS); 520 i2c->msg->buf[i2c->msg_ptr++] = byte; 521 522 /* Add actual length to read for smbus block read */ 523 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 524 i2c->msg->len += byte; 525 prepare_read: 526 if (is_msglast(i2c)) { 527 /* last byte of buffer */ 528 529 if (is_lastmsg(i2c)) 530 s3c24xx_i2c_disable_ack(i2c); 531 532 } else if (is_msgend(i2c)) { 533 /* ok, we've read the entire buffer, see if there 534 * is anything else we need to do */ 535 536 if (is_lastmsg(i2c)) { 537 /* last message, send stop and complete */ 538 dev_dbg(i2c->dev, "READ: Send Stop\n"); 539 540 s3c24xx_i2c_stop(i2c, 0); 541 } else { 542 /* go to the next transfer */ 543 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 544 545 i2c->msg_ptr = 0; 546 i2c->msg_idx++; 547 i2c->msg++; 548 } 549 } 550 551 break; 552 } 553 554 /* acknowlegde the IRQ and get back on with the work */ 555 556 out_ack: 557 tmp = readl(i2c->regs + S3C2410_IICCON); 558 tmp &= ~S3C2410_IICCON_IRQPEND; 559 writel(tmp, i2c->regs + S3C2410_IICCON); 560 out: 561 return ret; 562 } 563 564 /* s3c24xx_i2c_irq 565 * 566 * top level IRQ servicing routine 567 */ 568 569 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 570 { 571 struct s3c24xx_i2c *i2c = dev_id; 572 unsigned long status; 573 unsigned long tmp; 574 575 status = readl(i2c->regs + S3C2410_IICSTAT); 576 577 if (status & S3C2410_IICSTAT_ARBITR) { 578 /* deal with arbitration loss */ 579 dev_err(i2c->dev, "deal with arbitration loss\n"); 580 } 581 582 if (i2c->state == STATE_IDLE) { 583 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 584 585 tmp = readl(i2c->regs + S3C2410_IICCON); 586 tmp &= ~S3C2410_IICCON_IRQPEND; 587 writel(tmp, i2c->regs + S3C2410_IICCON); 588 goto out; 589 } 590 591 /* pretty much this leaves us with the fact that we've 592 * transmitted or received whatever byte we last sent */ 593 594 i2c_s3c_irq_nextbyte(i2c, status); 595 596 out: 597 return IRQ_HANDLED; 598 } 599 600 /* 601 * Disable the bus so that we won't get any interrupts from now on, or try 602 * to drive any lines. This is the default state when we don't have 603 * anything to send/receive. 604 * 605 * If there is an event on the bus, or we have a pre-existing event at 606 * kernel boot time, we may not notice the event and the I2C controller 607 * will lock the bus with the I2C clock line low indefinitely. 608 */ 609 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c) 610 { 611 unsigned long tmp; 612 613 /* Stop driving the I2C pins */ 614 tmp = readl(i2c->regs + S3C2410_IICSTAT); 615 tmp &= ~S3C2410_IICSTAT_TXRXEN; 616 writel(tmp, i2c->regs + S3C2410_IICSTAT); 617 618 /* We don't expect any interrupts now, and don't want send acks */ 619 tmp = readl(i2c->regs + S3C2410_IICCON); 620 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND | 621 S3C2410_IICCON_ACKEN); 622 writel(tmp, i2c->regs + S3C2410_IICCON); 623 } 624 625 626 /* s3c24xx_i2c_set_master 627 * 628 * get the i2c bus for a master transaction 629 */ 630 631 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 632 { 633 unsigned long iicstat; 634 int timeout = 400; 635 636 while (timeout-- > 0) { 637 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 638 639 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 640 return 0; 641 642 msleep(1); 643 } 644 645 return -ETIMEDOUT; 646 } 647 648 /* s3c24xx_i2c_wait_idle 649 * 650 * wait for the i2c bus to become idle. 651 */ 652 653 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) 654 { 655 unsigned long iicstat; 656 ktime_t start, now; 657 unsigned long delay; 658 int spins; 659 660 /* ensure the stop has been through the bus */ 661 662 dev_dbg(i2c->dev, "waiting for bus idle\n"); 663 664 start = now = ktime_get(); 665 666 /* 667 * Most of the time, the bus is already idle within a few usec of the 668 * end of a transaction. However, really slow i2c devices can stretch 669 * the clock, delaying STOP generation. 670 * 671 * On slower SoCs this typically happens within a very small number of 672 * instructions so busy wait briefly to avoid scheduling overhead. 673 */ 674 spins = 3; 675 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 676 while ((iicstat & S3C2410_IICSTAT_START) && --spins) { 677 cpu_relax(); 678 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 679 } 680 681 /* 682 * If we do get an appreciable delay as a compromise between idle 683 * detection latency for the normal, fast case, and system load in the 684 * slow device case, use an exponential back off in the polling loop, 685 * up to 1/10th of the total timeout, then continue to poll at a 686 * constant rate up to the timeout. 687 */ 688 delay = 1; 689 while ((iicstat & S3C2410_IICSTAT_START) && 690 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { 691 usleep_range(delay, 2 * delay); 692 if (delay < S3C2410_IDLE_TIMEOUT / 10) 693 delay <<= 1; 694 now = ktime_get(); 695 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 696 } 697 698 if (iicstat & S3C2410_IICSTAT_START) 699 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 700 } 701 702 /* s3c24xx_i2c_doxfer 703 * 704 * this starts an i2c transfer 705 */ 706 707 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 708 struct i2c_msg *msgs, int num) 709 { 710 unsigned long timeout; 711 int ret; 712 713 if (i2c->suspended) 714 return -EIO; 715 716 ret = s3c24xx_i2c_set_master(i2c); 717 if (ret != 0) { 718 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 719 ret = -EAGAIN; 720 goto out; 721 } 722 723 i2c->msg = msgs; 724 i2c->msg_num = num; 725 i2c->msg_ptr = 0; 726 i2c->msg_idx = 0; 727 i2c->state = STATE_START; 728 729 s3c24xx_i2c_enable_irq(i2c); 730 s3c24xx_i2c_message_start(i2c, msgs); 731 732 if (i2c->quirks & QUIRK_POLL) { 733 ret = i2c->msg_idx; 734 735 if (ret != num) 736 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 737 738 goto out; 739 } 740 741 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 742 743 ret = i2c->msg_idx; 744 745 /* having these next two as dev_err() makes life very 746 * noisy when doing an i2cdetect */ 747 748 if (timeout == 0) 749 dev_dbg(i2c->dev, "timeout\n"); 750 else if (ret != num) 751 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 752 753 /* For QUIRK_HDMIPHY, bus is already disabled */ 754 if (i2c->quirks & QUIRK_HDMIPHY) 755 goto out; 756 757 s3c24xx_i2c_wait_idle(i2c); 758 759 s3c24xx_i2c_disable_bus(i2c); 760 761 out: 762 i2c->state = STATE_IDLE; 763 764 return ret; 765 } 766 767 /* s3c24xx_i2c_xfer 768 * 769 * first port of call from the i2c bus code when an message needs 770 * transferring across the i2c bus. 771 */ 772 773 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 774 struct i2c_msg *msgs, int num) 775 { 776 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 777 int retry; 778 int ret; 779 780 pm_runtime_get_sync(&adap->dev); 781 clk_prepare_enable(i2c->clk); 782 783 for (retry = 0; retry < adap->retries; retry++) { 784 785 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 786 787 if (ret != -EAGAIN) { 788 clk_disable_unprepare(i2c->clk); 789 pm_runtime_put(&adap->dev); 790 return ret; 791 } 792 793 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 794 795 udelay(100); 796 } 797 798 clk_disable_unprepare(i2c->clk); 799 pm_runtime_put(&adap->dev); 800 return -EREMOTEIO; 801 } 802 803 /* declare our i2c functionality */ 804 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 805 { 806 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | 807 I2C_FUNC_PROTOCOL_MANGLING; 808 } 809 810 /* i2c bus registration info */ 811 812 static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 813 .master_xfer = s3c24xx_i2c_xfer, 814 .functionality = s3c24xx_i2c_func, 815 }; 816 817 /* s3c24xx_i2c_calcdivisor 818 * 819 * return the divisor settings for a given frequency 820 */ 821 822 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 823 unsigned int *div1, unsigned int *divs) 824 { 825 unsigned int calc_divs = clkin / wanted; 826 unsigned int calc_div1; 827 828 if (calc_divs > (16*16)) 829 calc_div1 = 512; 830 else 831 calc_div1 = 16; 832 833 calc_divs += calc_div1-1; 834 calc_divs /= calc_div1; 835 836 if (calc_divs == 0) 837 calc_divs = 1; 838 if (calc_divs > 17) 839 calc_divs = 17; 840 841 *divs = calc_divs; 842 *div1 = calc_div1; 843 844 return clkin / (calc_divs * calc_div1); 845 } 846 847 /* s3c24xx_i2c_clockrate 848 * 849 * work out a divisor for the user requested frequency setting, 850 * either by the requested frequency, or scanning the acceptable 851 * range of frequencies until something is found 852 */ 853 854 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 855 { 856 struct s3c2410_platform_i2c *pdata = i2c->pdata; 857 unsigned long clkin = clk_get_rate(i2c->clk); 858 unsigned int divs, div1; 859 unsigned long target_frequency; 860 u32 iiccon; 861 int freq; 862 863 i2c->clkrate = clkin; 864 clkin /= 1000; /* clkin now in KHz */ 865 866 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 867 868 target_frequency = pdata->frequency ? pdata->frequency : 100000; 869 870 target_frequency /= 1000; /* Target frequency now in KHz */ 871 872 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 873 874 if (freq > target_frequency) { 875 dev_err(i2c->dev, 876 "Unable to achieve desired frequency %luKHz." \ 877 " Lowest achievable %dKHz\n", target_frequency, freq); 878 return -EINVAL; 879 } 880 881 *got = freq; 882 883 iiccon = readl(i2c->regs + S3C2410_IICCON); 884 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 885 iiccon |= (divs-1); 886 887 if (div1 == 512) 888 iiccon |= S3C2410_IICCON_TXDIV_512; 889 890 if (i2c->quirks & QUIRK_POLL) 891 iiccon |= S3C2410_IICCON_SCALE(2); 892 893 writel(iiccon, i2c->regs + S3C2410_IICCON); 894 895 if (i2c->quirks & QUIRK_S3C2440) { 896 unsigned long sda_delay; 897 898 if (pdata->sda_delay) { 899 sda_delay = clkin * pdata->sda_delay; 900 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 901 sda_delay = DIV_ROUND_UP(sda_delay, 5); 902 if (sda_delay > 3) 903 sda_delay = 3; 904 sda_delay |= S3C2410_IICLC_FILTER_ON; 905 } else 906 sda_delay = 0; 907 908 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 909 writel(sda_delay, i2c->regs + S3C2440_IICLC); 910 } 911 912 return 0; 913 } 914 915 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ) 916 917 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) 918 919 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, 920 unsigned long val, void *data) 921 { 922 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 923 unsigned int got; 924 int delta_f; 925 int ret; 926 927 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; 928 929 /* if we're post-change and the input clock has slowed down 930 * or at pre-change and the clock is about to speed up, then 931 * adjust our clock rate. <0 is slow, >0 speedup. 932 */ 933 934 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 935 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 936 i2c_lock_adapter(&i2c->adap); 937 ret = s3c24xx_i2c_clockrate(i2c, &got); 938 i2c_unlock_adapter(&i2c->adap); 939 940 if (ret < 0) 941 dev_err(i2c->dev, "cannot find frequency\n"); 942 else 943 dev_info(i2c->dev, "setting freq %d\n", got); 944 } 945 946 return 0; 947 } 948 949 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 950 { 951 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; 952 953 return cpufreq_register_notifier(&i2c->freq_transition, 954 CPUFREQ_TRANSITION_NOTIFIER); 955 } 956 957 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 958 { 959 cpufreq_unregister_notifier(&i2c->freq_transition, 960 CPUFREQ_TRANSITION_NOTIFIER); 961 } 962 963 #else 964 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 965 { 966 return 0; 967 } 968 969 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 970 { 971 } 972 #endif 973 974 #ifdef CONFIG_OF 975 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 976 { 977 int idx, gpio, ret; 978 979 if (i2c->quirks & QUIRK_NO_GPIO) 980 return 0; 981 982 for (idx = 0; idx < 2; idx++) { 983 gpio = of_get_gpio(i2c->dev->of_node, idx); 984 if (!gpio_is_valid(gpio)) { 985 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); 986 goto free_gpio; 987 } 988 i2c->gpios[idx] = gpio; 989 990 ret = gpio_request(gpio, "i2c-bus"); 991 if (ret) { 992 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); 993 goto free_gpio; 994 } 995 } 996 return 0; 997 998 free_gpio: 999 while (--idx >= 0) 1000 gpio_free(i2c->gpios[idx]); 1001 return -EINVAL; 1002 } 1003 1004 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 1005 { 1006 unsigned int idx; 1007 1008 if (i2c->quirks & QUIRK_NO_GPIO) 1009 return; 1010 1011 for (idx = 0; idx < 2; idx++) 1012 gpio_free(i2c->gpios[idx]); 1013 } 1014 #else 1015 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 1016 { 1017 return 0; 1018 } 1019 1020 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 1021 { 1022 } 1023 #endif 1024 1025 /* s3c24xx_i2c_init 1026 * 1027 * initialise the controller, set the IO lines and frequency 1028 */ 1029 1030 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 1031 { 1032 struct s3c2410_platform_i2c *pdata; 1033 unsigned int freq; 1034 1035 /* get the plafrom data */ 1036 1037 pdata = i2c->pdata; 1038 1039 /* write slave address */ 1040 1041 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 1042 1043 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 1044 1045 writel(0, i2c->regs + S3C2410_IICCON); 1046 writel(0, i2c->regs + S3C2410_IICSTAT); 1047 1048 /* we need to work out the divisors for the clock... */ 1049 1050 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 1051 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 1052 return -EINVAL; 1053 } 1054 1055 /* todo - check that the i2c lines aren't being dragged anywhere */ 1056 1057 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 1058 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n", 1059 readl(i2c->regs + S3C2410_IICCON)); 1060 1061 return 0; 1062 } 1063 1064 #ifdef CONFIG_OF 1065 /* s3c24xx_i2c_parse_dt 1066 * 1067 * Parse the device tree node and retreive the platform data. 1068 */ 1069 1070 static void 1071 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 1072 { 1073 struct s3c2410_platform_i2c *pdata = i2c->pdata; 1074 1075 if (!np) 1076 return; 1077 1078 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ 1079 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); 1080 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 1081 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 1082 (u32 *)&pdata->frequency); 1083 } 1084 #else 1085 static void 1086 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 1087 { 1088 return; 1089 } 1090 #endif 1091 1092 /* s3c24xx_i2c_probe 1093 * 1094 * called by the bus driver when a suitable device is found 1095 */ 1096 1097 static int s3c24xx_i2c_probe(struct platform_device *pdev) 1098 { 1099 struct s3c24xx_i2c *i2c; 1100 struct s3c2410_platform_i2c *pdata = NULL; 1101 struct resource *res; 1102 int ret; 1103 1104 if (!pdev->dev.of_node) { 1105 pdata = dev_get_platdata(&pdev->dev); 1106 if (!pdata) { 1107 dev_err(&pdev->dev, "no platform data\n"); 1108 return -EINVAL; 1109 } 1110 } 1111 1112 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 1113 if (!i2c) 1114 return -ENOMEM; 1115 1116 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1117 if (!i2c->pdata) 1118 return -ENOMEM; 1119 1120 i2c->quirks = s3c24xx_get_device_quirks(pdev); 1121 if (pdata) 1122 memcpy(i2c->pdata, pdata, sizeof(*pdata)); 1123 else 1124 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); 1125 1126 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 1127 i2c->adap.owner = THIS_MODULE; 1128 i2c->adap.algo = &s3c24xx_i2c_algorithm; 1129 i2c->adap.retries = 2; 1130 i2c->adap.class = I2C_CLASS_DEPRECATED; 1131 i2c->tx_setup = 50; 1132 1133 init_waitqueue_head(&i2c->wait); 1134 1135 /* find the clock and enable it */ 1136 1137 i2c->dev = &pdev->dev; 1138 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1139 if (IS_ERR(i2c->clk)) { 1140 dev_err(&pdev->dev, "cannot get clock\n"); 1141 return -ENOENT; 1142 } 1143 1144 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 1145 1146 1147 /* map the registers */ 1148 1149 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1150 i2c->regs = devm_ioremap_resource(&pdev->dev, res); 1151 1152 if (IS_ERR(i2c->regs)) 1153 return PTR_ERR(i2c->regs); 1154 1155 dev_dbg(&pdev->dev, "registers %p (%p)\n", 1156 i2c->regs, res); 1157 1158 /* setup info block for the i2c core */ 1159 1160 i2c->adap.algo_data = i2c; 1161 i2c->adap.dev.parent = &pdev->dev; 1162 1163 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); 1164 1165 /* inititalise the i2c gpio lines */ 1166 1167 if (i2c->pdata->cfg_gpio) { 1168 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); 1169 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) { 1170 return -EINVAL; 1171 } 1172 1173 /* initialise the i2c controller */ 1174 1175 clk_prepare_enable(i2c->clk); 1176 ret = s3c24xx_i2c_init(i2c); 1177 clk_disable_unprepare(i2c->clk); 1178 if (ret != 0) { 1179 dev_err(&pdev->dev, "I2C controller init failed\n"); 1180 return ret; 1181 } 1182 /* find the IRQ for this unit (note, this relies on the init call to 1183 * ensure no current IRQs pending 1184 */ 1185 1186 if (!(i2c->quirks & QUIRK_POLL)) { 1187 i2c->irq = ret = platform_get_irq(pdev, 0); 1188 if (ret <= 0) { 1189 dev_err(&pdev->dev, "cannot find IRQ\n"); 1190 return ret; 1191 } 1192 1193 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, 1194 dev_name(&pdev->dev), i2c); 1195 1196 if (ret != 0) { 1197 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1198 return ret; 1199 } 1200 } 1201 1202 ret = s3c24xx_i2c_register_cpufreq(i2c); 1203 if (ret < 0) { 1204 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 1205 return ret; 1206 } 1207 1208 /* Note, previous versions of the driver used i2c_add_adapter() 1209 * to add the bus at any number. We now pass the bus number via 1210 * the platform data, so if unset it will now default to always 1211 * being bus 0. 1212 */ 1213 1214 i2c->adap.nr = i2c->pdata->bus_num; 1215 i2c->adap.dev.of_node = pdev->dev.of_node; 1216 1217 ret = i2c_add_numbered_adapter(&i2c->adap); 1218 if (ret < 0) { 1219 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 1220 s3c24xx_i2c_deregister_cpufreq(i2c); 1221 return ret; 1222 } 1223 1224 platform_set_drvdata(pdev, i2c); 1225 1226 pm_runtime_enable(&pdev->dev); 1227 pm_runtime_enable(&i2c->adap.dev); 1228 1229 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1230 return 0; 1231 } 1232 1233 /* s3c24xx_i2c_remove 1234 * 1235 * called when device is removed from the bus 1236 */ 1237 1238 static int s3c24xx_i2c_remove(struct platform_device *pdev) 1239 { 1240 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1241 1242 pm_runtime_disable(&i2c->adap.dev); 1243 pm_runtime_disable(&pdev->dev); 1244 1245 s3c24xx_i2c_deregister_cpufreq(i2c); 1246 1247 i2c_del_adapter(&i2c->adap); 1248 1249 if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) 1250 s3c24xx_i2c_dt_gpio_free(i2c); 1251 1252 return 0; 1253 } 1254 1255 #ifdef CONFIG_PM_SLEEP 1256 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1257 { 1258 struct platform_device *pdev = to_platform_device(dev); 1259 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1260 1261 i2c->suspended = 1; 1262 1263 return 0; 1264 } 1265 1266 static int s3c24xx_i2c_resume_noirq(struct device *dev) 1267 { 1268 struct platform_device *pdev = to_platform_device(dev); 1269 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1270 1271 clk_prepare_enable(i2c->clk); 1272 s3c24xx_i2c_init(i2c); 1273 clk_disable_unprepare(i2c->clk); 1274 i2c->suspended = 0; 1275 1276 return 0; 1277 } 1278 #endif 1279 1280 #ifdef CONFIG_PM 1281 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1282 #ifdef CONFIG_PM_SLEEP 1283 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 1284 .resume_noirq = s3c24xx_i2c_resume_noirq, 1285 .freeze_noirq = s3c24xx_i2c_suspend_noirq, 1286 .thaw_noirq = s3c24xx_i2c_resume_noirq, 1287 .poweroff_noirq = s3c24xx_i2c_suspend_noirq, 1288 .restore_noirq = s3c24xx_i2c_resume_noirq, 1289 #endif 1290 }; 1291 1292 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 1293 #else 1294 #define S3C24XX_DEV_PM_OPS NULL 1295 #endif 1296 1297 /* device driver for platform bus bits */ 1298 1299 static struct platform_driver s3c24xx_i2c_driver = { 1300 .probe = s3c24xx_i2c_probe, 1301 .remove = s3c24xx_i2c_remove, 1302 .id_table = s3c24xx_driver_ids, 1303 .driver = { 1304 .owner = THIS_MODULE, 1305 .name = "s3c-i2c", 1306 .pm = S3C24XX_DEV_PM_OPS, 1307 .of_match_table = of_match_ptr(s3c24xx_i2c_match), 1308 }, 1309 }; 1310 1311 static int __init i2c_adap_s3c_init(void) 1312 { 1313 return platform_driver_register(&s3c24xx_i2c_driver); 1314 } 1315 subsys_initcall(i2c_adap_s3c_init); 1316 1317 static void __exit i2c_adap_s3c_exit(void) 1318 { 1319 platform_driver_unregister(&s3c24xx_i2c_driver); 1320 } 1321 module_exit(i2c_adap_s3c_exit); 1322 1323 MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1324 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 1325 MODULE_LICENSE("GPL"); 1326