1 /* linux/drivers/i2c/busses/i2c-s3c2410.c 2 * 3 * Copyright (C) 2004,2005,2009 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 I2C Controller 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 26 #include <linux/i2c.h> 27 #include <linux/init.h> 28 #include <linux/time.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/errno.h> 32 #include <linux/err.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clk.h> 36 #include <linux/cpufreq.h> 37 #include <linux/slab.h> 38 #include <linux/io.h> 39 #include <linux/of_i2c.h> 40 #include <linux/of_gpio.h> 41 #include <linux/pinctrl/consumer.h> 42 43 #include <asm/irq.h> 44 45 #include <plat/regs-iic.h> 46 #include <linux/platform_data/i2c-s3c2410.h> 47 48 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ 49 #define QUIRK_S3C2440 (1 << 0) 50 #define QUIRK_HDMIPHY (1 << 1) 51 #define QUIRK_NO_GPIO (1 << 2) 52 53 /* Max time to wait for bus to become idle after a xfer (in us) */ 54 #define S3C2410_IDLE_TIMEOUT 5000 55 56 /* i2c controller state */ 57 enum s3c24xx_i2c_state { 58 STATE_IDLE, 59 STATE_START, 60 STATE_READ, 61 STATE_WRITE, 62 STATE_STOP 63 }; 64 65 struct s3c24xx_i2c { 66 wait_queue_head_t wait; 67 unsigned int quirks; 68 unsigned int suspended:1; 69 70 struct i2c_msg *msg; 71 unsigned int msg_num; 72 unsigned int msg_idx; 73 unsigned int msg_ptr; 74 75 unsigned int tx_setup; 76 unsigned int irq; 77 78 enum s3c24xx_i2c_state state; 79 unsigned long clkrate; 80 81 void __iomem *regs; 82 struct clk *clk; 83 struct device *dev; 84 struct i2c_adapter adap; 85 86 struct s3c2410_platform_i2c *pdata; 87 int gpios[2]; 88 struct pinctrl *pctrl; 89 #ifdef CONFIG_CPU_FREQ 90 struct notifier_block freq_transition; 91 #endif 92 }; 93 94 static struct platform_device_id s3c24xx_driver_ids[] = { 95 { 96 .name = "s3c2410-i2c", 97 .driver_data = 0, 98 }, { 99 .name = "s3c2440-i2c", 100 .driver_data = QUIRK_S3C2440, 101 }, { 102 .name = "s3c2440-hdmiphy-i2c", 103 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, 104 }, { }, 105 }; 106 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 107 108 #ifdef CONFIG_OF 109 static const struct of_device_id s3c24xx_i2c_match[] = { 110 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, 111 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, 112 { .compatible = "samsung,s3c2440-hdmiphy-i2c", 113 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, 114 {}, 115 }; 116 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); 117 #endif 118 119 /* s3c24xx_get_device_quirks 120 * 121 * Get controller type either from device tree or platform device variant. 122 */ 123 124 static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev) 125 { 126 if (pdev->dev.of_node) { 127 const struct of_device_id *match; 128 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); 129 return (unsigned int)match->data; 130 } 131 132 return platform_get_device_id(pdev)->driver_data; 133 } 134 135 /* s3c24xx_i2c_master_complete 136 * 137 * complete the message and wake up the caller, using the given return code, 138 * or zero to mean ok. 139 */ 140 141 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 142 { 143 dev_dbg(i2c->dev, "master_complete %d\n", ret); 144 145 i2c->msg_ptr = 0; 146 i2c->msg = NULL; 147 i2c->msg_idx++; 148 i2c->msg_num = 0; 149 if (ret) 150 i2c->msg_idx = ret; 151 152 wake_up(&i2c->wait); 153 } 154 155 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 156 { 157 unsigned long tmp; 158 159 tmp = readl(i2c->regs + S3C2410_IICCON); 160 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 161 } 162 163 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 164 { 165 unsigned long tmp; 166 167 tmp = readl(i2c->regs + S3C2410_IICCON); 168 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 169 } 170 171 /* irq enable/disable functions */ 172 173 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 174 { 175 unsigned long tmp; 176 177 tmp = readl(i2c->regs + S3C2410_IICCON); 178 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 179 } 180 181 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 182 { 183 unsigned long tmp; 184 185 tmp = readl(i2c->regs + S3C2410_IICCON); 186 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 187 } 188 189 190 /* s3c24xx_i2c_message_start 191 * 192 * put the start of a message onto the bus 193 */ 194 195 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 196 struct i2c_msg *msg) 197 { 198 unsigned int addr = (msg->addr & 0x7f) << 1; 199 unsigned long stat; 200 unsigned long iiccon; 201 202 stat = 0; 203 stat |= S3C2410_IICSTAT_TXRXEN; 204 205 if (msg->flags & I2C_M_RD) { 206 stat |= S3C2410_IICSTAT_MASTER_RX; 207 addr |= 1; 208 } else 209 stat |= S3C2410_IICSTAT_MASTER_TX; 210 211 if (msg->flags & I2C_M_REV_DIR_ADDR) 212 addr ^= 1; 213 214 /* todo - check for whether ack wanted or not */ 215 s3c24xx_i2c_enable_ack(i2c); 216 217 iiccon = readl(i2c->regs + S3C2410_IICCON); 218 writel(stat, i2c->regs + S3C2410_IICSTAT); 219 220 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 221 writeb(addr, i2c->regs + S3C2410_IICDS); 222 223 /* delay here to ensure the data byte has gotten onto the bus 224 * before the transaction is started */ 225 226 ndelay(i2c->tx_setup); 227 228 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 229 writel(iiccon, i2c->regs + S3C2410_IICCON); 230 231 stat |= S3C2410_IICSTAT_START; 232 writel(stat, i2c->regs + S3C2410_IICSTAT); 233 } 234 235 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 236 { 237 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 238 239 dev_dbg(i2c->dev, "STOP\n"); 240 241 /* 242 * The datasheet says that the STOP sequence should be: 243 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') 244 * 2) I2CCON.4 = 0 - Clear IRQPEND 245 * 3) Wait until the stop condition takes effect. 246 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN 247 * 248 * Where, step "4*" is only for buses with the "HDMIPHY" quirk. 249 * 250 * However, after much experimentation, it appears that: 251 * a) normal buses automatically clear BUSY and transition from 252 * Master->Slave when they complete generating a STOP condition. 253 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 254 * after starting the STOP generation here. 255 * b) HDMIPHY bus does neither, so there is no way to do step 3. 256 * There is no indication when this bus has finished generating 257 * STOP. 258 * 259 * In fact, we have found that as soon as the IRQPEND bit is cleared in 260 * step 2, the HDMIPHY bus generates the STOP condition, and then 261 * immediately starts transferring another data byte, even though the 262 * bus is supposedly stopped. This is presumably because the bus is 263 * still in "Master" mode, and its BUSY bit is still set. 264 * 265 * To avoid these extra post-STOP transactions on HDMI phy devices, we 266 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, 267 * instead of first generating a proper STOP condition. This should 268 * float SDA & SCK terminating the transfer. Subsequent transfers 269 * start with a proper START condition, and proceed normally. 270 * 271 * The HDMIPHY bus is an internal bus that always has exactly two 272 * devices, the host as Master and the HDMIPHY device as the slave. 273 * Skipping the STOP condition has been tested on this bus and works. 274 */ 275 if (i2c->quirks & QUIRK_HDMIPHY) { 276 /* Stop driving the I2C pins */ 277 iicstat &= ~S3C2410_IICSTAT_TXRXEN; 278 } else { 279 /* stop the transfer */ 280 iicstat &= ~S3C2410_IICSTAT_START; 281 } 282 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 283 284 i2c->state = STATE_STOP; 285 286 s3c24xx_i2c_master_complete(i2c, ret); 287 s3c24xx_i2c_disable_irq(i2c); 288 } 289 290 /* helper functions to determine the current state in the set of 291 * messages we are sending */ 292 293 /* is_lastmsg() 294 * 295 * returns TRUE if the current message is the last in the set 296 */ 297 298 static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 299 { 300 return i2c->msg_idx >= (i2c->msg_num - 1); 301 } 302 303 /* is_msglast 304 * 305 * returns TRUE if we this is the last byte in the current message 306 */ 307 308 static inline int is_msglast(struct s3c24xx_i2c *i2c) 309 { 310 return i2c->msg_ptr == i2c->msg->len-1; 311 } 312 313 /* is_msgend 314 * 315 * returns TRUE if we reached the end of the current message 316 */ 317 318 static inline int is_msgend(struct s3c24xx_i2c *i2c) 319 { 320 return i2c->msg_ptr >= i2c->msg->len; 321 } 322 323 /* i2c_s3c_irq_nextbyte 324 * 325 * process an interrupt and work out what to do 326 */ 327 328 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 329 { 330 unsigned long tmp; 331 unsigned char byte; 332 int ret = 0; 333 334 switch (i2c->state) { 335 336 case STATE_IDLE: 337 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 338 goto out; 339 340 case STATE_STOP: 341 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 342 s3c24xx_i2c_disable_irq(i2c); 343 goto out_ack; 344 345 case STATE_START: 346 /* last thing we did was send a start condition on the 347 * bus, or started a new i2c message 348 */ 349 350 if (iicstat & S3C2410_IICSTAT_LASTBIT && 351 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 352 /* ack was not received... */ 353 354 dev_dbg(i2c->dev, "ack was not received\n"); 355 s3c24xx_i2c_stop(i2c, -ENXIO); 356 goto out_ack; 357 } 358 359 if (i2c->msg->flags & I2C_M_RD) 360 i2c->state = STATE_READ; 361 else 362 i2c->state = STATE_WRITE; 363 364 /* terminate the transfer if there is nothing to do 365 * as this is used by the i2c probe to find devices. */ 366 367 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 368 s3c24xx_i2c_stop(i2c, 0); 369 goto out_ack; 370 } 371 372 if (i2c->state == STATE_READ) 373 goto prepare_read; 374 375 /* fall through to the write state, as we will need to 376 * send a byte as well */ 377 378 case STATE_WRITE: 379 /* we are writing data to the device... check for the 380 * end of the message, and if so, work out what to do 381 */ 382 383 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 384 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 385 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 386 387 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 388 goto out_ack; 389 } 390 } 391 392 retry_write: 393 394 if (!is_msgend(i2c)) { 395 byte = i2c->msg->buf[i2c->msg_ptr++]; 396 writeb(byte, i2c->regs + S3C2410_IICDS); 397 398 /* delay after writing the byte to allow the 399 * data setup time on the bus, as writing the 400 * data to the register causes the first bit 401 * to appear on SDA, and SCL will change as 402 * soon as the interrupt is acknowledged */ 403 404 ndelay(i2c->tx_setup); 405 406 } else if (!is_lastmsg(i2c)) { 407 /* we need to go to the next i2c message */ 408 409 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 410 411 i2c->msg_ptr = 0; 412 i2c->msg_idx++; 413 i2c->msg++; 414 415 /* check to see if we need to do another message */ 416 if (i2c->msg->flags & I2C_M_NOSTART) { 417 418 if (i2c->msg->flags & I2C_M_RD) { 419 /* cannot do this, the controller 420 * forces us to send a new START 421 * when we change direction */ 422 423 s3c24xx_i2c_stop(i2c, -EINVAL); 424 } 425 426 goto retry_write; 427 } else { 428 /* send the new start */ 429 s3c24xx_i2c_message_start(i2c, i2c->msg); 430 i2c->state = STATE_START; 431 } 432 433 } else { 434 /* send stop */ 435 436 s3c24xx_i2c_stop(i2c, 0); 437 } 438 break; 439 440 case STATE_READ: 441 /* we have a byte of data in the data register, do 442 * something with it, and then work out whether we are 443 * going to do any more read/write 444 */ 445 446 byte = readb(i2c->regs + S3C2410_IICDS); 447 i2c->msg->buf[i2c->msg_ptr++] = byte; 448 449 prepare_read: 450 if (is_msglast(i2c)) { 451 /* last byte of buffer */ 452 453 if (is_lastmsg(i2c)) 454 s3c24xx_i2c_disable_ack(i2c); 455 456 } else if (is_msgend(i2c)) { 457 /* ok, we've read the entire buffer, see if there 458 * is anything else we need to do */ 459 460 if (is_lastmsg(i2c)) { 461 /* last message, send stop and complete */ 462 dev_dbg(i2c->dev, "READ: Send Stop\n"); 463 464 s3c24xx_i2c_stop(i2c, 0); 465 } else { 466 /* go to the next transfer */ 467 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 468 469 i2c->msg_ptr = 0; 470 i2c->msg_idx++; 471 i2c->msg++; 472 } 473 } 474 475 break; 476 } 477 478 /* acknowlegde the IRQ and get back on with the work */ 479 480 out_ack: 481 tmp = readl(i2c->regs + S3C2410_IICCON); 482 tmp &= ~S3C2410_IICCON_IRQPEND; 483 writel(tmp, i2c->regs + S3C2410_IICCON); 484 out: 485 return ret; 486 } 487 488 /* s3c24xx_i2c_irq 489 * 490 * top level IRQ servicing routine 491 */ 492 493 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 494 { 495 struct s3c24xx_i2c *i2c = dev_id; 496 unsigned long status; 497 unsigned long tmp; 498 499 status = readl(i2c->regs + S3C2410_IICSTAT); 500 501 if (status & S3C2410_IICSTAT_ARBITR) { 502 /* deal with arbitration loss */ 503 dev_err(i2c->dev, "deal with arbitration loss\n"); 504 } 505 506 if (i2c->state == STATE_IDLE) { 507 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 508 509 tmp = readl(i2c->regs + S3C2410_IICCON); 510 tmp &= ~S3C2410_IICCON_IRQPEND; 511 writel(tmp, i2c->regs + S3C2410_IICCON); 512 goto out; 513 } 514 515 /* pretty much this leaves us with the fact that we've 516 * transmitted or received whatever byte we last sent */ 517 518 i2c_s3c_irq_nextbyte(i2c, status); 519 520 out: 521 return IRQ_HANDLED; 522 } 523 524 525 /* s3c24xx_i2c_set_master 526 * 527 * get the i2c bus for a master transaction 528 */ 529 530 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 531 { 532 unsigned long iicstat; 533 int timeout = 400; 534 535 while (timeout-- > 0) { 536 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 537 538 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 539 return 0; 540 541 msleep(1); 542 } 543 544 return -ETIMEDOUT; 545 } 546 547 /* s3c24xx_i2c_wait_idle 548 * 549 * wait for the i2c bus to become idle. 550 */ 551 552 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) 553 { 554 unsigned long iicstat; 555 ktime_t start, now; 556 unsigned long delay; 557 int spins; 558 559 /* ensure the stop has been through the bus */ 560 561 dev_dbg(i2c->dev, "waiting for bus idle\n"); 562 563 start = now = ktime_get(); 564 565 /* 566 * Most of the time, the bus is already idle within a few usec of the 567 * end of a transaction. However, really slow i2c devices can stretch 568 * the clock, delaying STOP generation. 569 * 570 * On slower SoCs this typically happens within a very small number of 571 * instructions so busy wait briefly to avoid scheduling overhead. 572 */ 573 spins = 3; 574 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 575 while ((iicstat & S3C2410_IICSTAT_START) && --spins) { 576 cpu_relax(); 577 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 578 } 579 580 /* 581 * If we do get an appreciable delay as a compromise between idle 582 * detection latency for the normal, fast case, and system load in the 583 * slow device case, use an exponential back off in the polling loop, 584 * up to 1/10th of the total timeout, then continue to poll at a 585 * constant rate up to the timeout. 586 */ 587 delay = 1; 588 while ((iicstat & S3C2410_IICSTAT_START) && 589 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { 590 usleep_range(delay, 2 * delay); 591 if (delay < S3C2410_IDLE_TIMEOUT / 10) 592 delay <<= 1; 593 now = ktime_get(); 594 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 595 } 596 597 if (iicstat & S3C2410_IICSTAT_START) 598 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 599 } 600 601 /* s3c24xx_i2c_doxfer 602 * 603 * this starts an i2c transfer 604 */ 605 606 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 607 struct i2c_msg *msgs, int num) 608 { 609 unsigned long timeout; 610 int ret; 611 612 if (i2c->suspended) 613 return -EIO; 614 615 ret = s3c24xx_i2c_set_master(i2c); 616 if (ret != 0) { 617 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 618 ret = -EAGAIN; 619 goto out; 620 } 621 622 i2c->msg = msgs; 623 i2c->msg_num = num; 624 i2c->msg_ptr = 0; 625 i2c->msg_idx = 0; 626 i2c->state = STATE_START; 627 628 s3c24xx_i2c_enable_irq(i2c); 629 s3c24xx_i2c_message_start(i2c, msgs); 630 631 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 632 633 ret = i2c->msg_idx; 634 635 /* having these next two as dev_err() makes life very 636 * noisy when doing an i2cdetect */ 637 638 if (timeout == 0) 639 dev_dbg(i2c->dev, "timeout\n"); 640 else if (ret != num) 641 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 642 643 /* For QUIRK_HDMIPHY, bus is already disabled */ 644 if (i2c->quirks & QUIRK_HDMIPHY) 645 goto out; 646 647 s3c24xx_i2c_wait_idle(i2c); 648 649 out: 650 return ret; 651 } 652 653 /* s3c24xx_i2c_xfer 654 * 655 * first port of call from the i2c bus code when an message needs 656 * transferring across the i2c bus. 657 */ 658 659 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 660 struct i2c_msg *msgs, int num) 661 { 662 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 663 int retry; 664 int ret; 665 666 pm_runtime_get_sync(&adap->dev); 667 clk_prepare_enable(i2c->clk); 668 669 for (retry = 0; retry < adap->retries; retry++) { 670 671 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 672 673 if (ret != -EAGAIN) { 674 clk_disable_unprepare(i2c->clk); 675 pm_runtime_put(&adap->dev); 676 return ret; 677 } 678 679 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 680 681 udelay(100); 682 } 683 684 clk_disable_unprepare(i2c->clk); 685 pm_runtime_put(&adap->dev); 686 return -EREMOTEIO; 687 } 688 689 /* declare our i2c functionality */ 690 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 691 { 692 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | 693 I2C_FUNC_PROTOCOL_MANGLING; 694 } 695 696 /* i2c bus registration info */ 697 698 static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 699 .master_xfer = s3c24xx_i2c_xfer, 700 .functionality = s3c24xx_i2c_func, 701 }; 702 703 /* s3c24xx_i2c_calcdivisor 704 * 705 * return the divisor settings for a given frequency 706 */ 707 708 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 709 unsigned int *div1, unsigned int *divs) 710 { 711 unsigned int calc_divs = clkin / wanted; 712 unsigned int calc_div1; 713 714 if (calc_divs > (16*16)) 715 calc_div1 = 512; 716 else 717 calc_div1 = 16; 718 719 calc_divs += calc_div1-1; 720 calc_divs /= calc_div1; 721 722 if (calc_divs == 0) 723 calc_divs = 1; 724 if (calc_divs > 17) 725 calc_divs = 17; 726 727 *divs = calc_divs; 728 *div1 = calc_div1; 729 730 return clkin / (calc_divs * calc_div1); 731 } 732 733 /* s3c24xx_i2c_clockrate 734 * 735 * work out a divisor for the user requested frequency setting, 736 * either by the requested frequency, or scanning the acceptable 737 * range of frequencies until something is found 738 */ 739 740 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 741 { 742 struct s3c2410_platform_i2c *pdata = i2c->pdata; 743 unsigned long clkin = clk_get_rate(i2c->clk); 744 unsigned int divs, div1; 745 unsigned long target_frequency; 746 u32 iiccon; 747 int freq; 748 749 i2c->clkrate = clkin; 750 clkin /= 1000; /* clkin now in KHz */ 751 752 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 753 754 target_frequency = pdata->frequency ? pdata->frequency : 100000; 755 756 target_frequency /= 1000; /* Target frequency now in KHz */ 757 758 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 759 760 if (freq > target_frequency) { 761 dev_err(i2c->dev, 762 "Unable to achieve desired frequency %luKHz." \ 763 " Lowest achievable %dKHz\n", target_frequency, freq); 764 return -EINVAL; 765 } 766 767 *got = freq; 768 769 iiccon = readl(i2c->regs + S3C2410_IICCON); 770 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 771 iiccon |= (divs-1); 772 773 if (div1 == 512) 774 iiccon |= S3C2410_IICCON_TXDIV_512; 775 776 writel(iiccon, i2c->regs + S3C2410_IICCON); 777 778 if (i2c->quirks & QUIRK_S3C2440) { 779 unsigned long sda_delay; 780 781 if (pdata->sda_delay) { 782 sda_delay = clkin * pdata->sda_delay; 783 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 784 sda_delay = DIV_ROUND_UP(sda_delay, 5); 785 if (sda_delay > 3) 786 sda_delay = 3; 787 sda_delay |= S3C2410_IICLC_FILTER_ON; 788 } else 789 sda_delay = 0; 790 791 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 792 writel(sda_delay, i2c->regs + S3C2440_IICLC); 793 } 794 795 return 0; 796 } 797 798 #ifdef CONFIG_CPU_FREQ 799 800 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) 801 802 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, 803 unsigned long val, void *data) 804 { 805 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 806 unsigned int got; 807 int delta_f; 808 int ret; 809 810 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; 811 812 /* if we're post-change and the input clock has slowed down 813 * or at pre-change and the clock is about to speed up, then 814 * adjust our clock rate. <0 is slow, >0 speedup. 815 */ 816 817 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 818 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 819 i2c_lock_adapter(&i2c->adap); 820 ret = s3c24xx_i2c_clockrate(i2c, &got); 821 i2c_unlock_adapter(&i2c->adap); 822 823 if (ret < 0) 824 dev_err(i2c->dev, "cannot find frequency\n"); 825 else 826 dev_info(i2c->dev, "setting freq %d\n", got); 827 } 828 829 return 0; 830 } 831 832 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 833 { 834 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; 835 836 return cpufreq_register_notifier(&i2c->freq_transition, 837 CPUFREQ_TRANSITION_NOTIFIER); 838 } 839 840 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 841 { 842 cpufreq_unregister_notifier(&i2c->freq_transition, 843 CPUFREQ_TRANSITION_NOTIFIER); 844 } 845 846 #else 847 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 848 { 849 return 0; 850 } 851 852 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 853 { 854 } 855 #endif 856 857 #ifdef CONFIG_OF 858 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 859 { 860 int idx, gpio, ret; 861 862 if (i2c->quirks & QUIRK_NO_GPIO) 863 return 0; 864 865 for (idx = 0; idx < 2; idx++) { 866 gpio = of_get_gpio(i2c->dev->of_node, idx); 867 if (!gpio_is_valid(gpio)) { 868 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); 869 goto free_gpio; 870 } 871 i2c->gpios[idx] = gpio; 872 873 ret = gpio_request(gpio, "i2c-bus"); 874 if (ret) { 875 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); 876 goto free_gpio; 877 } 878 } 879 return 0; 880 881 free_gpio: 882 while (--idx >= 0) 883 gpio_free(i2c->gpios[idx]); 884 return -EINVAL; 885 } 886 887 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 888 { 889 unsigned int idx; 890 891 if (i2c->quirks & QUIRK_NO_GPIO) 892 return; 893 894 for (idx = 0; idx < 2; idx++) 895 gpio_free(i2c->gpios[idx]); 896 } 897 #else 898 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 899 { 900 return 0; 901 } 902 903 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 904 { 905 } 906 #endif 907 908 /* s3c24xx_i2c_init 909 * 910 * initialise the controller, set the IO lines and frequency 911 */ 912 913 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 914 { 915 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; 916 struct s3c2410_platform_i2c *pdata; 917 unsigned int freq; 918 919 /* get the plafrom data */ 920 921 pdata = i2c->pdata; 922 923 /* write slave address */ 924 925 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 926 927 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 928 929 writel(iicon, i2c->regs + S3C2410_IICCON); 930 931 /* we need to work out the divisors for the clock... */ 932 933 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 934 writel(0, i2c->regs + S3C2410_IICCON); 935 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 936 return -EINVAL; 937 } 938 939 /* todo - check that the i2c lines aren't being dragged anywhere */ 940 941 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 942 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); 943 944 return 0; 945 } 946 947 #ifdef CONFIG_OF 948 /* s3c24xx_i2c_parse_dt 949 * 950 * Parse the device tree node and retreive the platform data. 951 */ 952 953 static void 954 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 955 { 956 struct s3c2410_platform_i2c *pdata = i2c->pdata; 957 958 if (!np) 959 return; 960 961 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ 962 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); 963 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 964 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 965 (u32 *)&pdata->frequency); 966 } 967 #else 968 static void 969 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 970 { 971 return; 972 } 973 #endif 974 975 /* s3c24xx_i2c_probe 976 * 977 * called by the bus driver when a suitable device is found 978 */ 979 980 static int s3c24xx_i2c_probe(struct platform_device *pdev) 981 { 982 struct s3c24xx_i2c *i2c; 983 struct s3c2410_platform_i2c *pdata = NULL; 984 struct resource *res; 985 int ret; 986 987 if (!pdev->dev.of_node) { 988 pdata = pdev->dev.platform_data; 989 if (!pdata) { 990 dev_err(&pdev->dev, "no platform data\n"); 991 return -EINVAL; 992 } 993 } 994 995 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 996 if (!i2c) { 997 dev_err(&pdev->dev, "no memory for state\n"); 998 return -ENOMEM; 999 } 1000 1001 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1002 if (!i2c->pdata) { 1003 ret = -ENOMEM; 1004 goto err_noclk; 1005 } 1006 1007 i2c->quirks = s3c24xx_get_device_quirks(pdev); 1008 if (pdata) 1009 memcpy(i2c->pdata, pdata, sizeof(*pdata)); 1010 else 1011 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); 1012 1013 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 1014 i2c->adap.owner = THIS_MODULE; 1015 i2c->adap.algo = &s3c24xx_i2c_algorithm; 1016 i2c->adap.retries = 2; 1017 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1018 i2c->tx_setup = 50; 1019 1020 init_waitqueue_head(&i2c->wait); 1021 1022 /* find the clock and enable it */ 1023 1024 i2c->dev = &pdev->dev; 1025 i2c->clk = clk_get(&pdev->dev, "i2c"); 1026 if (IS_ERR(i2c->clk)) { 1027 dev_err(&pdev->dev, "cannot get clock\n"); 1028 ret = -ENOENT; 1029 goto err_noclk; 1030 } 1031 1032 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 1033 1034 clk_prepare_enable(i2c->clk); 1035 1036 /* map the registers */ 1037 1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1039 if (res == NULL) { 1040 dev_err(&pdev->dev, "cannot find IO resource\n"); 1041 ret = -ENOENT; 1042 goto err_clk; 1043 } 1044 1045 i2c->regs = devm_request_and_ioremap(&pdev->dev, res); 1046 1047 if (i2c->regs == NULL) { 1048 dev_err(&pdev->dev, "cannot map IO\n"); 1049 ret = -ENXIO; 1050 goto err_clk; 1051 } 1052 1053 dev_dbg(&pdev->dev, "registers %p (%p)\n", 1054 i2c->regs, res); 1055 1056 /* setup info block for the i2c core */ 1057 1058 i2c->adap.algo_data = i2c; 1059 i2c->adap.dev.parent = &pdev->dev; 1060 1061 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); 1062 1063 /* inititalise the i2c gpio lines */ 1064 1065 if (i2c->pdata->cfg_gpio) { 1066 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); 1067 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) { 1068 ret = -EINVAL; 1069 goto err_clk; 1070 } 1071 1072 /* initialise the i2c controller */ 1073 1074 ret = s3c24xx_i2c_init(i2c); 1075 if (ret != 0) 1076 goto err_clk; 1077 1078 /* find the IRQ for this unit (note, this relies on the init call to 1079 * ensure no current IRQs pending 1080 */ 1081 1082 i2c->irq = ret = platform_get_irq(pdev, 0); 1083 if (ret <= 0) { 1084 dev_err(&pdev->dev, "cannot find IRQ\n"); 1085 goto err_clk; 1086 } 1087 1088 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0, 1089 dev_name(&pdev->dev), i2c); 1090 1091 if (ret != 0) { 1092 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1093 goto err_clk; 1094 } 1095 1096 ret = s3c24xx_i2c_register_cpufreq(i2c); 1097 if (ret < 0) { 1098 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 1099 goto err_irq; 1100 } 1101 1102 /* Note, previous versions of the driver used i2c_add_adapter() 1103 * to add the bus at any number. We now pass the bus number via 1104 * the platform data, so if unset it will now default to always 1105 * being bus 0. 1106 */ 1107 1108 i2c->adap.nr = i2c->pdata->bus_num; 1109 i2c->adap.dev.of_node = pdev->dev.of_node; 1110 1111 ret = i2c_add_numbered_adapter(&i2c->adap); 1112 if (ret < 0) { 1113 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 1114 goto err_cpufreq; 1115 } 1116 1117 of_i2c_register_devices(&i2c->adap); 1118 platform_set_drvdata(pdev, i2c); 1119 1120 pm_runtime_enable(&pdev->dev); 1121 pm_runtime_enable(&i2c->adap.dev); 1122 1123 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1124 clk_disable_unprepare(i2c->clk); 1125 return 0; 1126 1127 err_cpufreq: 1128 s3c24xx_i2c_deregister_cpufreq(i2c); 1129 1130 err_irq: 1131 free_irq(i2c->irq, i2c); 1132 1133 err_clk: 1134 clk_disable_unprepare(i2c->clk); 1135 clk_put(i2c->clk); 1136 1137 err_noclk: 1138 return ret; 1139 } 1140 1141 /* s3c24xx_i2c_remove 1142 * 1143 * called when device is removed from the bus 1144 */ 1145 1146 static int s3c24xx_i2c_remove(struct platform_device *pdev) 1147 { 1148 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1149 1150 pm_runtime_disable(&i2c->adap.dev); 1151 pm_runtime_disable(&pdev->dev); 1152 1153 s3c24xx_i2c_deregister_cpufreq(i2c); 1154 1155 i2c_del_adapter(&i2c->adap); 1156 free_irq(i2c->irq, i2c); 1157 1158 clk_disable_unprepare(i2c->clk); 1159 clk_put(i2c->clk); 1160 1161 if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) 1162 s3c24xx_i2c_dt_gpio_free(i2c); 1163 1164 return 0; 1165 } 1166 1167 #ifdef CONFIG_PM_SLEEP 1168 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1169 { 1170 struct platform_device *pdev = to_platform_device(dev); 1171 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1172 1173 i2c->suspended = 1; 1174 1175 return 0; 1176 } 1177 1178 static int s3c24xx_i2c_resume(struct device *dev) 1179 { 1180 struct platform_device *pdev = to_platform_device(dev); 1181 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1182 1183 i2c->suspended = 0; 1184 clk_prepare_enable(i2c->clk); 1185 s3c24xx_i2c_init(i2c); 1186 clk_disable_unprepare(i2c->clk); 1187 1188 return 0; 1189 } 1190 #endif 1191 1192 #ifdef CONFIG_PM 1193 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1194 #ifdef CONFIG_PM_SLEEP 1195 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 1196 .resume = s3c24xx_i2c_resume, 1197 #endif 1198 }; 1199 1200 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 1201 #else 1202 #define S3C24XX_DEV_PM_OPS NULL 1203 #endif 1204 1205 /* device driver for platform bus bits */ 1206 1207 static struct platform_driver s3c24xx_i2c_driver = { 1208 .probe = s3c24xx_i2c_probe, 1209 .remove = s3c24xx_i2c_remove, 1210 .id_table = s3c24xx_driver_ids, 1211 .driver = { 1212 .owner = THIS_MODULE, 1213 .name = "s3c-i2c", 1214 .pm = S3C24XX_DEV_PM_OPS, 1215 .of_match_table = of_match_ptr(s3c24xx_i2c_match), 1216 }, 1217 }; 1218 1219 static int __init i2c_adap_s3c_init(void) 1220 { 1221 return platform_driver_register(&s3c24xx_i2c_driver); 1222 } 1223 subsys_initcall(i2c_adap_s3c_init); 1224 1225 static void __exit i2c_adap_s3c_exit(void) 1226 { 1227 platform_driver_unregister(&s3c24xx_i2c_driver); 1228 } 1229 module_exit(i2c_adap_s3c_exit); 1230 1231 MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1232 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 1233 MODULE_LICENSE("GPL"); 1234