1 /* 2 * Driver for I2C adapter in Rockchip RK3xxx SoC 3 * 4 * Max Schwarz <max.schwarz@online.de> 5 * based on the patches by Rockchip Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/platform_device.h> 19 #include <linux/io.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/spinlock.h> 23 #include <linux/clk.h> 24 #include <linux/wait.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/regmap.h> 27 #include <linux/math64.h> 28 29 30 /* Register Map */ 31 #define REG_CON 0x00 /* control register */ 32 #define REG_CLKDIV 0x04 /* clock divisor register */ 33 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */ 34 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */ 35 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */ 36 #define REG_MRXCNT 0x14 /* number of bytes to be received */ 37 #define REG_IEN 0x18 /* interrupt enable */ 38 #define REG_IPD 0x1c /* interrupt pending */ 39 #define REG_FCNT 0x20 /* finished count */ 40 41 /* Data buffer offsets */ 42 #define TXBUFFER_BASE 0x100 43 #define RXBUFFER_BASE 0x200 44 45 /* REG_CON bits */ 46 #define REG_CON_EN BIT(0) 47 enum { 48 REG_CON_MOD_TX = 0, /* transmit data */ 49 REG_CON_MOD_REGISTER_TX, /* select register and restart */ 50 REG_CON_MOD_RX, /* receive data */ 51 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes 52 * register addr */ 53 }; 54 #define REG_CON_MOD(mod) ((mod) << 1) 55 #define REG_CON_MOD_MASK (BIT(1) | BIT(2)) 56 #define REG_CON_START BIT(3) 57 #define REG_CON_STOP BIT(4) 58 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */ 59 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */ 60 61 /* REG_MRXADDR bits */ 62 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */ 63 64 /* REG_IEN/REG_IPD bits */ 65 #define REG_INT_BTF BIT(0) /* a byte was transmitted */ 66 #define REG_INT_BRF BIT(1) /* a byte was received */ 67 #define REG_INT_MBTF BIT(2) /* master data transmit finished */ 68 #define REG_INT_MBRF BIT(3) /* master data receive finished */ 69 #define REG_INT_START BIT(4) /* START condition generated */ 70 #define REG_INT_STOP BIT(5) /* STOP condition generated */ 71 #define REG_INT_NAKRCV BIT(6) /* NACK received */ 72 #define REG_INT_ALL 0x7f 73 74 /* Constants */ 75 #define WAIT_TIMEOUT 200 /* ms */ 76 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ 77 78 enum rk3x_i2c_state { 79 STATE_IDLE, 80 STATE_START, 81 STATE_READ, 82 STATE_WRITE, 83 STATE_STOP 84 }; 85 86 /** 87 * @grf_offset: offset inside the grf regmap for setting the i2c type 88 */ 89 struct rk3x_i2c_soc_data { 90 int grf_offset; 91 }; 92 93 struct rk3x_i2c { 94 struct i2c_adapter adap; 95 struct device *dev; 96 struct rk3x_i2c_soc_data *soc_data; 97 98 /* Hardware resources */ 99 void __iomem *regs; 100 struct clk *clk; 101 struct notifier_block clk_rate_nb; 102 103 /* Settings */ 104 unsigned int scl_frequency; 105 106 /* Synchronization & notification */ 107 spinlock_t lock; 108 wait_queue_head_t wait; 109 bool busy; 110 111 /* Current message */ 112 struct i2c_msg *msg; 113 u8 addr; 114 unsigned int mode; 115 bool is_last_msg; 116 117 /* I2C state machine */ 118 enum rk3x_i2c_state state; 119 unsigned int processed; /* sent/received bytes */ 120 int error; 121 }; 122 123 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value, 124 unsigned int offset) 125 { 126 writel(value, i2c->regs + offset); 127 } 128 129 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset) 130 { 131 return readl(i2c->regs + offset); 132 } 133 134 /* Reset all interrupt pending bits */ 135 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c) 136 { 137 i2c_writel(i2c, REG_INT_ALL, REG_IPD); 138 } 139 140 /** 141 * Generate a START condition, which triggers a REG_INT_START interrupt. 142 */ 143 static void rk3x_i2c_start(struct rk3x_i2c *i2c) 144 { 145 u32 val; 146 147 rk3x_i2c_clean_ipd(i2c); 148 i2c_writel(i2c, REG_INT_START, REG_IEN); 149 150 /* enable adapter with correct mode, send START condition */ 151 val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START; 152 153 /* if we want to react to NACK, set ACTACK bit */ 154 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 155 val |= REG_CON_ACTACK; 156 157 i2c_writel(i2c, val, REG_CON); 158 } 159 160 /** 161 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt. 162 * 163 * @error: Error code to return in rk3x_i2c_xfer 164 */ 165 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error) 166 { 167 unsigned int ctrl; 168 169 i2c->processed = 0; 170 i2c->msg = NULL; 171 i2c->error = error; 172 173 if (i2c->is_last_msg) { 174 /* Enable stop interrupt */ 175 i2c_writel(i2c, REG_INT_STOP, REG_IEN); 176 177 i2c->state = STATE_STOP; 178 179 ctrl = i2c_readl(i2c, REG_CON); 180 ctrl |= REG_CON_STOP; 181 i2c_writel(i2c, ctrl, REG_CON); 182 } else { 183 /* Signal rk3x_i2c_xfer to start the next message. */ 184 i2c->busy = false; 185 i2c->state = STATE_IDLE; 186 187 /* 188 * The HW is actually not capable of REPEATED START. But we can 189 * get the intended effect by resetting its internal state 190 * and issuing an ordinary START. 191 */ 192 i2c_writel(i2c, 0, REG_CON); 193 194 /* signal that we are finished with the current msg */ 195 wake_up(&i2c->wait); 196 } 197 } 198 199 /** 200 * Setup a read according to i2c->msg 201 */ 202 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c) 203 { 204 unsigned int len = i2c->msg->len - i2c->processed; 205 u32 con; 206 207 con = i2c_readl(i2c, REG_CON); 208 209 /* 210 * The hw can read up to 32 bytes at a time. If we need more than one 211 * chunk, send an ACK after the last byte of the current chunk. 212 */ 213 if (len > 32) { 214 len = 32; 215 con &= ~REG_CON_LASTACK; 216 } else { 217 con |= REG_CON_LASTACK; 218 } 219 220 /* make sure we are in plain RX mode if we read a second chunk */ 221 if (i2c->processed != 0) { 222 con &= ~REG_CON_MOD_MASK; 223 con |= REG_CON_MOD(REG_CON_MOD_RX); 224 } 225 226 i2c_writel(i2c, con, REG_CON); 227 i2c_writel(i2c, len, REG_MRXCNT); 228 } 229 230 /** 231 * Fill the transmit buffer with data from i2c->msg 232 */ 233 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c) 234 { 235 unsigned int i, j; 236 u32 cnt = 0; 237 u32 val; 238 u8 byte; 239 240 for (i = 0; i < 8; ++i) { 241 val = 0; 242 for (j = 0; j < 4; ++j) { 243 if ((i2c->processed == i2c->msg->len) && (cnt != 0)) 244 break; 245 246 if (i2c->processed == 0 && cnt == 0) 247 byte = (i2c->addr & 0x7f) << 1; 248 else 249 byte = i2c->msg->buf[i2c->processed++]; 250 251 val |= byte << (j * 8); 252 cnt++; 253 } 254 255 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i); 256 257 if (i2c->processed == i2c->msg->len) 258 break; 259 } 260 261 i2c_writel(i2c, cnt, REG_MTXCNT); 262 } 263 264 265 /* IRQ handlers for individual states */ 266 267 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd) 268 { 269 if (!(ipd & REG_INT_START)) { 270 rk3x_i2c_stop(i2c, -EIO); 271 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd); 272 rk3x_i2c_clean_ipd(i2c); 273 return; 274 } 275 276 /* ack interrupt */ 277 i2c_writel(i2c, REG_INT_START, REG_IPD); 278 279 /* disable start bit */ 280 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON); 281 282 /* enable appropriate interrupts and transition */ 283 if (i2c->mode == REG_CON_MOD_TX) { 284 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN); 285 i2c->state = STATE_WRITE; 286 rk3x_i2c_fill_transmit_buf(i2c); 287 } else { 288 /* in any other case, we are going to be reading. */ 289 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN); 290 i2c->state = STATE_READ; 291 rk3x_i2c_prepare_read(i2c); 292 } 293 } 294 295 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd) 296 { 297 if (!(ipd & REG_INT_MBTF)) { 298 rk3x_i2c_stop(i2c, -EIO); 299 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd); 300 rk3x_i2c_clean_ipd(i2c); 301 return; 302 } 303 304 /* ack interrupt */ 305 i2c_writel(i2c, REG_INT_MBTF, REG_IPD); 306 307 /* are we finished? */ 308 if (i2c->processed == i2c->msg->len) 309 rk3x_i2c_stop(i2c, i2c->error); 310 else 311 rk3x_i2c_fill_transmit_buf(i2c); 312 } 313 314 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) 315 { 316 unsigned int i; 317 unsigned int len = i2c->msg->len - i2c->processed; 318 u32 uninitialized_var(val); 319 u8 byte; 320 321 /* we only care for MBRF here. */ 322 if (!(ipd & REG_INT_MBRF)) 323 return; 324 325 /* ack interrupt */ 326 i2c_writel(i2c, REG_INT_MBRF, REG_IPD); 327 328 /* Can only handle a maximum of 32 bytes at a time */ 329 if (len > 32) 330 len = 32; 331 332 /* read the data from receive buffer */ 333 for (i = 0; i < len; ++i) { 334 if (i % 4 == 0) 335 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4); 336 337 byte = (val >> ((i % 4) * 8)) & 0xff; 338 i2c->msg->buf[i2c->processed++] = byte; 339 } 340 341 /* are we finished? */ 342 if (i2c->processed == i2c->msg->len) 343 rk3x_i2c_stop(i2c, i2c->error); 344 else 345 rk3x_i2c_prepare_read(i2c); 346 } 347 348 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd) 349 { 350 unsigned int con; 351 352 if (!(ipd & REG_INT_STOP)) { 353 rk3x_i2c_stop(i2c, -EIO); 354 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd); 355 rk3x_i2c_clean_ipd(i2c); 356 return; 357 } 358 359 /* ack interrupt */ 360 i2c_writel(i2c, REG_INT_STOP, REG_IPD); 361 362 /* disable STOP bit */ 363 con = i2c_readl(i2c, REG_CON); 364 con &= ~REG_CON_STOP; 365 i2c_writel(i2c, con, REG_CON); 366 367 i2c->busy = false; 368 i2c->state = STATE_IDLE; 369 370 /* signal rk3x_i2c_xfer that we are finished */ 371 wake_up(&i2c->wait); 372 } 373 374 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id) 375 { 376 struct rk3x_i2c *i2c = dev_id; 377 unsigned int ipd; 378 379 spin_lock(&i2c->lock); 380 381 ipd = i2c_readl(i2c, REG_IPD); 382 if (i2c->state == STATE_IDLE) { 383 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd); 384 rk3x_i2c_clean_ipd(i2c); 385 goto out; 386 } 387 388 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd); 389 390 /* Clean interrupt bits we don't care about */ 391 ipd &= ~(REG_INT_BRF | REG_INT_BTF); 392 393 if (ipd & REG_INT_NAKRCV) { 394 /* 395 * We got a NACK in the last operation. Depending on whether 396 * IGNORE_NAK is set, we have to stop the operation and report 397 * an error. 398 */ 399 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD); 400 401 ipd &= ~REG_INT_NAKRCV; 402 403 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 404 rk3x_i2c_stop(i2c, -ENXIO); 405 } 406 407 /* is there anything left to handle? */ 408 if ((ipd & REG_INT_ALL) == 0) 409 goto out; 410 411 switch (i2c->state) { 412 case STATE_START: 413 rk3x_i2c_handle_start(i2c, ipd); 414 break; 415 case STATE_WRITE: 416 rk3x_i2c_handle_write(i2c, ipd); 417 break; 418 case STATE_READ: 419 rk3x_i2c_handle_read(i2c, ipd); 420 break; 421 case STATE_STOP: 422 rk3x_i2c_handle_stop(i2c, ipd); 423 break; 424 case STATE_IDLE: 425 break; 426 } 427 428 out: 429 spin_unlock(&i2c->lock); 430 return IRQ_HANDLED; 431 } 432 433 /** 434 * Calculate divider values for desired SCL frequency 435 * 436 * @clk_rate: I2C input clock rate 437 * @scl_rate: Desired SCL rate 438 * @div_low: Divider output for low 439 * @div_high: Divider output for high 440 * 441 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case 442 * a best-effort divider value is returned in divs. If the target rate is 443 * too high, we silently use the highest possible rate. 444 */ 445 static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate, 446 unsigned long *div_low, unsigned long *div_high) 447 { 448 unsigned long min_low_ns, min_high_ns; 449 unsigned long max_data_hold_ns; 450 unsigned long data_hold_buffer_ns; 451 unsigned long max_low_ns, min_total_ns; 452 453 unsigned long clk_rate_khz, scl_rate_khz; 454 455 unsigned long min_low_div, min_high_div; 456 unsigned long max_low_div; 457 458 unsigned long min_div_for_hold, min_total_div; 459 unsigned long extra_div, extra_low_div, ideal_low_div; 460 461 int ret = 0; 462 463 /* Only support standard-mode and fast-mode */ 464 if (WARN_ON(scl_rate > 400000)) 465 scl_rate = 400000; 466 467 /* prevent scl_rate_khz from becoming 0 */ 468 if (WARN_ON(scl_rate < 1000)) 469 scl_rate = 1000; 470 471 /* 472 * min_low_ns: The minimum number of ns we need to hold low 473 * to meet i2c spec 474 * min_high_ns: The minimum number of ns we need to hold high 475 * to meet i2c spec 476 * max_low_ns: The maximum number of ns we can hold low 477 * to meet i2c spec 478 * 479 * Note: max_low_ns should be (max data hold time * 2 - buffer) 480 * This is because the i2c host on Rockchip holds the data line 481 * for half the low time. 482 */ 483 if (scl_rate <= 100000) { 484 min_low_ns = 4700; 485 min_high_ns = 4000; 486 max_data_hold_ns = 3450; 487 data_hold_buffer_ns = 50; 488 } else { 489 min_low_ns = 1300; 490 min_high_ns = 600; 491 max_data_hold_ns = 900; 492 data_hold_buffer_ns = 50; 493 } 494 max_low_ns = max_data_hold_ns * 2 - data_hold_buffer_ns; 495 min_total_ns = min_low_ns + min_high_ns; 496 497 /* Adjust to avoid overflow */ 498 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); 499 scl_rate_khz = scl_rate / 1000; 500 501 /* 502 * We need the total div to be >= this number 503 * so we don't clock too fast. 504 */ 505 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); 506 507 /* These are the min dividers needed for min hold times. */ 508 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); 509 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); 510 min_div_for_hold = (min_low_div + min_high_div); 511 512 /* 513 * This is the maximum divider so we don't go over the max. 514 * We don't round up here (we round down) since this is a max. 515 */ 516 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000); 517 518 if (min_low_div > max_low_div) { 519 WARN_ONCE(true, 520 "Conflicting, min_low_div %lu, max_low_div %lu\n", 521 min_low_div, max_low_div); 522 max_low_div = min_low_div; 523 } 524 525 if (min_div_for_hold > min_total_div) { 526 /* 527 * Time needed to meet hold requirements is important. 528 * Just use that. 529 */ 530 *div_low = min_low_div; 531 *div_high = min_high_div; 532 } else { 533 /* 534 * We've got to distribute some time among the low and high 535 * so we don't run too fast. 536 */ 537 extra_div = min_total_div - min_div_for_hold; 538 539 /* 540 * We'll try to split things up perfectly evenly, 541 * biasing slightly towards having a higher div 542 * for low (spend more time low). 543 */ 544 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 545 scl_rate_khz * 8 * min_total_ns); 546 547 /* Don't allow it to go over the max */ 548 if (ideal_low_div > max_low_div) 549 ideal_low_div = max_low_div; 550 551 /* 552 * Handle when the ideal low div is going to take up 553 * more than we have. 554 */ 555 if (ideal_low_div > min_low_div + extra_div) 556 ideal_low_div = min_low_div + extra_div; 557 558 /* Give low the "ideal" and give high whatever extra is left */ 559 extra_low_div = ideal_low_div - min_low_div; 560 *div_low = ideal_low_div; 561 *div_high = min_high_div + (extra_div - extra_low_div); 562 } 563 564 /* 565 * Adjust to the fact that the hardware has an implicit "+1". 566 * NOTE: Above calculations always produce div_low > 0 and div_high > 0. 567 */ 568 *div_low = *div_low - 1; 569 *div_high = *div_high - 1; 570 571 /* Maximum divider supported by hw is 0xffff */ 572 if (*div_low > 0xffff) { 573 *div_low = 0xffff; 574 ret = -EINVAL; 575 } 576 577 if (*div_high > 0xffff) { 578 *div_high = 0xffff; 579 ret = -EINVAL; 580 } 581 582 return ret; 583 } 584 585 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate) 586 { 587 unsigned long div_low, div_high; 588 u64 t_low_ns, t_high_ns; 589 int ret; 590 591 ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, &div_low, 592 &div_high); 593 594 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency); 595 596 clk_enable(i2c->clk); 597 i2c_writel(i2c, (div_high << 16) | (div_low & 0xffff), REG_CLKDIV); 598 clk_disable(i2c->clk); 599 600 t_low_ns = div_u64(((u64)div_low + 1) * 8 * 1000000000, clk_rate); 601 t_high_ns = div_u64(((u64)div_high + 1) * 8 * 1000000000, clk_rate); 602 dev_dbg(i2c->dev, 603 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n", 604 clk_rate / 1000, 605 1000000000 / i2c->scl_frequency, 606 t_low_ns, t_high_ns); 607 } 608 609 /** 610 * rk3x_i2c_clk_notifier_cb - Clock rate change callback 611 * @nb: Pointer to notifier block 612 * @event: Notification reason 613 * @data: Pointer to notification data object 614 * 615 * The callback checks whether a valid bus frequency can be generated after the 616 * change. If so, the change is acknowledged, otherwise the change is aborted. 617 * New dividers are written to the HW in the pre- or post change notification 618 * depending on the scaling direction. 619 * 620 * Code adapted from i2c-cadence.c. 621 * 622 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 623 * to acknowedge the change, NOTIFY_DONE if the notification is 624 * considered irrelevant. 625 */ 626 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 627 event, void *data) 628 { 629 struct clk_notifier_data *ndata = data; 630 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb); 631 unsigned long div_low, div_high; 632 633 switch (event) { 634 case PRE_RATE_CHANGE: 635 if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency, 636 &div_low, &div_high) != 0) { 637 return NOTIFY_STOP; 638 } 639 640 /* scale up */ 641 if (ndata->new_rate > ndata->old_rate) 642 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 643 644 return NOTIFY_OK; 645 case POST_RATE_CHANGE: 646 /* scale down */ 647 if (ndata->new_rate < ndata->old_rate) 648 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 649 return NOTIFY_OK; 650 case ABORT_RATE_CHANGE: 651 /* scale up */ 652 if (ndata->new_rate > ndata->old_rate) 653 rk3x_i2c_adapt_div(i2c, ndata->old_rate); 654 return NOTIFY_OK; 655 default: 656 return NOTIFY_DONE; 657 } 658 } 659 660 /** 661 * Setup I2C registers for an I2C operation specified by msgs, num. 662 * 663 * Must be called with i2c->lock held. 664 * 665 * @msgs: I2C msgs to process 666 * @num: Number of msgs 667 * 668 * returns: Number of I2C msgs processed or negative in case of error 669 */ 670 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num) 671 { 672 u32 addr = (msgs[0].addr & 0x7f) << 1; 673 int ret = 0; 674 675 /* 676 * The I2C adapter can issue a small (len < 4) write packet before 677 * reading. This speeds up SMBus-style register reads. 678 * The MRXADDR/MRXRADDR hold the slave address and the slave register 679 * address in this case. 680 */ 681 682 if (num >= 2 && msgs[0].len < 4 && 683 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) { 684 u32 reg_addr = 0; 685 int i; 686 687 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n", 688 addr >> 1); 689 690 /* Fill MRXRADDR with the register address(es) */ 691 for (i = 0; i < msgs[0].len; ++i) { 692 reg_addr |= msgs[0].buf[i] << (i * 8); 693 reg_addr |= REG_MRXADDR_VALID(i); 694 } 695 696 /* msgs[0] is handled by hw. */ 697 i2c->msg = &msgs[1]; 698 699 i2c->mode = REG_CON_MOD_REGISTER_TX; 700 701 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR); 702 i2c_writel(i2c, reg_addr, REG_MRXRADDR); 703 704 ret = 2; 705 } else { 706 /* 707 * We'll have to do it the boring way and process the msgs 708 * one-by-one. 709 */ 710 711 if (msgs[0].flags & I2C_M_RD) { 712 addr |= 1; /* set read bit */ 713 714 /* 715 * We have to transmit the slave addr first. Use 716 * MOD_REGISTER_TX for that purpose. 717 */ 718 i2c->mode = REG_CON_MOD_REGISTER_TX; 719 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), 720 REG_MRXADDR); 721 i2c_writel(i2c, 0, REG_MRXRADDR); 722 } else { 723 i2c->mode = REG_CON_MOD_TX; 724 } 725 726 i2c->msg = &msgs[0]; 727 728 ret = 1; 729 } 730 731 i2c->addr = msgs[0].addr; 732 i2c->busy = true; 733 i2c->state = STATE_START; 734 i2c->processed = 0; 735 i2c->error = 0; 736 737 rk3x_i2c_clean_ipd(i2c); 738 739 return ret; 740 } 741 742 static int rk3x_i2c_xfer(struct i2c_adapter *adap, 743 struct i2c_msg *msgs, int num) 744 { 745 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data; 746 unsigned long timeout, flags; 747 int ret = 0; 748 int i; 749 750 spin_lock_irqsave(&i2c->lock, flags); 751 752 clk_enable(i2c->clk); 753 754 i2c->is_last_msg = false; 755 756 /* 757 * Process msgs. We can handle more than one message at once (see 758 * rk3x_i2c_setup()). 759 */ 760 for (i = 0; i < num; i += ret) { 761 ret = rk3x_i2c_setup(i2c, msgs + i, num - i); 762 763 if (ret < 0) { 764 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n"); 765 break; 766 } 767 768 if (i + ret >= num) 769 i2c->is_last_msg = true; 770 771 spin_unlock_irqrestore(&i2c->lock, flags); 772 773 rk3x_i2c_start(i2c); 774 775 timeout = wait_event_timeout(i2c->wait, !i2c->busy, 776 msecs_to_jiffies(WAIT_TIMEOUT)); 777 778 spin_lock_irqsave(&i2c->lock, flags); 779 780 if (timeout == 0) { 781 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n", 782 i2c_readl(i2c, REG_IPD), i2c->state); 783 784 /* Force a STOP condition without interrupt */ 785 i2c_writel(i2c, 0, REG_IEN); 786 i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON); 787 788 i2c->state = STATE_IDLE; 789 790 ret = -ETIMEDOUT; 791 break; 792 } 793 794 if (i2c->error) { 795 ret = i2c->error; 796 break; 797 } 798 } 799 800 clk_disable(i2c->clk); 801 spin_unlock_irqrestore(&i2c->lock, flags); 802 803 return ret; 804 } 805 806 static u32 rk3x_i2c_func(struct i2c_adapter *adap) 807 { 808 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 809 } 810 811 static const struct i2c_algorithm rk3x_i2c_algorithm = { 812 .master_xfer = rk3x_i2c_xfer, 813 .functionality = rk3x_i2c_func, 814 }; 815 816 static struct rk3x_i2c_soc_data soc_data[3] = { 817 { .grf_offset = 0x154 }, /* rk3066 */ 818 { .grf_offset = 0x0a4 }, /* rk3188 */ 819 { .grf_offset = -1 }, /* no I2C switching needed */ 820 }; 821 822 static const struct of_device_id rk3x_i2c_match[] = { 823 { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] }, 824 { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] }, 825 { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] }, 826 {}, 827 }; 828 829 static int rk3x_i2c_probe(struct platform_device *pdev) 830 { 831 struct device_node *np = pdev->dev.of_node; 832 const struct of_device_id *match; 833 struct rk3x_i2c *i2c; 834 struct resource *mem; 835 int ret = 0; 836 int bus_nr; 837 u32 value; 838 int irq; 839 unsigned long clk_rate; 840 841 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL); 842 if (!i2c) 843 return -ENOMEM; 844 845 match = of_match_node(rk3x_i2c_match, np); 846 i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data; 847 848 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", 849 &i2c->scl_frequency)) { 850 dev_info(&pdev->dev, "using default SCL frequency: %d\n", 851 DEFAULT_SCL_RATE); 852 i2c->scl_frequency = DEFAULT_SCL_RATE; 853 } 854 855 if (i2c->scl_frequency == 0 || i2c->scl_frequency > 400 * 1000) { 856 dev_warn(&pdev->dev, "invalid SCL frequency specified.\n"); 857 dev_warn(&pdev->dev, "using default SCL frequency: %d\n", 858 DEFAULT_SCL_RATE); 859 i2c->scl_frequency = DEFAULT_SCL_RATE; 860 } 861 862 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); 863 i2c->adap.owner = THIS_MODULE; 864 i2c->adap.algo = &rk3x_i2c_algorithm; 865 i2c->adap.retries = 3; 866 i2c->adap.dev.of_node = np; 867 i2c->adap.algo_data = i2c; 868 i2c->adap.dev.parent = &pdev->dev; 869 870 i2c->dev = &pdev->dev; 871 872 spin_lock_init(&i2c->lock); 873 init_waitqueue_head(&i2c->wait); 874 875 i2c->clk = devm_clk_get(&pdev->dev, NULL); 876 if (IS_ERR(i2c->clk)) { 877 dev_err(&pdev->dev, "cannot get clock\n"); 878 return PTR_ERR(i2c->clk); 879 } 880 881 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 882 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 883 if (IS_ERR(i2c->regs)) 884 return PTR_ERR(i2c->regs); 885 886 /* Try to set the I2C adapter number from dt */ 887 bus_nr = of_alias_get_id(np, "i2c"); 888 889 /* 890 * Switch to new interface if the SoC also offers the old one. 891 * The control bit is located in the GRF register space. 892 */ 893 if (i2c->soc_data->grf_offset >= 0) { 894 struct regmap *grf; 895 896 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 897 if (IS_ERR(grf)) { 898 dev_err(&pdev->dev, 899 "rk3x-i2c needs 'rockchip,grf' property\n"); 900 return PTR_ERR(grf); 901 } 902 903 if (bus_nr < 0) { 904 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias"); 905 return -EINVAL; 906 } 907 908 /* 27+i: write mask, 11+i: value */ 909 value = BIT(27 + bus_nr) | BIT(11 + bus_nr); 910 911 ret = regmap_write(grf, i2c->soc_data->grf_offset, value); 912 if (ret != 0) { 913 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret); 914 return ret; 915 } 916 } 917 918 /* IRQ setup */ 919 irq = platform_get_irq(pdev, 0); 920 if (irq < 0) { 921 dev_err(&pdev->dev, "cannot find rk3x IRQ\n"); 922 return irq; 923 } 924 925 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq, 926 0, dev_name(&pdev->dev), i2c); 927 if (ret < 0) { 928 dev_err(&pdev->dev, "cannot request IRQ\n"); 929 return ret; 930 } 931 932 platform_set_drvdata(pdev, i2c); 933 934 ret = clk_prepare(i2c->clk); 935 if (ret < 0) { 936 dev_err(&pdev->dev, "Could not prepare clock\n"); 937 return ret; 938 } 939 940 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb; 941 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb); 942 if (ret != 0) { 943 dev_err(&pdev->dev, "Unable to register clock notifier\n"); 944 goto err_clk; 945 } 946 947 clk_rate = clk_get_rate(i2c->clk); 948 rk3x_i2c_adapt_div(i2c, clk_rate); 949 950 ret = i2c_add_adapter(&i2c->adap); 951 if (ret < 0) { 952 dev_err(&pdev->dev, "Could not register adapter\n"); 953 goto err_clk_notifier; 954 } 955 956 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs); 957 958 return 0; 959 960 err_clk_notifier: 961 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 962 err_clk: 963 clk_unprepare(i2c->clk); 964 return ret; 965 } 966 967 static int rk3x_i2c_remove(struct platform_device *pdev) 968 { 969 struct rk3x_i2c *i2c = platform_get_drvdata(pdev); 970 971 i2c_del_adapter(&i2c->adap); 972 973 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 974 clk_unprepare(i2c->clk); 975 976 return 0; 977 } 978 979 static struct platform_driver rk3x_i2c_driver = { 980 .probe = rk3x_i2c_probe, 981 .remove = rk3x_i2c_remove, 982 .driver = { 983 .name = "rk3x-i2c", 984 .of_match_table = rk3x_i2c_match, 985 }, 986 }; 987 988 module_platform_driver(rk3x_i2c_driver); 989 990 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver"); 991 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>"); 992 MODULE_LICENSE("GPL v2"); 993