1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for I2C adapter in Rockchip RK3xxx SoC 4 * 5 * Max Schwarz <max.schwarz@online.de> 6 * based on the patches by Rockchip Inc. 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/errno.h> 15 #include <linux/err.h> 16 #include <linux/platform_device.h> 17 #include <linux/io.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/spinlock.h> 21 #include <linux/clk.h> 22 #include <linux/wait.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/regmap.h> 25 #include <linux/math64.h> 26 27 28 /* Register Map */ 29 #define REG_CON 0x00 /* control register */ 30 #define REG_CLKDIV 0x04 /* clock divisor register */ 31 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */ 32 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */ 33 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */ 34 #define REG_MRXCNT 0x14 /* number of bytes to be received */ 35 #define REG_IEN 0x18 /* interrupt enable */ 36 #define REG_IPD 0x1c /* interrupt pending */ 37 #define REG_FCNT 0x20 /* finished count */ 38 39 /* Data buffer offsets */ 40 #define TXBUFFER_BASE 0x100 41 #define RXBUFFER_BASE 0x200 42 43 /* REG_CON bits */ 44 #define REG_CON_EN BIT(0) 45 enum { 46 REG_CON_MOD_TX = 0, /* transmit data */ 47 REG_CON_MOD_REGISTER_TX, /* select register and restart */ 48 REG_CON_MOD_RX, /* receive data */ 49 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes 50 * register addr */ 51 }; 52 #define REG_CON_MOD(mod) ((mod) << 1) 53 #define REG_CON_MOD_MASK (BIT(1) | BIT(2)) 54 #define REG_CON_START BIT(3) 55 #define REG_CON_STOP BIT(4) 56 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */ 57 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */ 58 59 #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8) 60 61 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8) 62 #define REG_CON_STA_CFG(cfg) ((cfg) << 12) 63 #define REG_CON_STO_CFG(cfg) ((cfg) << 14) 64 65 /* REG_MRXADDR bits */ 66 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */ 67 68 /* REG_IEN/REG_IPD bits */ 69 #define REG_INT_BTF BIT(0) /* a byte was transmitted */ 70 #define REG_INT_BRF BIT(1) /* a byte was received */ 71 #define REG_INT_MBTF BIT(2) /* master data transmit finished */ 72 #define REG_INT_MBRF BIT(3) /* master data receive finished */ 73 #define REG_INT_START BIT(4) /* START condition generated */ 74 #define REG_INT_STOP BIT(5) /* STOP condition generated */ 75 #define REG_INT_NAKRCV BIT(6) /* NACK received */ 76 #define REG_INT_ALL 0x7f 77 78 /* Constants */ 79 #define WAIT_TIMEOUT 1000 /* ms */ 80 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ 81 82 /** 83 * struct i2c_spec_values - I2C specification values for various modes 84 * @min_hold_start_ns: min hold time (repeated) START condition 85 * @min_low_ns: min LOW period of the SCL clock 86 * @min_high_ns: min HIGH period of the SCL cloc 87 * @min_setup_start_ns: min set-up time for a repeated START conditio 88 * @max_data_hold_ns: max data hold time 89 * @min_data_setup_ns: min data set-up time 90 * @min_setup_stop_ns: min set-up time for STOP condition 91 * @min_hold_buffer_ns: min bus free time between a STOP and 92 * START condition 93 */ 94 struct i2c_spec_values { 95 unsigned long min_hold_start_ns; 96 unsigned long min_low_ns; 97 unsigned long min_high_ns; 98 unsigned long min_setup_start_ns; 99 unsigned long max_data_hold_ns; 100 unsigned long min_data_setup_ns; 101 unsigned long min_setup_stop_ns; 102 unsigned long min_hold_buffer_ns; 103 }; 104 105 static const struct i2c_spec_values standard_mode_spec = { 106 .min_hold_start_ns = 4000, 107 .min_low_ns = 4700, 108 .min_high_ns = 4000, 109 .min_setup_start_ns = 4700, 110 .max_data_hold_ns = 3450, 111 .min_data_setup_ns = 250, 112 .min_setup_stop_ns = 4000, 113 .min_hold_buffer_ns = 4700, 114 }; 115 116 static const struct i2c_spec_values fast_mode_spec = { 117 .min_hold_start_ns = 600, 118 .min_low_ns = 1300, 119 .min_high_ns = 600, 120 .min_setup_start_ns = 600, 121 .max_data_hold_ns = 900, 122 .min_data_setup_ns = 100, 123 .min_setup_stop_ns = 600, 124 .min_hold_buffer_ns = 1300, 125 }; 126 127 static const struct i2c_spec_values fast_mode_plus_spec = { 128 .min_hold_start_ns = 260, 129 .min_low_ns = 500, 130 .min_high_ns = 260, 131 .min_setup_start_ns = 260, 132 .max_data_hold_ns = 400, 133 .min_data_setup_ns = 50, 134 .min_setup_stop_ns = 260, 135 .min_hold_buffer_ns = 500, 136 }; 137 138 /** 139 * struct rk3x_i2c_calced_timings - calculated V1 timings 140 * @div_low: Divider output for low 141 * @div_high: Divider output for high 142 * @tuning: Used to adjust setup/hold data time, 143 * setup/hold start time and setup stop time for 144 * v1's calc_timings, the tuning should all be 0 145 * for old hardware anyone using v0's calc_timings. 146 */ 147 struct rk3x_i2c_calced_timings { 148 unsigned long div_low; 149 unsigned long div_high; 150 unsigned int tuning; 151 }; 152 153 enum rk3x_i2c_state { 154 STATE_IDLE, 155 STATE_START, 156 STATE_READ, 157 STATE_WRITE, 158 STATE_STOP 159 }; 160 161 /** 162 * struct rk3x_i2c_soc_data - SOC-specific data 163 * @grf_offset: offset inside the grf regmap for setting the i2c type 164 * @calc_timings: Callback function for i2c timing information calculated 165 */ 166 struct rk3x_i2c_soc_data { 167 int grf_offset; 168 int (*calc_timings)(unsigned long, struct i2c_timings *, 169 struct rk3x_i2c_calced_timings *); 170 }; 171 172 /** 173 * struct rk3x_i2c - private data of the controller 174 * @adap: corresponding I2C adapter 175 * @dev: device for this controller 176 * @soc_data: related soc data struct 177 * @regs: virtual memory area 178 * @clk: function clk for rk3399 or function & Bus clks for others 179 * @pclk: Bus clk for rk3399 180 * @clk_rate_nb: i2c clk rate change notify 181 * @t: I2C known timing information 182 * @lock: spinlock for the i2c bus 183 * @wait: the waitqueue to wait for i2c transfer 184 * @busy: the condition for the event to wait for 185 * @msg: current i2c message 186 * @addr: addr of i2c slave device 187 * @mode: mode of i2c transfer 188 * @is_last_msg: flag determines whether it is the last msg in this transfer 189 * @state: state of i2c transfer 190 * @processed: byte length which has been send or received 191 * @error: error code for i2c transfer 192 */ 193 struct rk3x_i2c { 194 struct i2c_adapter adap; 195 struct device *dev; 196 const struct rk3x_i2c_soc_data *soc_data; 197 198 /* Hardware resources */ 199 void __iomem *regs; 200 struct clk *clk; 201 struct clk *pclk; 202 struct notifier_block clk_rate_nb; 203 204 /* Settings */ 205 struct i2c_timings t; 206 207 /* Synchronization & notification */ 208 spinlock_t lock; 209 wait_queue_head_t wait; 210 bool busy; 211 212 /* Current message */ 213 struct i2c_msg *msg; 214 u8 addr; 215 unsigned int mode; 216 bool is_last_msg; 217 218 /* I2C state machine */ 219 enum rk3x_i2c_state state; 220 unsigned int processed; 221 int error; 222 }; 223 224 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value, 225 unsigned int offset) 226 { 227 writel(value, i2c->regs + offset); 228 } 229 230 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset) 231 { 232 return readl(i2c->regs + offset); 233 } 234 235 /* Reset all interrupt pending bits */ 236 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c) 237 { 238 i2c_writel(i2c, REG_INT_ALL, REG_IPD); 239 } 240 241 /** 242 * rk3x_i2c_start - Generate a START condition, which triggers a REG_INT_START interrupt. 243 * @i2c: target controller data 244 */ 245 static void rk3x_i2c_start(struct rk3x_i2c *i2c) 246 { 247 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 248 249 i2c_writel(i2c, REG_INT_START, REG_IEN); 250 251 /* enable adapter with correct mode, send START condition */ 252 val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START; 253 254 /* if we want to react to NACK, set ACTACK bit */ 255 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 256 val |= REG_CON_ACTACK; 257 258 i2c_writel(i2c, val, REG_CON); 259 } 260 261 /** 262 * rk3x_i2c_stop - Generate a STOP condition, which triggers a REG_INT_STOP interrupt. 263 * @i2c: target controller data 264 * @error: Error code to return in rk3x_i2c_xfer 265 */ 266 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error) 267 { 268 unsigned int ctrl; 269 270 i2c->processed = 0; 271 i2c->msg = NULL; 272 i2c->error = error; 273 274 if (i2c->is_last_msg) { 275 /* Enable stop interrupt */ 276 i2c_writel(i2c, REG_INT_STOP, REG_IEN); 277 278 i2c->state = STATE_STOP; 279 280 ctrl = i2c_readl(i2c, REG_CON); 281 ctrl |= REG_CON_STOP; 282 i2c_writel(i2c, ctrl, REG_CON); 283 } else { 284 /* Signal rk3x_i2c_xfer to start the next message. */ 285 i2c->busy = false; 286 i2c->state = STATE_IDLE; 287 288 /* 289 * The HW is actually not capable of REPEATED START. But we can 290 * get the intended effect by resetting its internal state 291 * and issuing an ordinary START. 292 */ 293 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 294 i2c_writel(i2c, ctrl, REG_CON); 295 296 /* signal that we are finished with the current msg */ 297 wake_up(&i2c->wait); 298 } 299 } 300 301 /** 302 * rk3x_i2c_prepare_read - Setup a read according to i2c->msg 303 * @i2c: target controller data 304 */ 305 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c) 306 { 307 unsigned int len = i2c->msg->len - i2c->processed; 308 u32 con; 309 310 con = i2c_readl(i2c, REG_CON); 311 312 /* 313 * The hw can read up to 32 bytes at a time. If we need more than one 314 * chunk, send an ACK after the last byte of the current chunk. 315 */ 316 if (len > 32) { 317 len = 32; 318 con &= ~REG_CON_LASTACK; 319 } else { 320 con |= REG_CON_LASTACK; 321 } 322 323 /* make sure we are in plain RX mode if we read a second chunk */ 324 if (i2c->processed != 0) { 325 con &= ~REG_CON_MOD_MASK; 326 con |= REG_CON_MOD(REG_CON_MOD_RX); 327 } 328 329 i2c_writel(i2c, con, REG_CON); 330 i2c_writel(i2c, len, REG_MRXCNT); 331 } 332 333 /** 334 * rk3x_i2c_fill_transmit_buf - Fill the transmit buffer with data from i2c->msg 335 * @i2c: target controller data 336 */ 337 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c) 338 { 339 unsigned int i, j; 340 u32 cnt = 0; 341 u32 val; 342 u8 byte; 343 344 for (i = 0; i < 8; ++i) { 345 val = 0; 346 for (j = 0; j < 4; ++j) { 347 if ((i2c->processed == i2c->msg->len) && (cnt != 0)) 348 break; 349 350 if (i2c->processed == 0 && cnt == 0) 351 byte = (i2c->addr & 0x7f) << 1; 352 else 353 byte = i2c->msg->buf[i2c->processed++]; 354 355 val |= byte << (j * 8); 356 cnt++; 357 } 358 359 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i); 360 361 if (i2c->processed == i2c->msg->len) 362 break; 363 } 364 365 i2c_writel(i2c, cnt, REG_MTXCNT); 366 } 367 368 369 /* IRQ handlers for individual states */ 370 371 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd) 372 { 373 if (!(ipd & REG_INT_START)) { 374 rk3x_i2c_stop(i2c, -EIO); 375 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd); 376 rk3x_i2c_clean_ipd(i2c); 377 return; 378 } 379 380 /* ack interrupt */ 381 i2c_writel(i2c, REG_INT_START, REG_IPD); 382 383 /* disable start bit */ 384 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON); 385 386 /* enable appropriate interrupts and transition */ 387 if (i2c->mode == REG_CON_MOD_TX) { 388 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN); 389 i2c->state = STATE_WRITE; 390 rk3x_i2c_fill_transmit_buf(i2c); 391 } else { 392 /* in any other case, we are going to be reading. */ 393 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN); 394 i2c->state = STATE_READ; 395 rk3x_i2c_prepare_read(i2c); 396 } 397 } 398 399 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd) 400 { 401 if (!(ipd & REG_INT_MBTF)) { 402 rk3x_i2c_stop(i2c, -EIO); 403 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd); 404 rk3x_i2c_clean_ipd(i2c); 405 return; 406 } 407 408 /* ack interrupt */ 409 i2c_writel(i2c, REG_INT_MBTF, REG_IPD); 410 411 /* are we finished? */ 412 if (i2c->processed == i2c->msg->len) 413 rk3x_i2c_stop(i2c, i2c->error); 414 else 415 rk3x_i2c_fill_transmit_buf(i2c); 416 } 417 418 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) 419 { 420 unsigned int i; 421 unsigned int len = i2c->msg->len - i2c->processed; 422 u32 val; 423 u8 byte; 424 425 /* we only care for MBRF here. */ 426 if (!(ipd & REG_INT_MBRF)) 427 return; 428 429 /* ack interrupt (read also produces a spurious START flag, clear it too) */ 430 i2c_writel(i2c, REG_INT_MBRF | REG_INT_START, REG_IPD); 431 432 /* Can only handle a maximum of 32 bytes at a time */ 433 if (len > 32) 434 len = 32; 435 436 /* read the data from receive buffer */ 437 for (i = 0; i < len; ++i) { 438 if (i % 4 == 0) 439 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4); 440 441 byte = (val >> ((i % 4) * 8)) & 0xff; 442 i2c->msg->buf[i2c->processed++] = byte; 443 } 444 445 /* are we finished? */ 446 if (i2c->processed == i2c->msg->len) 447 rk3x_i2c_stop(i2c, i2c->error); 448 else 449 rk3x_i2c_prepare_read(i2c); 450 } 451 452 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd) 453 { 454 unsigned int con; 455 456 if (!(ipd & REG_INT_STOP)) { 457 rk3x_i2c_stop(i2c, -EIO); 458 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd); 459 rk3x_i2c_clean_ipd(i2c); 460 return; 461 } 462 463 /* ack interrupt */ 464 i2c_writel(i2c, REG_INT_STOP, REG_IPD); 465 466 /* disable STOP bit */ 467 con = i2c_readl(i2c, REG_CON); 468 con &= ~REG_CON_STOP; 469 i2c_writel(i2c, con, REG_CON); 470 471 i2c->busy = false; 472 i2c->state = STATE_IDLE; 473 474 /* signal rk3x_i2c_xfer that we are finished */ 475 wake_up(&i2c->wait); 476 } 477 478 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id) 479 { 480 struct rk3x_i2c *i2c = dev_id; 481 unsigned int ipd; 482 483 spin_lock(&i2c->lock); 484 485 ipd = i2c_readl(i2c, REG_IPD); 486 if (i2c->state == STATE_IDLE) { 487 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd); 488 rk3x_i2c_clean_ipd(i2c); 489 goto out; 490 } 491 492 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd); 493 494 /* Clean interrupt bits we don't care about */ 495 ipd &= ~(REG_INT_BRF | REG_INT_BTF); 496 497 if (ipd & REG_INT_NAKRCV) { 498 /* 499 * We got a NACK in the last operation. Depending on whether 500 * IGNORE_NAK is set, we have to stop the operation and report 501 * an error. 502 */ 503 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD); 504 505 ipd &= ~REG_INT_NAKRCV; 506 507 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 508 rk3x_i2c_stop(i2c, -ENXIO); 509 } 510 511 /* is there anything left to handle? */ 512 if ((ipd & REG_INT_ALL) == 0) 513 goto out; 514 515 switch (i2c->state) { 516 case STATE_START: 517 rk3x_i2c_handle_start(i2c, ipd); 518 break; 519 case STATE_WRITE: 520 rk3x_i2c_handle_write(i2c, ipd); 521 break; 522 case STATE_READ: 523 rk3x_i2c_handle_read(i2c, ipd); 524 break; 525 case STATE_STOP: 526 rk3x_i2c_handle_stop(i2c, ipd); 527 break; 528 case STATE_IDLE: 529 break; 530 } 531 532 out: 533 spin_unlock(&i2c->lock); 534 return IRQ_HANDLED; 535 } 536 537 /** 538 * rk3x_i2c_get_spec - Get timing values of I2C specification 539 * @speed: Desired SCL frequency 540 * 541 * Return: Matched i2c_spec_values. 542 */ 543 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed) 544 { 545 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 546 return &standard_mode_spec; 547 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 548 return &fast_mode_spec; 549 else 550 return &fast_mode_plus_spec; 551 } 552 553 /** 554 * rk3x_i2c_v0_calc_timings - Calculate divider values for desired SCL frequency 555 * @clk_rate: I2C input clock rate 556 * @t: Known I2C timing information 557 * @t_calc: Caculated rk3x private timings that would be written into regs 558 * 559 * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case 560 * a best-effort divider value is returned in divs. If the target rate is 561 * too high, we silently use the highest possible rate. 562 */ 563 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate, 564 struct i2c_timings *t, 565 struct rk3x_i2c_calced_timings *t_calc) 566 { 567 unsigned long min_low_ns, min_high_ns; 568 unsigned long max_low_ns, min_total_ns; 569 570 unsigned long clk_rate_khz, scl_rate_khz; 571 572 unsigned long min_low_div, min_high_div; 573 unsigned long max_low_div; 574 575 unsigned long min_div_for_hold, min_total_div; 576 unsigned long extra_div, extra_low_div, ideal_low_div; 577 578 unsigned long data_hold_buffer_ns = 50; 579 const struct i2c_spec_values *spec; 580 int ret = 0; 581 582 /* Only support standard-mode and fast-mode */ 583 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)) 584 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; 585 586 /* prevent scl_rate_khz from becoming 0 */ 587 if (WARN_ON(t->bus_freq_hz < 1000)) 588 t->bus_freq_hz = 1000; 589 590 /* 591 * min_low_ns: The minimum number of ns we need to hold low to 592 * meet I2C specification, should include fall time. 593 * min_high_ns: The minimum number of ns we need to hold high to 594 * meet I2C specification, should include rise time. 595 * max_low_ns: The maximum number of ns we can hold low to meet 596 * I2C specification. 597 * 598 * Note: max_low_ns should be (maximum data hold time * 2 - buffer) 599 * This is because the i2c host on Rockchip holds the data line 600 * for half the low time. 601 */ 602 spec = rk3x_i2c_get_spec(t->bus_freq_hz); 603 min_high_ns = t->scl_rise_ns + spec->min_high_ns; 604 605 /* 606 * Timings for repeated start: 607 * - controller appears to drop SDA at .875x (7/8) programmed clk high. 608 * - controller appears to keep SCL high for 2x programmed clk high. 609 * 610 * We need to account for those rules in picking our "high" time so 611 * we meet tSU;STA and tHD;STA times. 612 */ 613 min_high_ns = max(min_high_ns, DIV_ROUND_UP( 614 (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875)); 615 min_high_ns = max(min_high_ns, DIV_ROUND_UP( 616 (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns + 617 spec->min_high_ns), 2)); 618 619 min_low_ns = t->scl_fall_ns + spec->min_low_ns; 620 max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns; 621 min_total_ns = min_low_ns + min_high_ns; 622 623 /* Adjust to avoid overflow */ 624 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); 625 scl_rate_khz = t->bus_freq_hz / 1000; 626 627 /* 628 * We need the total div to be >= this number 629 * so we don't clock too fast. 630 */ 631 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); 632 633 /* These are the min dividers needed for min hold times. */ 634 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); 635 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); 636 min_div_for_hold = (min_low_div + min_high_div); 637 638 /* 639 * This is the maximum divider so we don't go over the maximum. 640 * We don't round up here (we round down) since this is a maximum. 641 */ 642 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000); 643 644 if (min_low_div > max_low_div) { 645 WARN_ONCE(true, 646 "Conflicting, min_low_div %lu, max_low_div %lu\n", 647 min_low_div, max_low_div); 648 max_low_div = min_low_div; 649 } 650 651 if (min_div_for_hold > min_total_div) { 652 /* 653 * Time needed to meet hold requirements is important. 654 * Just use that. 655 */ 656 t_calc->div_low = min_low_div; 657 t_calc->div_high = min_high_div; 658 } else { 659 /* 660 * We've got to distribute some time among the low and high 661 * so we don't run too fast. 662 */ 663 extra_div = min_total_div - min_div_for_hold; 664 665 /* 666 * We'll try to split things up perfectly evenly, 667 * biasing slightly towards having a higher div 668 * for low (spend more time low). 669 */ 670 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 671 scl_rate_khz * 8 * min_total_ns); 672 673 /* Don't allow it to go over the maximum */ 674 if (ideal_low_div > max_low_div) 675 ideal_low_div = max_low_div; 676 677 /* 678 * Handle when the ideal low div is going to take up 679 * more than we have. 680 */ 681 if (ideal_low_div > min_low_div + extra_div) 682 ideal_low_div = min_low_div + extra_div; 683 684 /* Give low the "ideal" and give high whatever extra is left */ 685 extra_low_div = ideal_low_div - min_low_div; 686 t_calc->div_low = ideal_low_div; 687 t_calc->div_high = min_high_div + (extra_div - extra_low_div); 688 } 689 690 /* 691 * Adjust to the fact that the hardware has an implicit "+1". 692 * NOTE: Above calculations always produce div_low > 0 and div_high > 0. 693 */ 694 t_calc->div_low--; 695 t_calc->div_high--; 696 697 /* Give the tuning value 0, that would not update con register */ 698 t_calc->tuning = 0; 699 /* Maximum divider supported by hw is 0xffff */ 700 if (t_calc->div_low > 0xffff) { 701 t_calc->div_low = 0xffff; 702 ret = -EINVAL; 703 } 704 705 if (t_calc->div_high > 0xffff) { 706 t_calc->div_high = 0xffff; 707 ret = -EINVAL; 708 } 709 710 return ret; 711 } 712 713 /** 714 * rk3x_i2c_v1_calc_timings - Calculate timing values for desired SCL frequency 715 * @clk_rate: I2C input clock rate 716 * @t: Known I2C timing information 717 * @t_calc: Caculated rk3x private timings that would be written into regs 718 * 719 * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case 720 * a best-effort divider value is returned in divs. If the target rate is 721 * too high, we silently use the highest possible rate. 722 * The following formulas are v1's method to calculate timings. 723 * 724 * l = divl + 1; 725 * h = divh + 1; 726 * s = sda_update_config + 1; 727 * u = start_setup_config + 1; 728 * p = stop_setup_config + 1; 729 * T = Tclk_i2c; 730 * 731 * tHigh = 8 * h * T; 732 * tLow = 8 * l * T; 733 * 734 * tHD;sda = (l * s + 1) * T; 735 * tSU;sda = [(8 - s) * l + 1] * T; 736 * tI2C = 8 * (l + h) * T; 737 * 738 * tSU;sta = (8h * u + 1) * T; 739 * tHD;sta = [8h * (u + 1) - 1] * T; 740 * tSU;sto = (8h * p + 1) * T; 741 */ 742 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate, 743 struct i2c_timings *t, 744 struct rk3x_i2c_calced_timings *t_calc) 745 { 746 unsigned long min_low_ns, min_high_ns; 747 unsigned long min_setup_start_ns, min_setup_data_ns; 748 unsigned long min_setup_stop_ns, max_hold_data_ns; 749 750 unsigned long clk_rate_khz, scl_rate_khz; 751 752 unsigned long min_low_div, min_high_div; 753 754 unsigned long min_div_for_hold, min_total_div; 755 unsigned long extra_div, extra_low_div; 756 unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg; 757 758 const struct i2c_spec_values *spec; 759 int ret = 0; 760 761 /* Support standard-mode, fast-mode and fast-mode plus */ 762 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)) 763 t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ; 764 765 /* prevent scl_rate_khz from becoming 0 */ 766 if (WARN_ON(t->bus_freq_hz < 1000)) 767 t->bus_freq_hz = 1000; 768 769 /* 770 * min_low_ns: The minimum number of ns we need to hold low to 771 * meet I2C specification, should include fall time. 772 * min_high_ns: The minimum number of ns we need to hold high to 773 * meet I2C specification, should include rise time. 774 */ 775 spec = rk3x_i2c_get_spec(t->bus_freq_hz); 776 777 /* calculate min-divh and min-divl */ 778 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); 779 scl_rate_khz = t->bus_freq_hz / 1000; 780 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); 781 782 min_high_ns = t->scl_rise_ns + spec->min_high_ns; 783 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); 784 785 min_low_ns = t->scl_fall_ns + spec->min_low_ns; 786 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); 787 788 /* 789 * Final divh and divl must be greater than 0, otherwise the 790 * hardware would not output the i2c clk. 791 */ 792 min_high_div = (min_high_div < 1) ? 2 : min_high_div; 793 min_low_div = (min_low_div < 1) ? 2 : min_low_div; 794 795 /* These are the min dividers needed for min hold times. */ 796 min_div_for_hold = (min_low_div + min_high_div); 797 798 /* 799 * This is the maximum divider so we don't go over the maximum. 800 * We don't round up here (we round down) since this is a maximum. 801 */ 802 if (min_div_for_hold >= min_total_div) { 803 /* 804 * Time needed to meet hold requirements is important. 805 * Just use that. 806 */ 807 t_calc->div_low = min_low_div; 808 t_calc->div_high = min_high_div; 809 } else { 810 /* 811 * We've got to distribute some time among the low and high 812 * so we don't run too fast. 813 * We'll try to split things up by the scale of min_low_div and 814 * min_high_div, biasing slightly towards having a higher div 815 * for low (spend more time low). 816 */ 817 extra_div = min_total_div - min_div_for_hold; 818 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div, 819 min_div_for_hold); 820 821 t_calc->div_low = min_low_div + extra_low_div; 822 t_calc->div_high = min_high_div + (extra_div - extra_low_div); 823 } 824 825 /* 826 * calculate sda data hold count by the rules, data_upd_st:3 827 * is a appropriate value to reduce calculated times. 828 */ 829 for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) { 830 max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg 831 * (t_calc->div_low) + 1) 832 * 1000000, clk_rate_khz); 833 min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg) 834 * (t_calc->div_low) + 1) 835 * 1000000, clk_rate_khz); 836 if ((max_hold_data_ns < spec->max_data_hold_ns) && 837 (min_setup_data_ns > spec->min_data_setup_ns)) 838 break; 839 } 840 841 /* calculate setup start config */ 842 min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns; 843 stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns 844 - 1000000, 8 * 1000000 * (t_calc->div_high)); 845 846 /* calculate setup stop config */ 847 min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns; 848 stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns 849 - 1000000, 8 * 1000000 * (t_calc->div_high)); 850 851 t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) | 852 REG_CON_STA_CFG(--stp_sta_cfg) | 853 REG_CON_STO_CFG(--stp_sto_cfg); 854 855 t_calc->div_low--; 856 t_calc->div_high--; 857 858 /* Maximum divider supported by hw is 0xffff */ 859 if (t_calc->div_low > 0xffff) { 860 t_calc->div_low = 0xffff; 861 ret = -EINVAL; 862 } 863 864 if (t_calc->div_high > 0xffff) { 865 t_calc->div_high = 0xffff; 866 ret = -EINVAL; 867 } 868 869 return ret; 870 } 871 872 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate) 873 { 874 struct i2c_timings *t = &i2c->t; 875 struct rk3x_i2c_calced_timings calc; 876 u64 t_low_ns, t_high_ns; 877 unsigned long flags; 878 u32 val; 879 int ret; 880 881 ret = i2c->soc_data->calc_timings(clk_rate, t, &calc); 882 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz); 883 884 clk_enable(i2c->pclk); 885 886 spin_lock_irqsave(&i2c->lock, flags); 887 val = i2c_readl(i2c, REG_CON); 888 val &= ~REG_CON_TUNING_MASK; 889 val |= calc.tuning; 890 i2c_writel(i2c, val, REG_CON); 891 i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff), 892 REG_CLKDIV); 893 spin_unlock_irqrestore(&i2c->lock, flags); 894 895 clk_disable(i2c->pclk); 896 897 t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate); 898 t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000, 899 clk_rate); 900 dev_dbg(i2c->dev, 901 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n", 902 clk_rate / 1000, 903 1000000000 / t->bus_freq_hz, 904 t_low_ns, t_high_ns); 905 } 906 907 /** 908 * rk3x_i2c_clk_notifier_cb - Clock rate change callback 909 * @nb: Pointer to notifier block 910 * @event: Notification reason 911 * @data: Pointer to notification data object 912 * 913 * The callback checks whether a valid bus frequency can be generated after the 914 * change. If so, the change is acknowledged, otherwise the change is aborted. 915 * New dividers are written to the HW in the pre- or post change notification 916 * depending on the scaling direction. 917 * 918 * Code adapted from i2c-cadence.c. 919 * 920 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 921 * to acknowledge the change, NOTIFY_DONE if the notification is 922 * considered irrelevant. 923 */ 924 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 925 event, void *data) 926 { 927 struct clk_notifier_data *ndata = data; 928 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb); 929 struct rk3x_i2c_calced_timings calc; 930 931 switch (event) { 932 case PRE_RATE_CHANGE: 933 /* 934 * Try the calculation (but don't store the result) ahead of 935 * time to see if we need to block the clock change. Timings 936 * shouldn't actually take effect until rk3x_i2c_adapt_div(). 937 */ 938 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t, 939 &calc) != 0) 940 return NOTIFY_STOP; 941 942 /* scale up */ 943 if (ndata->new_rate > ndata->old_rate) 944 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 945 946 return NOTIFY_OK; 947 case POST_RATE_CHANGE: 948 /* scale down */ 949 if (ndata->new_rate < ndata->old_rate) 950 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 951 return NOTIFY_OK; 952 case ABORT_RATE_CHANGE: 953 /* scale up */ 954 if (ndata->new_rate > ndata->old_rate) 955 rk3x_i2c_adapt_div(i2c, ndata->old_rate); 956 return NOTIFY_OK; 957 default: 958 return NOTIFY_DONE; 959 } 960 } 961 962 /** 963 * rk3x_i2c_setup - Setup I2C registers for an I2C operation specified by msgs, num. 964 * @i2c: target controller data 965 * @msgs: I2C msgs to process 966 * @num: Number of msgs 967 * 968 * Must be called with i2c->lock held. 969 * 970 * Return: Number of I2C msgs processed or negative in case of error 971 */ 972 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num) 973 { 974 u32 addr = (msgs[0].addr & 0x7f) << 1; 975 int ret = 0; 976 977 /* 978 * The I2C adapter can issue a small (len < 4) write packet before 979 * reading. This speeds up SMBus-style register reads. 980 * The MRXADDR/MRXRADDR hold the slave address and the slave register 981 * address in this case. 982 */ 983 984 if (num >= 2 && msgs[0].len < 4 && 985 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) { 986 u32 reg_addr = 0; 987 int i; 988 989 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n", 990 addr >> 1); 991 992 /* Fill MRXRADDR with the register address(es) */ 993 for (i = 0; i < msgs[0].len; ++i) { 994 reg_addr |= msgs[0].buf[i] << (i * 8); 995 reg_addr |= REG_MRXADDR_VALID(i); 996 } 997 998 /* msgs[0] is handled by hw. */ 999 i2c->msg = &msgs[1]; 1000 1001 i2c->mode = REG_CON_MOD_REGISTER_TX; 1002 1003 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR); 1004 i2c_writel(i2c, reg_addr, REG_MRXRADDR); 1005 1006 ret = 2; 1007 } else { 1008 /* 1009 * We'll have to do it the boring way and process the msgs 1010 * one-by-one. 1011 */ 1012 1013 if (msgs[0].flags & I2C_M_RD) { 1014 addr |= 1; /* set read bit */ 1015 1016 /* 1017 * We have to transmit the slave addr first. Use 1018 * MOD_REGISTER_TX for that purpose. 1019 */ 1020 i2c->mode = REG_CON_MOD_REGISTER_TX; 1021 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), 1022 REG_MRXADDR); 1023 i2c_writel(i2c, 0, REG_MRXRADDR); 1024 } else { 1025 i2c->mode = REG_CON_MOD_TX; 1026 } 1027 1028 i2c->msg = &msgs[0]; 1029 1030 ret = 1; 1031 } 1032 1033 i2c->addr = msgs[0].addr; 1034 i2c->busy = true; 1035 i2c->state = STATE_START; 1036 i2c->processed = 0; 1037 i2c->error = 0; 1038 1039 rk3x_i2c_clean_ipd(i2c); 1040 1041 return ret; 1042 } 1043 1044 static int rk3x_i2c_wait_xfer_poll(struct rk3x_i2c *i2c) 1045 { 1046 ktime_t timeout = ktime_add_ms(ktime_get(), WAIT_TIMEOUT); 1047 1048 while (READ_ONCE(i2c->busy) && 1049 ktime_compare(ktime_get(), timeout) < 0) { 1050 udelay(5); 1051 rk3x_i2c_irq(0, i2c); 1052 } 1053 1054 return !i2c->busy; 1055 } 1056 1057 static int rk3x_i2c_xfer_common(struct i2c_adapter *adap, 1058 struct i2c_msg *msgs, int num, bool polling) 1059 { 1060 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data; 1061 unsigned long timeout, flags; 1062 u32 val; 1063 int ret = 0; 1064 int i; 1065 1066 spin_lock_irqsave(&i2c->lock, flags); 1067 1068 clk_enable(i2c->clk); 1069 clk_enable(i2c->pclk); 1070 1071 i2c->is_last_msg = false; 1072 1073 /* 1074 * Process msgs. We can handle more than one message at once (see 1075 * rk3x_i2c_setup()). 1076 */ 1077 for (i = 0; i < num; i += ret) { 1078 ret = rk3x_i2c_setup(i2c, msgs + i, num - i); 1079 1080 if (ret < 0) { 1081 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n"); 1082 break; 1083 } 1084 1085 if (i + ret >= num) 1086 i2c->is_last_msg = true; 1087 1088 spin_unlock_irqrestore(&i2c->lock, flags); 1089 1090 rk3x_i2c_start(i2c); 1091 1092 if (!polling) { 1093 timeout = wait_event_timeout(i2c->wait, !i2c->busy, 1094 msecs_to_jiffies(WAIT_TIMEOUT)); 1095 } else { 1096 timeout = rk3x_i2c_wait_xfer_poll(i2c); 1097 } 1098 1099 spin_lock_irqsave(&i2c->lock, flags); 1100 1101 if (timeout == 0) { 1102 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n", 1103 i2c_readl(i2c, REG_IPD), i2c->state); 1104 1105 /* Force a STOP condition without interrupt */ 1106 i2c_writel(i2c, 0, REG_IEN); 1107 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 1108 val |= REG_CON_EN | REG_CON_STOP; 1109 i2c_writel(i2c, val, REG_CON); 1110 1111 i2c->state = STATE_IDLE; 1112 1113 ret = -ETIMEDOUT; 1114 break; 1115 } 1116 1117 if (i2c->error) { 1118 ret = i2c->error; 1119 break; 1120 } 1121 } 1122 1123 clk_disable(i2c->pclk); 1124 clk_disable(i2c->clk); 1125 1126 spin_unlock_irqrestore(&i2c->lock, flags); 1127 1128 return ret < 0 ? ret : num; 1129 } 1130 1131 static int rk3x_i2c_xfer(struct i2c_adapter *adap, 1132 struct i2c_msg *msgs, int num) 1133 { 1134 return rk3x_i2c_xfer_common(adap, msgs, num, false); 1135 } 1136 1137 static int rk3x_i2c_xfer_polling(struct i2c_adapter *adap, 1138 struct i2c_msg *msgs, int num) 1139 { 1140 return rk3x_i2c_xfer_common(adap, msgs, num, true); 1141 } 1142 1143 static __maybe_unused int rk3x_i2c_resume(struct device *dev) 1144 { 1145 struct rk3x_i2c *i2c = dev_get_drvdata(dev); 1146 1147 rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk)); 1148 1149 return 0; 1150 } 1151 1152 static u32 rk3x_i2c_func(struct i2c_adapter *adap) 1153 { 1154 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 1155 } 1156 1157 static const struct i2c_algorithm rk3x_i2c_algorithm = { 1158 .master_xfer = rk3x_i2c_xfer, 1159 .master_xfer_atomic = rk3x_i2c_xfer_polling, 1160 .functionality = rk3x_i2c_func, 1161 }; 1162 1163 static const struct rk3x_i2c_soc_data rv1108_soc_data = { 1164 .grf_offset = -1, 1165 .calc_timings = rk3x_i2c_v1_calc_timings, 1166 }; 1167 1168 static const struct rk3x_i2c_soc_data rv1126_soc_data = { 1169 .grf_offset = 0x118, 1170 .calc_timings = rk3x_i2c_v1_calc_timings, 1171 }; 1172 1173 static const struct rk3x_i2c_soc_data rk3066_soc_data = { 1174 .grf_offset = 0x154, 1175 .calc_timings = rk3x_i2c_v0_calc_timings, 1176 }; 1177 1178 static const struct rk3x_i2c_soc_data rk3188_soc_data = { 1179 .grf_offset = 0x0a4, 1180 .calc_timings = rk3x_i2c_v0_calc_timings, 1181 }; 1182 1183 static const struct rk3x_i2c_soc_data rk3228_soc_data = { 1184 .grf_offset = -1, 1185 .calc_timings = rk3x_i2c_v0_calc_timings, 1186 }; 1187 1188 static const struct rk3x_i2c_soc_data rk3288_soc_data = { 1189 .grf_offset = -1, 1190 .calc_timings = rk3x_i2c_v0_calc_timings, 1191 }; 1192 1193 static const struct rk3x_i2c_soc_data rk3399_soc_data = { 1194 .grf_offset = -1, 1195 .calc_timings = rk3x_i2c_v1_calc_timings, 1196 }; 1197 1198 static const struct of_device_id rk3x_i2c_match[] = { 1199 { 1200 .compatible = "rockchip,rv1108-i2c", 1201 .data = &rv1108_soc_data 1202 }, 1203 { 1204 .compatible = "rockchip,rv1126-i2c", 1205 .data = &rv1126_soc_data 1206 }, 1207 { 1208 .compatible = "rockchip,rk3066-i2c", 1209 .data = &rk3066_soc_data 1210 }, 1211 { 1212 .compatible = "rockchip,rk3188-i2c", 1213 .data = &rk3188_soc_data 1214 }, 1215 { 1216 .compatible = "rockchip,rk3228-i2c", 1217 .data = &rk3228_soc_data 1218 }, 1219 { 1220 .compatible = "rockchip,rk3288-i2c", 1221 .data = &rk3288_soc_data 1222 }, 1223 { 1224 .compatible = "rockchip,rk3399-i2c", 1225 .data = &rk3399_soc_data 1226 }, 1227 {}, 1228 }; 1229 MODULE_DEVICE_TABLE(of, rk3x_i2c_match); 1230 1231 static int rk3x_i2c_probe(struct platform_device *pdev) 1232 { 1233 struct device_node *np = pdev->dev.of_node; 1234 const struct of_device_id *match; 1235 struct rk3x_i2c *i2c; 1236 int ret = 0; 1237 int bus_nr; 1238 u32 value; 1239 int irq; 1240 unsigned long clk_rate; 1241 1242 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL); 1243 if (!i2c) 1244 return -ENOMEM; 1245 1246 match = of_match_node(rk3x_i2c_match, np); 1247 i2c->soc_data = match->data; 1248 1249 /* use common interface to get I2C timing properties */ 1250 i2c_parse_fw_timings(&pdev->dev, &i2c->t, true); 1251 1252 strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); 1253 i2c->adap.owner = THIS_MODULE; 1254 i2c->adap.algo = &rk3x_i2c_algorithm; 1255 i2c->adap.retries = 3; 1256 i2c->adap.dev.of_node = np; 1257 i2c->adap.algo_data = i2c; 1258 i2c->adap.dev.parent = &pdev->dev; 1259 1260 i2c->dev = &pdev->dev; 1261 1262 spin_lock_init(&i2c->lock); 1263 init_waitqueue_head(&i2c->wait); 1264 1265 i2c->regs = devm_platform_ioremap_resource(pdev, 0); 1266 if (IS_ERR(i2c->regs)) 1267 return PTR_ERR(i2c->regs); 1268 1269 /* Try to set the I2C adapter number from dt */ 1270 bus_nr = of_alias_get_id(np, "i2c"); 1271 1272 /* 1273 * Switch to new interface if the SoC also offers the old one. 1274 * The control bit is located in the GRF register space. 1275 */ 1276 if (i2c->soc_data->grf_offset >= 0) { 1277 struct regmap *grf; 1278 1279 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1280 if (IS_ERR(grf)) { 1281 dev_err(&pdev->dev, 1282 "rk3x-i2c needs 'rockchip,grf' property\n"); 1283 return PTR_ERR(grf); 1284 } 1285 1286 if (bus_nr < 0) { 1287 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias"); 1288 return -EINVAL; 1289 } 1290 1291 /* 27+i: write mask, 11+i: value */ 1292 value = BIT(27 + bus_nr) | BIT(11 + bus_nr); 1293 1294 ret = regmap_write(grf, i2c->soc_data->grf_offset, value); 1295 if (ret != 0) { 1296 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret); 1297 return ret; 1298 } 1299 } 1300 1301 /* IRQ setup */ 1302 irq = platform_get_irq(pdev, 0); 1303 if (irq < 0) 1304 return irq; 1305 1306 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq, 1307 0, dev_name(&pdev->dev), i2c); 1308 if (ret < 0) { 1309 dev_err(&pdev->dev, "cannot request IRQ\n"); 1310 return ret; 1311 } 1312 1313 platform_set_drvdata(pdev, i2c); 1314 1315 if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) { 1316 /* Only one clock to use for bus clock and peripheral clock */ 1317 i2c->clk = devm_clk_get(&pdev->dev, NULL); 1318 i2c->pclk = i2c->clk; 1319 } else { 1320 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1321 i2c->pclk = devm_clk_get(&pdev->dev, "pclk"); 1322 } 1323 1324 if (IS_ERR(i2c->clk)) 1325 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 1326 "Can't get bus clk\n"); 1327 1328 if (IS_ERR(i2c->pclk)) 1329 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk), 1330 "Can't get periph clk\n"); 1331 1332 ret = clk_prepare(i2c->clk); 1333 if (ret < 0) { 1334 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret); 1335 return ret; 1336 } 1337 ret = clk_prepare(i2c->pclk); 1338 if (ret < 0) { 1339 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret); 1340 goto err_clk; 1341 } 1342 1343 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb; 1344 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb); 1345 if (ret != 0) { 1346 dev_err(&pdev->dev, "Unable to register clock notifier\n"); 1347 goto err_pclk; 1348 } 1349 1350 ret = clk_enable(i2c->clk); 1351 if (ret < 0) { 1352 dev_err(&pdev->dev, "Can't enable bus clk: %d\n", ret); 1353 goto err_clk_notifier; 1354 } 1355 1356 clk_rate = clk_get_rate(i2c->clk); 1357 rk3x_i2c_adapt_div(i2c, clk_rate); 1358 clk_disable(i2c->clk); 1359 1360 ret = i2c_add_adapter(&i2c->adap); 1361 if (ret < 0) 1362 goto err_clk_notifier; 1363 1364 return 0; 1365 1366 err_clk_notifier: 1367 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 1368 err_pclk: 1369 clk_unprepare(i2c->pclk); 1370 err_clk: 1371 clk_unprepare(i2c->clk); 1372 return ret; 1373 } 1374 1375 static int rk3x_i2c_remove(struct platform_device *pdev) 1376 { 1377 struct rk3x_i2c *i2c = platform_get_drvdata(pdev); 1378 1379 i2c_del_adapter(&i2c->adap); 1380 1381 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 1382 clk_unprepare(i2c->pclk); 1383 clk_unprepare(i2c->clk); 1384 1385 return 0; 1386 } 1387 1388 static SIMPLE_DEV_PM_OPS(rk3x_i2c_pm_ops, NULL, rk3x_i2c_resume); 1389 1390 static struct platform_driver rk3x_i2c_driver = { 1391 .probe = rk3x_i2c_probe, 1392 .remove = rk3x_i2c_remove, 1393 .driver = { 1394 .name = "rk3x-i2c", 1395 .of_match_table = rk3x_i2c_match, 1396 .pm = &rk3x_i2c_pm_ops, 1397 }, 1398 }; 1399 1400 module_platform_driver(rk3x_i2c_driver); 1401 1402 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver"); 1403 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>"); 1404 MODULE_LICENSE("GPL v2"); 1405