1 /* 2 * Driver for I2C adapter in Rockchip RK3xxx SoC 3 * 4 * Max Schwarz <max.schwarz@online.de> 5 * based on the patches by Rockchip Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/platform_device.h> 19 #include <linux/io.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/spinlock.h> 23 #include <linux/clk.h> 24 #include <linux/wait.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/regmap.h> 27 28 29 /* Register Map */ 30 #define REG_CON 0x00 /* control register */ 31 #define REG_CLKDIV 0x04 /* clock divisor register */ 32 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */ 33 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */ 34 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */ 35 #define REG_MRXCNT 0x14 /* number of bytes to be received */ 36 #define REG_IEN 0x18 /* interrupt enable */ 37 #define REG_IPD 0x1c /* interrupt pending */ 38 #define REG_FCNT 0x20 /* finished count */ 39 40 /* Data buffer offsets */ 41 #define TXBUFFER_BASE 0x100 42 #define RXBUFFER_BASE 0x200 43 44 /* REG_CON bits */ 45 #define REG_CON_EN BIT(0) 46 enum { 47 REG_CON_MOD_TX = 0, /* transmit data */ 48 REG_CON_MOD_REGISTER_TX, /* select register and restart */ 49 REG_CON_MOD_RX, /* receive data */ 50 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes 51 * register addr */ 52 }; 53 #define REG_CON_MOD(mod) ((mod) << 1) 54 #define REG_CON_MOD_MASK (BIT(1) | BIT(2)) 55 #define REG_CON_START BIT(3) 56 #define REG_CON_STOP BIT(4) 57 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */ 58 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */ 59 60 /* REG_MRXADDR bits */ 61 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */ 62 63 /* REG_IEN/REG_IPD bits */ 64 #define REG_INT_BTF BIT(0) /* a byte was transmitted */ 65 #define REG_INT_BRF BIT(1) /* a byte was received */ 66 #define REG_INT_MBTF BIT(2) /* master data transmit finished */ 67 #define REG_INT_MBRF BIT(3) /* master data receive finished */ 68 #define REG_INT_START BIT(4) /* START condition generated */ 69 #define REG_INT_STOP BIT(5) /* STOP condition generated */ 70 #define REG_INT_NAKRCV BIT(6) /* NACK received */ 71 #define REG_INT_ALL 0x7f 72 73 /* Constants */ 74 #define WAIT_TIMEOUT 200 /* ms */ 75 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ 76 77 enum rk3x_i2c_state { 78 STATE_IDLE, 79 STATE_START, 80 STATE_READ, 81 STATE_WRITE, 82 STATE_STOP 83 }; 84 85 /** 86 * @grf_offset: offset inside the grf regmap for setting the i2c type 87 */ 88 struct rk3x_i2c_soc_data { 89 int grf_offset; 90 }; 91 92 struct rk3x_i2c { 93 struct i2c_adapter adap; 94 struct device *dev; 95 struct rk3x_i2c_soc_data *soc_data; 96 97 /* Hardware resources */ 98 void __iomem *regs; 99 struct clk *clk; 100 101 /* Settings */ 102 unsigned int scl_frequency; 103 104 /* Synchronization & notification */ 105 spinlock_t lock; 106 wait_queue_head_t wait; 107 bool busy; 108 109 /* Current message */ 110 struct i2c_msg *msg; 111 u8 addr; 112 unsigned int mode; 113 bool is_last_msg; 114 115 /* I2C state machine */ 116 enum rk3x_i2c_state state; 117 unsigned int processed; /* sent/received bytes */ 118 int error; 119 }; 120 121 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value, 122 unsigned int offset) 123 { 124 writel(value, i2c->regs + offset); 125 } 126 127 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset) 128 { 129 return readl(i2c->regs + offset); 130 } 131 132 /* Reset all interrupt pending bits */ 133 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c) 134 { 135 i2c_writel(i2c, REG_INT_ALL, REG_IPD); 136 } 137 138 /** 139 * Generate a START condition, which triggers a REG_INT_START interrupt. 140 */ 141 static void rk3x_i2c_start(struct rk3x_i2c *i2c) 142 { 143 u32 val; 144 145 rk3x_i2c_clean_ipd(i2c); 146 i2c_writel(i2c, REG_INT_START, REG_IEN); 147 148 /* enable adapter with correct mode, send START condition */ 149 val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START; 150 151 /* if we want to react to NACK, set ACTACK bit */ 152 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 153 val |= REG_CON_ACTACK; 154 155 i2c_writel(i2c, val, REG_CON); 156 } 157 158 /** 159 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt. 160 * 161 * @error: Error code to return in rk3x_i2c_xfer 162 */ 163 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error) 164 { 165 unsigned int ctrl; 166 167 i2c->processed = 0; 168 i2c->msg = NULL; 169 i2c->error = error; 170 171 if (i2c->is_last_msg) { 172 /* Enable stop interrupt */ 173 i2c_writel(i2c, REG_INT_STOP, REG_IEN); 174 175 i2c->state = STATE_STOP; 176 177 ctrl = i2c_readl(i2c, REG_CON); 178 ctrl |= REG_CON_STOP; 179 i2c_writel(i2c, ctrl, REG_CON); 180 } else { 181 /* Signal rk3x_i2c_xfer to start the next message. */ 182 i2c->busy = false; 183 i2c->state = STATE_IDLE; 184 185 /* 186 * The HW is actually not capable of REPEATED START. But we can 187 * get the intended effect by resetting its internal state 188 * and issuing an ordinary START. 189 */ 190 i2c_writel(i2c, 0, REG_CON); 191 192 /* signal that we are finished with the current msg */ 193 wake_up(&i2c->wait); 194 } 195 } 196 197 /** 198 * Setup a read according to i2c->msg 199 */ 200 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c) 201 { 202 unsigned int len = i2c->msg->len - i2c->processed; 203 u32 con; 204 205 con = i2c_readl(i2c, REG_CON); 206 207 /* 208 * The hw can read up to 32 bytes at a time. If we need more than one 209 * chunk, send an ACK after the last byte of the current chunk. 210 */ 211 if (unlikely(len > 32)) { 212 len = 32; 213 con &= ~REG_CON_LASTACK; 214 } else { 215 con |= REG_CON_LASTACK; 216 } 217 218 /* make sure we are in plain RX mode if we read a second chunk */ 219 if (i2c->processed != 0) { 220 con &= ~REG_CON_MOD_MASK; 221 con |= REG_CON_MOD(REG_CON_MOD_RX); 222 } 223 224 i2c_writel(i2c, con, REG_CON); 225 i2c_writel(i2c, len, REG_MRXCNT); 226 } 227 228 /** 229 * Fill the transmit buffer with data from i2c->msg 230 */ 231 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c) 232 { 233 unsigned int i, j; 234 u32 cnt = 0; 235 u32 val; 236 u8 byte; 237 238 for (i = 0; i < 8; ++i) { 239 val = 0; 240 for (j = 0; j < 4; ++j) { 241 if (i2c->processed == i2c->msg->len) 242 break; 243 244 if (i2c->processed == 0 && cnt == 0) 245 byte = (i2c->addr & 0x7f) << 1; 246 else 247 byte = i2c->msg->buf[i2c->processed++]; 248 249 val |= byte << (j * 8); 250 cnt++; 251 } 252 253 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i); 254 255 if (i2c->processed == i2c->msg->len) 256 break; 257 } 258 259 i2c_writel(i2c, cnt, REG_MTXCNT); 260 } 261 262 263 /* IRQ handlers for individual states */ 264 265 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd) 266 { 267 if (!(ipd & REG_INT_START)) { 268 rk3x_i2c_stop(i2c, -EIO); 269 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd); 270 rk3x_i2c_clean_ipd(i2c); 271 return; 272 } 273 274 /* ack interrupt */ 275 i2c_writel(i2c, REG_INT_START, REG_IPD); 276 277 /* disable start bit */ 278 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON); 279 280 /* enable appropriate interrupts and transition */ 281 if (i2c->mode == REG_CON_MOD_TX) { 282 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN); 283 i2c->state = STATE_WRITE; 284 rk3x_i2c_fill_transmit_buf(i2c); 285 } else { 286 /* in any other case, we are going to be reading. */ 287 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN); 288 i2c->state = STATE_READ; 289 rk3x_i2c_prepare_read(i2c); 290 } 291 } 292 293 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd) 294 { 295 if (!(ipd & REG_INT_MBTF)) { 296 rk3x_i2c_stop(i2c, -EIO); 297 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd); 298 rk3x_i2c_clean_ipd(i2c); 299 return; 300 } 301 302 /* ack interrupt */ 303 i2c_writel(i2c, REG_INT_MBTF, REG_IPD); 304 305 /* are we finished? */ 306 if (i2c->processed == i2c->msg->len) 307 rk3x_i2c_stop(i2c, i2c->error); 308 else 309 rk3x_i2c_fill_transmit_buf(i2c); 310 } 311 312 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) 313 { 314 unsigned int i; 315 unsigned int len = i2c->msg->len - i2c->processed; 316 u32 uninitialized_var(val); 317 u8 byte; 318 319 /* we only care for MBRF here. */ 320 if (!(ipd & REG_INT_MBRF)) 321 return; 322 323 /* ack interrupt */ 324 i2c_writel(i2c, REG_INT_MBRF, REG_IPD); 325 326 /* read the data from receive buffer */ 327 for (i = 0; i < len; ++i) { 328 if (i % 4 == 0) 329 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4); 330 331 byte = (val >> ((i % 4) * 8)) & 0xff; 332 i2c->msg->buf[i2c->processed++] = byte; 333 } 334 335 /* are we finished? */ 336 if (i2c->processed == i2c->msg->len) 337 rk3x_i2c_stop(i2c, i2c->error); 338 else 339 rk3x_i2c_prepare_read(i2c); 340 } 341 342 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd) 343 { 344 unsigned int con; 345 346 if (!(ipd & REG_INT_STOP)) { 347 rk3x_i2c_stop(i2c, -EIO); 348 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd); 349 rk3x_i2c_clean_ipd(i2c); 350 return; 351 } 352 353 /* ack interrupt */ 354 i2c_writel(i2c, REG_INT_STOP, REG_IPD); 355 356 /* disable STOP bit */ 357 con = i2c_readl(i2c, REG_CON); 358 con &= ~REG_CON_STOP; 359 i2c_writel(i2c, con, REG_CON); 360 361 i2c->busy = false; 362 i2c->state = STATE_IDLE; 363 364 /* signal rk3x_i2c_xfer that we are finished */ 365 wake_up(&i2c->wait); 366 } 367 368 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id) 369 { 370 struct rk3x_i2c *i2c = dev_id; 371 unsigned int ipd; 372 373 spin_lock(&i2c->lock); 374 375 ipd = i2c_readl(i2c, REG_IPD); 376 if (i2c->state == STATE_IDLE) { 377 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd); 378 rk3x_i2c_clean_ipd(i2c); 379 goto out; 380 } 381 382 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd); 383 384 /* Clean interrupt bits we don't care about */ 385 ipd &= ~(REG_INT_BRF | REG_INT_BTF); 386 387 if (ipd & REG_INT_NAKRCV) { 388 /* 389 * We got a NACK in the last operation. Depending on whether 390 * IGNORE_NAK is set, we have to stop the operation and report 391 * an error. 392 */ 393 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD); 394 395 ipd &= ~REG_INT_NAKRCV; 396 397 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 398 rk3x_i2c_stop(i2c, -ENXIO); 399 } 400 401 /* is there anything left to handle? */ 402 if (unlikely(ipd == 0)) 403 goto out; 404 405 switch (i2c->state) { 406 case STATE_START: 407 rk3x_i2c_handle_start(i2c, ipd); 408 break; 409 case STATE_WRITE: 410 rk3x_i2c_handle_write(i2c, ipd); 411 break; 412 case STATE_READ: 413 rk3x_i2c_handle_read(i2c, ipd); 414 break; 415 case STATE_STOP: 416 rk3x_i2c_handle_stop(i2c, ipd); 417 break; 418 case STATE_IDLE: 419 break; 420 } 421 422 out: 423 spin_unlock(&i2c->lock); 424 return IRQ_HANDLED; 425 } 426 427 static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate) 428 { 429 unsigned long i2c_rate = clk_get_rate(i2c->clk); 430 unsigned int div; 431 432 /* SCL rate = (clk rate) / (8 * DIV) */ 433 div = DIV_ROUND_UP(i2c_rate, scl_rate * 8); 434 435 /* The lower and upper half of the CLKDIV reg describe the length of 436 * SCL low & high periods. */ 437 div = DIV_ROUND_UP(div, 2); 438 439 i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV); 440 } 441 442 /** 443 * Setup I2C registers for an I2C operation specified by msgs, num. 444 * 445 * Must be called with i2c->lock held. 446 * 447 * @msgs: I2C msgs to process 448 * @num: Number of msgs 449 * 450 * returns: Number of I2C msgs processed or negative in case of error 451 */ 452 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num) 453 { 454 u32 addr = (msgs[0].addr & 0x7f) << 1; 455 int ret = 0; 456 457 /* 458 * The I2C adapter can issue a small (len < 4) write packet before 459 * reading. This speeds up SMBus-style register reads. 460 * The MRXADDR/MRXRADDR hold the slave address and the slave register 461 * address in this case. 462 */ 463 464 if (num >= 2 && msgs[0].len < 4 && 465 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) { 466 u32 reg_addr = 0; 467 int i; 468 469 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n", 470 addr >> 1); 471 472 /* Fill MRXRADDR with the register address(es) */ 473 for (i = 0; i < msgs[0].len; ++i) { 474 reg_addr |= msgs[0].buf[i] << (i * 8); 475 reg_addr |= REG_MRXADDR_VALID(i); 476 } 477 478 /* msgs[0] is handled by hw. */ 479 i2c->msg = &msgs[1]; 480 481 i2c->mode = REG_CON_MOD_REGISTER_TX; 482 483 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR); 484 i2c_writel(i2c, reg_addr, REG_MRXRADDR); 485 486 ret = 2; 487 } else { 488 /* 489 * We'll have to do it the boring way and process the msgs 490 * one-by-one. 491 */ 492 493 if (msgs[0].flags & I2C_M_RD) { 494 addr |= 1; /* set read bit */ 495 496 /* 497 * We have to transmit the slave addr first. Use 498 * MOD_REGISTER_TX for that purpose. 499 */ 500 i2c->mode = REG_CON_MOD_REGISTER_TX; 501 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), 502 REG_MRXADDR); 503 i2c_writel(i2c, 0, REG_MRXRADDR); 504 } else { 505 i2c->mode = REG_CON_MOD_TX; 506 } 507 508 i2c->msg = &msgs[0]; 509 510 ret = 1; 511 } 512 513 i2c->addr = msgs[0].addr; 514 i2c->busy = true; 515 i2c->state = STATE_START; 516 i2c->processed = 0; 517 i2c->error = 0; 518 519 rk3x_i2c_clean_ipd(i2c); 520 521 return ret; 522 } 523 524 static int rk3x_i2c_xfer(struct i2c_adapter *adap, 525 struct i2c_msg *msgs, int num) 526 { 527 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data; 528 unsigned long timeout, flags; 529 int ret = 0; 530 int i; 531 532 spin_lock_irqsave(&i2c->lock, flags); 533 534 clk_enable(i2c->clk); 535 536 /* The clock rate might have changed, so setup the divider again */ 537 rk3x_i2c_set_scl_rate(i2c, i2c->scl_frequency); 538 539 i2c->is_last_msg = false; 540 541 /* 542 * Process msgs. We can handle more than one message at once (see 543 * rk3x_i2c_setup()). 544 */ 545 for (i = 0; i < num; i += ret) { 546 ret = rk3x_i2c_setup(i2c, msgs + i, num - i); 547 548 if (ret < 0) { 549 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n"); 550 break; 551 } 552 553 if (i + ret >= num) 554 i2c->is_last_msg = true; 555 556 spin_unlock_irqrestore(&i2c->lock, flags); 557 558 rk3x_i2c_start(i2c); 559 560 timeout = wait_event_timeout(i2c->wait, !i2c->busy, 561 msecs_to_jiffies(WAIT_TIMEOUT)); 562 563 spin_lock_irqsave(&i2c->lock, flags); 564 565 if (timeout == 0) { 566 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n", 567 i2c_readl(i2c, REG_IPD), i2c->state); 568 569 /* Force a STOP condition without interrupt */ 570 i2c_writel(i2c, 0, REG_IEN); 571 i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON); 572 573 i2c->state = STATE_IDLE; 574 575 ret = -ETIMEDOUT; 576 break; 577 } 578 579 if (i2c->error) { 580 ret = i2c->error; 581 break; 582 } 583 } 584 585 clk_disable(i2c->clk); 586 spin_unlock_irqrestore(&i2c->lock, flags); 587 588 return ret; 589 } 590 591 static u32 rk3x_i2c_func(struct i2c_adapter *adap) 592 { 593 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 594 } 595 596 static const struct i2c_algorithm rk3x_i2c_algorithm = { 597 .master_xfer = rk3x_i2c_xfer, 598 .functionality = rk3x_i2c_func, 599 }; 600 601 static struct rk3x_i2c_soc_data soc_data[3] = { 602 { .grf_offset = 0x154 }, /* rk3066 */ 603 { .grf_offset = 0x0a4 }, /* rk3188 */ 604 { .grf_offset = -1 }, /* no I2C switching needed */ 605 }; 606 607 static const struct of_device_id rk3x_i2c_match[] = { 608 { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] }, 609 { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] }, 610 { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] }, 611 {}, 612 }; 613 614 static int rk3x_i2c_probe(struct platform_device *pdev) 615 { 616 struct device_node *np = pdev->dev.of_node; 617 const struct of_device_id *match; 618 struct rk3x_i2c *i2c; 619 struct resource *mem; 620 int ret = 0; 621 int bus_nr; 622 u32 value; 623 int irq; 624 625 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL); 626 if (!i2c) 627 return -ENOMEM; 628 629 match = of_match_node(rk3x_i2c_match, np); 630 i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data; 631 632 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", 633 &i2c->scl_frequency)) { 634 dev_info(&pdev->dev, "using default SCL frequency: %d\n", 635 DEFAULT_SCL_RATE); 636 i2c->scl_frequency = DEFAULT_SCL_RATE; 637 } 638 639 if (i2c->scl_frequency == 0 || i2c->scl_frequency > 400 * 1000) { 640 dev_warn(&pdev->dev, "invalid SCL frequency specified.\n"); 641 dev_warn(&pdev->dev, "using default SCL frequency: %d\n", 642 DEFAULT_SCL_RATE); 643 i2c->scl_frequency = DEFAULT_SCL_RATE; 644 } 645 646 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); 647 i2c->adap.owner = THIS_MODULE; 648 i2c->adap.algo = &rk3x_i2c_algorithm; 649 i2c->adap.retries = 3; 650 i2c->adap.dev.of_node = np; 651 i2c->adap.algo_data = i2c; 652 i2c->adap.dev.parent = &pdev->dev; 653 654 i2c->dev = &pdev->dev; 655 656 spin_lock_init(&i2c->lock); 657 init_waitqueue_head(&i2c->wait); 658 659 i2c->clk = devm_clk_get(&pdev->dev, NULL); 660 if (IS_ERR(i2c->clk)) { 661 dev_err(&pdev->dev, "cannot get clock\n"); 662 return PTR_ERR(i2c->clk); 663 } 664 665 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 666 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 667 if (IS_ERR(i2c->regs)) 668 return PTR_ERR(i2c->regs); 669 670 /* Try to set the I2C adapter number from dt */ 671 bus_nr = of_alias_get_id(np, "i2c"); 672 673 /* 674 * Switch to new interface if the SoC also offers the old one. 675 * The control bit is located in the GRF register space. 676 */ 677 if (i2c->soc_data->grf_offset >= 0) { 678 struct regmap *grf; 679 680 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 681 if (IS_ERR(grf)) { 682 dev_err(&pdev->dev, 683 "rk3x-i2c needs 'rockchip,grf' property\n"); 684 return PTR_ERR(grf); 685 } 686 687 if (bus_nr < 0) { 688 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias"); 689 return -EINVAL; 690 } 691 692 /* 27+i: write mask, 11+i: value */ 693 value = BIT(27 + bus_nr) | BIT(11 + bus_nr); 694 695 ret = regmap_write(grf, i2c->soc_data->grf_offset, value); 696 if (ret != 0) { 697 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret); 698 return ret; 699 } 700 } 701 702 /* IRQ setup */ 703 irq = platform_get_irq(pdev, 0); 704 if (irq < 0) { 705 dev_err(&pdev->dev, "cannot find rk3x IRQ\n"); 706 return irq; 707 } 708 709 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq, 710 0, dev_name(&pdev->dev), i2c); 711 if (ret < 0) { 712 dev_err(&pdev->dev, "cannot request IRQ\n"); 713 return ret; 714 } 715 716 platform_set_drvdata(pdev, i2c); 717 718 ret = clk_prepare(i2c->clk); 719 if (ret < 0) { 720 dev_err(&pdev->dev, "Could not prepare clock\n"); 721 return ret; 722 } 723 724 ret = i2c_add_adapter(&i2c->adap); 725 if (ret < 0) { 726 dev_err(&pdev->dev, "Could not register adapter\n"); 727 goto err_clk; 728 } 729 730 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs); 731 732 return 0; 733 734 err_clk: 735 clk_unprepare(i2c->clk); 736 return ret; 737 } 738 739 static int rk3x_i2c_remove(struct platform_device *pdev) 740 { 741 struct rk3x_i2c *i2c = platform_get_drvdata(pdev); 742 743 i2c_del_adapter(&i2c->adap); 744 clk_unprepare(i2c->clk); 745 746 return 0; 747 } 748 749 static struct platform_driver rk3x_i2c_driver = { 750 .probe = rk3x_i2c_probe, 751 .remove = rk3x_i2c_remove, 752 .driver = { 753 .owner = THIS_MODULE, 754 .name = "rk3x-i2c", 755 .of_match_table = rk3x_i2c_match, 756 }, 757 }; 758 759 module_platform_driver(rk3x_i2c_driver); 760 761 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver"); 762 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>"); 763 MODULE_LICENSE("GPL v2"); 764