1 /* 2 * Driver for I2C adapter in Rockchip RK3xxx SoC 3 * 4 * Max Schwarz <max.schwarz@online.de> 5 * based on the patches by Rockchip Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/platform_device.h> 19 #include <linux/io.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/spinlock.h> 23 #include <linux/clk.h> 24 #include <linux/wait.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/regmap.h> 27 #include <linux/math64.h> 28 29 30 /* Register Map */ 31 #define REG_CON 0x00 /* control register */ 32 #define REG_CLKDIV 0x04 /* clock divisor register */ 33 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */ 34 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */ 35 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */ 36 #define REG_MRXCNT 0x14 /* number of bytes to be received */ 37 #define REG_IEN 0x18 /* interrupt enable */ 38 #define REG_IPD 0x1c /* interrupt pending */ 39 #define REG_FCNT 0x20 /* finished count */ 40 41 /* Data buffer offsets */ 42 #define TXBUFFER_BASE 0x100 43 #define RXBUFFER_BASE 0x200 44 45 /* REG_CON bits */ 46 #define REG_CON_EN BIT(0) 47 enum { 48 REG_CON_MOD_TX = 0, /* transmit data */ 49 REG_CON_MOD_REGISTER_TX, /* select register and restart */ 50 REG_CON_MOD_RX, /* receive data */ 51 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes 52 * register addr */ 53 }; 54 #define REG_CON_MOD(mod) ((mod) << 1) 55 #define REG_CON_MOD_MASK (BIT(1) | BIT(2)) 56 #define REG_CON_START BIT(3) 57 #define REG_CON_STOP BIT(4) 58 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */ 59 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */ 60 61 #define REG_CON_TUNING_MASK GENMASK(15, 8) 62 63 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8) 64 #define REG_CON_STA_CFG(cfg) ((cfg) << 12) 65 #define REG_CON_STO_CFG(cfg) ((cfg) << 14) 66 67 /* REG_MRXADDR bits */ 68 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */ 69 70 /* REG_IEN/REG_IPD bits */ 71 #define REG_INT_BTF BIT(0) /* a byte was transmitted */ 72 #define REG_INT_BRF BIT(1) /* a byte was received */ 73 #define REG_INT_MBTF BIT(2) /* master data transmit finished */ 74 #define REG_INT_MBRF BIT(3) /* master data receive finished */ 75 #define REG_INT_START BIT(4) /* START condition generated */ 76 #define REG_INT_STOP BIT(5) /* STOP condition generated */ 77 #define REG_INT_NAKRCV BIT(6) /* NACK received */ 78 #define REG_INT_ALL 0x7f 79 80 /* Constants */ 81 #define WAIT_TIMEOUT 1000 /* ms */ 82 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ 83 84 /** 85 * struct i2c_spec_values: 86 * @min_hold_start_ns: min hold time (repeated) START condition 87 * @min_low_ns: min LOW period of the SCL clock 88 * @min_high_ns: min HIGH period of the SCL cloc 89 * @min_setup_start_ns: min set-up time for a repeated START conditio 90 * @max_data_hold_ns: max data hold time 91 * @min_data_setup_ns: min data set-up time 92 * @min_setup_stop_ns: min set-up time for STOP condition 93 * @min_hold_buffer_ns: min bus free time between a STOP and 94 * START condition 95 */ 96 struct i2c_spec_values { 97 unsigned long min_hold_start_ns; 98 unsigned long min_low_ns; 99 unsigned long min_high_ns; 100 unsigned long min_setup_start_ns; 101 unsigned long max_data_hold_ns; 102 unsigned long min_data_setup_ns; 103 unsigned long min_setup_stop_ns; 104 unsigned long min_hold_buffer_ns; 105 }; 106 107 static const struct i2c_spec_values standard_mode_spec = { 108 .min_hold_start_ns = 4000, 109 .min_low_ns = 4700, 110 .min_high_ns = 4000, 111 .min_setup_start_ns = 4700, 112 .max_data_hold_ns = 3450, 113 .min_data_setup_ns = 250, 114 .min_setup_stop_ns = 4000, 115 .min_hold_buffer_ns = 4700, 116 }; 117 118 static const struct i2c_spec_values fast_mode_spec = { 119 .min_hold_start_ns = 600, 120 .min_low_ns = 1300, 121 .min_high_ns = 600, 122 .min_setup_start_ns = 600, 123 .max_data_hold_ns = 900, 124 .min_data_setup_ns = 100, 125 .min_setup_stop_ns = 600, 126 .min_hold_buffer_ns = 1300, 127 }; 128 129 static const struct i2c_spec_values fast_mode_plus_spec = { 130 .min_hold_start_ns = 260, 131 .min_low_ns = 500, 132 .min_high_ns = 260, 133 .min_setup_start_ns = 260, 134 .max_data_hold_ns = 400, 135 .min_data_setup_ns = 50, 136 .min_setup_stop_ns = 260, 137 .min_hold_buffer_ns = 500, 138 }; 139 140 /** 141 * struct rk3x_i2c_calced_timings: 142 * @div_low: Divider output for low 143 * @div_high: Divider output for high 144 * @tuning: Used to adjust setup/hold data time, 145 * setup/hold start time and setup stop time for 146 * v1's calc_timings, the tuning should all be 0 147 * for old hardware anyone using v0's calc_timings. 148 */ 149 struct rk3x_i2c_calced_timings { 150 unsigned long div_low; 151 unsigned long div_high; 152 unsigned int tuning; 153 }; 154 155 enum rk3x_i2c_state { 156 STATE_IDLE, 157 STATE_START, 158 STATE_READ, 159 STATE_WRITE, 160 STATE_STOP 161 }; 162 163 /** 164 * @grf_offset: offset inside the grf regmap for setting the i2c type 165 * @calc_timings: Callback function for i2c timing information calculated 166 */ 167 struct rk3x_i2c_soc_data { 168 int grf_offset; 169 int (*calc_timings)(unsigned long, struct i2c_timings *, 170 struct rk3x_i2c_calced_timings *); 171 }; 172 173 /** 174 * struct rk3x_i2c - private data of the controller 175 * @adap: corresponding I2C adapter 176 * @dev: device for this controller 177 * @soc_data: related soc data struct 178 * @regs: virtual memory area 179 * @clk: function clk for rk3399 or function & Bus clks for others 180 * @pclk: Bus clk for rk3399 181 * @clk_rate_nb: i2c clk rate change notify 182 * @t: I2C known timing information 183 * @lock: spinlock for the i2c bus 184 * @wait: the waitqueue to wait for i2c transfer 185 * @busy: the condition for the event to wait for 186 * @msg: current i2c message 187 * @addr: addr of i2c slave device 188 * @mode: mode of i2c transfer 189 * @is_last_msg: flag determines whether it is the last msg in this transfer 190 * @state: state of i2c transfer 191 * @processed: byte length which has been send or received 192 * @error: error code for i2c transfer 193 */ 194 struct rk3x_i2c { 195 struct i2c_adapter adap; 196 struct device *dev; 197 struct rk3x_i2c_soc_data *soc_data; 198 199 /* Hardware resources */ 200 void __iomem *regs; 201 struct clk *clk; 202 struct clk *pclk; 203 struct notifier_block clk_rate_nb; 204 205 /* Settings */ 206 struct i2c_timings t; 207 208 /* Synchronization & notification */ 209 spinlock_t lock; 210 wait_queue_head_t wait; 211 bool busy; 212 213 /* Current message */ 214 struct i2c_msg *msg; 215 u8 addr; 216 unsigned int mode; 217 bool is_last_msg; 218 219 /* I2C state machine */ 220 enum rk3x_i2c_state state; 221 unsigned int processed; 222 int error; 223 }; 224 225 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value, 226 unsigned int offset) 227 { 228 writel(value, i2c->regs + offset); 229 } 230 231 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset) 232 { 233 return readl(i2c->regs + offset); 234 } 235 236 /* Reset all interrupt pending bits */ 237 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c) 238 { 239 i2c_writel(i2c, REG_INT_ALL, REG_IPD); 240 } 241 242 /** 243 * Generate a START condition, which triggers a REG_INT_START interrupt. 244 */ 245 static void rk3x_i2c_start(struct rk3x_i2c *i2c) 246 { 247 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 248 249 i2c_writel(i2c, REG_INT_START, REG_IEN); 250 251 /* enable adapter with correct mode, send START condition */ 252 val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START; 253 254 /* if we want to react to NACK, set ACTACK bit */ 255 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 256 val |= REG_CON_ACTACK; 257 258 i2c_writel(i2c, val, REG_CON); 259 } 260 261 /** 262 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt. 263 * 264 * @error: Error code to return in rk3x_i2c_xfer 265 */ 266 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error) 267 { 268 unsigned int ctrl; 269 270 i2c->processed = 0; 271 i2c->msg = NULL; 272 i2c->error = error; 273 274 if (i2c->is_last_msg) { 275 /* Enable stop interrupt */ 276 i2c_writel(i2c, REG_INT_STOP, REG_IEN); 277 278 i2c->state = STATE_STOP; 279 280 ctrl = i2c_readl(i2c, REG_CON); 281 ctrl |= REG_CON_STOP; 282 i2c_writel(i2c, ctrl, REG_CON); 283 } else { 284 /* Signal rk3x_i2c_xfer to start the next message. */ 285 i2c->busy = false; 286 i2c->state = STATE_IDLE; 287 288 /* 289 * The HW is actually not capable of REPEATED START. But we can 290 * get the intended effect by resetting its internal state 291 * and issuing an ordinary START. 292 */ 293 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 294 i2c_writel(i2c, ctrl, REG_CON); 295 296 /* signal that we are finished with the current msg */ 297 wake_up(&i2c->wait); 298 } 299 } 300 301 /** 302 * Setup a read according to i2c->msg 303 */ 304 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c) 305 { 306 unsigned int len = i2c->msg->len - i2c->processed; 307 u32 con; 308 309 con = i2c_readl(i2c, REG_CON); 310 311 /* 312 * The hw can read up to 32 bytes at a time. If we need more than one 313 * chunk, send an ACK after the last byte of the current chunk. 314 */ 315 if (len > 32) { 316 len = 32; 317 con &= ~REG_CON_LASTACK; 318 } else { 319 con |= REG_CON_LASTACK; 320 } 321 322 /* make sure we are in plain RX mode if we read a second chunk */ 323 if (i2c->processed != 0) { 324 con &= ~REG_CON_MOD_MASK; 325 con |= REG_CON_MOD(REG_CON_MOD_RX); 326 } 327 328 i2c_writel(i2c, con, REG_CON); 329 i2c_writel(i2c, len, REG_MRXCNT); 330 } 331 332 /** 333 * Fill the transmit buffer with data from i2c->msg 334 */ 335 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c) 336 { 337 unsigned int i, j; 338 u32 cnt = 0; 339 u32 val; 340 u8 byte; 341 342 for (i = 0; i < 8; ++i) { 343 val = 0; 344 for (j = 0; j < 4; ++j) { 345 if ((i2c->processed == i2c->msg->len) && (cnt != 0)) 346 break; 347 348 if (i2c->processed == 0 && cnt == 0) 349 byte = (i2c->addr & 0x7f) << 1; 350 else 351 byte = i2c->msg->buf[i2c->processed++]; 352 353 val |= byte << (j * 8); 354 cnt++; 355 } 356 357 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i); 358 359 if (i2c->processed == i2c->msg->len) 360 break; 361 } 362 363 i2c_writel(i2c, cnt, REG_MTXCNT); 364 } 365 366 367 /* IRQ handlers for individual states */ 368 369 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd) 370 { 371 if (!(ipd & REG_INT_START)) { 372 rk3x_i2c_stop(i2c, -EIO); 373 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd); 374 rk3x_i2c_clean_ipd(i2c); 375 return; 376 } 377 378 /* ack interrupt */ 379 i2c_writel(i2c, REG_INT_START, REG_IPD); 380 381 /* disable start bit */ 382 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON); 383 384 /* enable appropriate interrupts and transition */ 385 if (i2c->mode == REG_CON_MOD_TX) { 386 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN); 387 i2c->state = STATE_WRITE; 388 rk3x_i2c_fill_transmit_buf(i2c); 389 } else { 390 /* in any other case, we are going to be reading. */ 391 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN); 392 i2c->state = STATE_READ; 393 rk3x_i2c_prepare_read(i2c); 394 } 395 } 396 397 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd) 398 { 399 if (!(ipd & REG_INT_MBTF)) { 400 rk3x_i2c_stop(i2c, -EIO); 401 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd); 402 rk3x_i2c_clean_ipd(i2c); 403 return; 404 } 405 406 /* ack interrupt */ 407 i2c_writel(i2c, REG_INT_MBTF, REG_IPD); 408 409 /* are we finished? */ 410 if (i2c->processed == i2c->msg->len) 411 rk3x_i2c_stop(i2c, i2c->error); 412 else 413 rk3x_i2c_fill_transmit_buf(i2c); 414 } 415 416 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) 417 { 418 unsigned int i; 419 unsigned int len = i2c->msg->len - i2c->processed; 420 u32 uninitialized_var(val); 421 u8 byte; 422 423 /* we only care for MBRF here. */ 424 if (!(ipd & REG_INT_MBRF)) 425 return; 426 427 /* ack interrupt */ 428 i2c_writel(i2c, REG_INT_MBRF, REG_IPD); 429 430 /* Can only handle a maximum of 32 bytes at a time */ 431 if (len > 32) 432 len = 32; 433 434 /* read the data from receive buffer */ 435 for (i = 0; i < len; ++i) { 436 if (i % 4 == 0) 437 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4); 438 439 byte = (val >> ((i % 4) * 8)) & 0xff; 440 i2c->msg->buf[i2c->processed++] = byte; 441 } 442 443 /* are we finished? */ 444 if (i2c->processed == i2c->msg->len) 445 rk3x_i2c_stop(i2c, i2c->error); 446 else 447 rk3x_i2c_prepare_read(i2c); 448 } 449 450 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd) 451 { 452 unsigned int con; 453 454 if (!(ipd & REG_INT_STOP)) { 455 rk3x_i2c_stop(i2c, -EIO); 456 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd); 457 rk3x_i2c_clean_ipd(i2c); 458 return; 459 } 460 461 /* ack interrupt */ 462 i2c_writel(i2c, REG_INT_STOP, REG_IPD); 463 464 /* disable STOP bit */ 465 con = i2c_readl(i2c, REG_CON); 466 con &= ~REG_CON_STOP; 467 i2c_writel(i2c, con, REG_CON); 468 469 i2c->busy = false; 470 i2c->state = STATE_IDLE; 471 472 /* signal rk3x_i2c_xfer that we are finished */ 473 wake_up(&i2c->wait); 474 } 475 476 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id) 477 { 478 struct rk3x_i2c *i2c = dev_id; 479 unsigned int ipd; 480 481 spin_lock(&i2c->lock); 482 483 ipd = i2c_readl(i2c, REG_IPD); 484 if (i2c->state == STATE_IDLE) { 485 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd); 486 rk3x_i2c_clean_ipd(i2c); 487 goto out; 488 } 489 490 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd); 491 492 /* Clean interrupt bits we don't care about */ 493 ipd &= ~(REG_INT_BRF | REG_INT_BTF); 494 495 if (ipd & REG_INT_NAKRCV) { 496 /* 497 * We got a NACK in the last operation. Depending on whether 498 * IGNORE_NAK is set, we have to stop the operation and report 499 * an error. 500 */ 501 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD); 502 503 ipd &= ~REG_INT_NAKRCV; 504 505 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 506 rk3x_i2c_stop(i2c, -ENXIO); 507 } 508 509 /* is there anything left to handle? */ 510 if ((ipd & REG_INT_ALL) == 0) 511 goto out; 512 513 switch (i2c->state) { 514 case STATE_START: 515 rk3x_i2c_handle_start(i2c, ipd); 516 break; 517 case STATE_WRITE: 518 rk3x_i2c_handle_write(i2c, ipd); 519 break; 520 case STATE_READ: 521 rk3x_i2c_handle_read(i2c, ipd); 522 break; 523 case STATE_STOP: 524 rk3x_i2c_handle_stop(i2c, ipd); 525 break; 526 case STATE_IDLE: 527 break; 528 } 529 530 out: 531 spin_unlock(&i2c->lock); 532 return IRQ_HANDLED; 533 } 534 535 /** 536 * Get timing values of I2C specification 537 * 538 * @speed: Desired SCL frequency 539 * 540 * Returns: Matched i2c spec values. 541 */ 542 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed) 543 { 544 if (speed <= 100000) 545 return &standard_mode_spec; 546 else if (speed <= 400000) 547 return &fast_mode_spec; 548 else 549 return &fast_mode_plus_spec; 550 } 551 552 /** 553 * Calculate divider values for desired SCL frequency 554 * 555 * @clk_rate: I2C input clock rate 556 * @t: Known I2C timing information 557 * @t_calc: Caculated rk3x private timings that would be written into regs 558 * 559 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case 560 * a best-effort divider value is returned in divs. If the target rate is 561 * too high, we silently use the highest possible rate. 562 */ 563 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate, 564 struct i2c_timings *t, 565 struct rk3x_i2c_calced_timings *t_calc) 566 { 567 unsigned long min_low_ns, min_high_ns; 568 unsigned long max_low_ns, min_total_ns; 569 570 unsigned long clk_rate_khz, scl_rate_khz; 571 572 unsigned long min_low_div, min_high_div; 573 unsigned long max_low_div; 574 575 unsigned long min_div_for_hold, min_total_div; 576 unsigned long extra_div, extra_low_div, ideal_low_div; 577 578 unsigned long data_hold_buffer_ns = 50; 579 const struct i2c_spec_values *spec; 580 int ret = 0; 581 582 /* Only support standard-mode and fast-mode */ 583 if (WARN_ON(t->bus_freq_hz > 400000)) 584 t->bus_freq_hz = 400000; 585 586 /* prevent scl_rate_khz from becoming 0 */ 587 if (WARN_ON(t->bus_freq_hz < 1000)) 588 t->bus_freq_hz = 1000; 589 590 /* 591 * min_low_ns: The minimum number of ns we need to hold low to 592 * meet I2C specification, should include fall time. 593 * min_high_ns: The minimum number of ns we need to hold high to 594 * meet I2C specification, should include rise time. 595 * max_low_ns: The maximum number of ns we can hold low to meet 596 * I2C specification. 597 * 598 * Note: max_low_ns should be (maximum data hold time * 2 - buffer) 599 * This is because the i2c host on Rockchip holds the data line 600 * for half the low time. 601 */ 602 spec = rk3x_i2c_get_spec(t->bus_freq_hz); 603 min_high_ns = t->scl_rise_ns + spec->min_high_ns; 604 605 /* 606 * Timings for repeated start: 607 * - controller appears to drop SDA at .875x (7/8) programmed clk high. 608 * - controller appears to keep SCL high for 2x programmed clk high. 609 * 610 * We need to account for those rules in picking our "high" time so 611 * we meet tSU;STA and tHD;STA times. 612 */ 613 min_high_ns = max(min_high_ns, DIV_ROUND_UP( 614 (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875)); 615 min_high_ns = max(min_high_ns, DIV_ROUND_UP( 616 (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns + 617 spec->min_high_ns), 2)); 618 619 min_low_ns = t->scl_fall_ns + spec->min_low_ns; 620 max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns; 621 min_total_ns = min_low_ns + min_high_ns; 622 623 /* Adjust to avoid overflow */ 624 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); 625 scl_rate_khz = t->bus_freq_hz / 1000; 626 627 /* 628 * We need the total div to be >= this number 629 * so we don't clock too fast. 630 */ 631 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); 632 633 /* These are the min dividers needed for min hold times. */ 634 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); 635 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); 636 min_div_for_hold = (min_low_div + min_high_div); 637 638 /* 639 * This is the maximum divider so we don't go over the maximum. 640 * We don't round up here (we round down) since this is a maximum. 641 */ 642 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000); 643 644 if (min_low_div > max_low_div) { 645 WARN_ONCE(true, 646 "Conflicting, min_low_div %lu, max_low_div %lu\n", 647 min_low_div, max_low_div); 648 max_low_div = min_low_div; 649 } 650 651 if (min_div_for_hold > min_total_div) { 652 /* 653 * Time needed to meet hold requirements is important. 654 * Just use that. 655 */ 656 t_calc->div_low = min_low_div; 657 t_calc->div_high = min_high_div; 658 } else { 659 /* 660 * We've got to distribute some time among the low and high 661 * so we don't run too fast. 662 */ 663 extra_div = min_total_div - min_div_for_hold; 664 665 /* 666 * We'll try to split things up perfectly evenly, 667 * biasing slightly towards having a higher div 668 * for low (spend more time low). 669 */ 670 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 671 scl_rate_khz * 8 * min_total_ns); 672 673 /* Don't allow it to go over the maximum */ 674 if (ideal_low_div > max_low_div) 675 ideal_low_div = max_low_div; 676 677 /* 678 * Handle when the ideal low div is going to take up 679 * more than we have. 680 */ 681 if (ideal_low_div > min_low_div + extra_div) 682 ideal_low_div = min_low_div + extra_div; 683 684 /* Give low the "ideal" and give high whatever extra is left */ 685 extra_low_div = ideal_low_div - min_low_div; 686 t_calc->div_low = ideal_low_div; 687 t_calc->div_high = min_high_div + (extra_div - extra_low_div); 688 } 689 690 /* 691 * Adjust to the fact that the hardware has an implicit "+1". 692 * NOTE: Above calculations always produce div_low > 0 and div_high > 0. 693 */ 694 t_calc->div_low--; 695 t_calc->div_high--; 696 697 /* Maximum divider supported by hw is 0xffff */ 698 if (t_calc->div_low > 0xffff) { 699 t_calc->div_low = 0xffff; 700 ret = -EINVAL; 701 } 702 703 if (t_calc->div_high > 0xffff) { 704 t_calc->div_high = 0xffff; 705 ret = -EINVAL; 706 } 707 708 return ret; 709 } 710 711 /** 712 * Calculate timing values for desired SCL frequency 713 * 714 * @clk_rate: I2C input clock rate 715 * @t: Known I2C timing information 716 * @t_calc: Caculated rk3x private timings that would be written into regs 717 * 718 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case 719 * a best-effort divider value is returned in divs. If the target rate is 720 * too high, we silently use the highest possible rate. 721 * The following formulas are v1's method to calculate timings. 722 * 723 * l = divl + 1; 724 * h = divh + 1; 725 * s = sda_update_config + 1; 726 * u = start_setup_config + 1; 727 * p = stop_setup_config + 1; 728 * T = Tclk_i2c; 729 * 730 * tHigh = 8 * h * T; 731 * tLow = 8 * l * T; 732 * 733 * tHD;sda = (l * s + 1) * T; 734 * tSU;sda = [(8 - s) * l + 1] * T; 735 * tI2C = 8 * (l + h) * T; 736 * 737 * tSU;sta = (8h * u + 1) * T; 738 * tHD;sta = [8h * (u + 1) - 1] * T; 739 * tSU;sto = (8h * p + 1) * T; 740 */ 741 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate, 742 struct i2c_timings *t, 743 struct rk3x_i2c_calced_timings *t_calc) 744 { 745 unsigned long min_low_ns, min_high_ns, min_total_ns; 746 unsigned long min_setup_start_ns, min_setup_data_ns; 747 unsigned long min_setup_stop_ns, max_hold_data_ns; 748 749 unsigned long clk_rate_khz, scl_rate_khz; 750 751 unsigned long min_low_div, min_high_div; 752 753 unsigned long min_div_for_hold, min_total_div; 754 unsigned long extra_div, extra_low_div; 755 unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg; 756 757 const struct i2c_spec_values *spec; 758 int ret = 0; 759 760 /* Support standard-mode, fast-mode and fast-mode plus */ 761 if (WARN_ON(t->bus_freq_hz > 1000000)) 762 t->bus_freq_hz = 1000000; 763 764 /* prevent scl_rate_khz from becoming 0 */ 765 if (WARN_ON(t->bus_freq_hz < 1000)) 766 t->bus_freq_hz = 1000; 767 768 /* 769 * min_low_ns: The minimum number of ns we need to hold low to 770 * meet I2C specification, should include fall time. 771 * min_high_ns: The minimum number of ns we need to hold high to 772 * meet I2C specification, should include rise time. 773 */ 774 spec = rk3x_i2c_get_spec(t->bus_freq_hz); 775 776 /* calculate min-divh and min-divl */ 777 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); 778 scl_rate_khz = t->bus_freq_hz / 1000; 779 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); 780 781 min_high_ns = t->scl_rise_ns + spec->min_high_ns; 782 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); 783 784 min_low_ns = t->scl_fall_ns + spec->min_low_ns; 785 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); 786 787 /* 788 * Final divh and divl must be greater than 0, otherwise the 789 * hardware would not output the i2c clk. 790 */ 791 min_high_div = (min_high_div < 1) ? 2 : min_high_div; 792 min_low_div = (min_low_div < 1) ? 2 : min_low_div; 793 794 /* These are the min dividers needed for min hold times. */ 795 min_div_for_hold = (min_low_div + min_high_div); 796 min_total_ns = min_low_ns + min_high_ns; 797 798 /* 799 * This is the maximum divider so we don't go over the maximum. 800 * We don't round up here (we round down) since this is a maximum. 801 */ 802 if (min_div_for_hold >= min_total_div) { 803 /* 804 * Time needed to meet hold requirements is important. 805 * Just use that. 806 */ 807 t_calc->div_low = min_low_div; 808 t_calc->div_high = min_high_div; 809 } else { 810 /* 811 * We've got to distribute some time among the low and high 812 * so we don't run too fast. 813 * We'll try to split things up by the scale of min_low_div and 814 * min_high_div, biasing slightly towards having a higher div 815 * for low (spend more time low). 816 */ 817 extra_div = min_total_div - min_div_for_hold; 818 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div, 819 min_div_for_hold); 820 821 t_calc->div_low = min_low_div + extra_low_div; 822 t_calc->div_high = min_high_div + (extra_div - extra_low_div); 823 } 824 825 /* 826 * calculate sda data hold count by the rules, data_upd_st:3 827 * is a appropriate value to reduce calculated times. 828 */ 829 for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) { 830 max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg 831 * (t_calc->div_low) + 1) 832 * 1000000, clk_rate_khz); 833 min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg) 834 * (t_calc->div_low) + 1) 835 * 1000000, clk_rate_khz); 836 if ((max_hold_data_ns < spec->max_data_hold_ns) && 837 (min_setup_data_ns > spec->min_data_setup_ns)) 838 break; 839 } 840 841 /* calculate setup start config */ 842 min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns; 843 stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns 844 - 1000000, 8 * 1000000 * (t_calc->div_high)); 845 846 /* calculate setup stop config */ 847 min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns; 848 stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns 849 - 1000000, 8 * 1000000 * (t_calc->div_high)); 850 851 t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) | 852 REG_CON_STA_CFG(--stp_sta_cfg) | 853 REG_CON_STO_CFG(--stp_sto_cfg); 854 855 t_calc->div_low--; 856 t_calc->div_high--; 857 858 /* Maximum divider supported by hw is 0xffff */ 859 if (t_calc->div_low > 0xffff) { 860 t_calc->div_low = 0xffff; 861 ret = -EINVAL; 862 } 863 864 if (t_calc->div_high > 0xffff) { 865 t_calc->div_high = 0xffff; 866 ret = -EINVAL; 867 } 868 869 return ret; 870 } 871 872 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate) 873 { 874 struct i2c_timings *t = &i2c->t; 875 struct rk3x_i2c_calced_timings calc; 876 u64 t_low_ns, t_high_ns; 877 unsigned long flags; 878 u32 val; 879 int ret; 880 881 ret = i2c->soc_data->calc_timings(clk_rate, t, &calc); 882 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz); 883 884 clk_enable(i2c->pclk); 885 886 spin_lock_irqsave(&i2c->lock, flags); 887 val = i2c_readl(i2c, REG_CON); 888 val &= ~REG_CON_TUNING_MASK; 889 val |= calc.tuning; 890 i2c_writel(i2c, val, REG_CON); 891 i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff), 892 REG_CLKDIV); 893 spin_unlock_irqrestore(&i2c->lock, flags); 894 895 clk_disable(i2c->pclk); 896 897 t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate); 898 t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000, 899 clk_rate); 900 dev_dbg(i2c->dev, 901 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n", 902 clk_rate / 1000, 903 1000000000 / t->bus_freq_hz, 904 t_low_ns, t_high_ns); 905 } 906 907 /** 908 * rk3x_i2c_clk_notifier_cb - Clock rate change callback 909 * @nb: Pointer to notifier block 910 * @event: Notification reason 911 * @data: Pointer to notification data object 912 * 913 * The callback checks whether a valid bus frequency can be generated after the 914 * change. If so, the change is acknowledged, otherwise the change is aborted. 915 * New dividers are written to the HW in the pre- or post change notification 916 * depending on the scaling direction. 917 * 918 * Code adapted from i2c-cadence.c. 919 * 920 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 921 * to acknowedge the change, NOTIFY_DONE if the notification is 922 * considered irrelevant. 923 */ 924 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 925 event, void *data) 926 { 927 struct clk_notifier_data *ndata = data; 928 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb); 929 struct rk3x_i2c_calced_timings calc; 930 931 switch (event) { 932 case PRE_RATE_CHANGE: 933 /* 934 * Try the calculation (but don't store the result) ahead of 935 * time to see if we need to block the clock change. Timings 936 * shouldn't actually take effect until rk3x_i2c_adapt_div(). 937 */ 938 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t, 939 &calc) != 0) 940 return NOTIFY_STOP; 941 942 /* scale up */ 943 if (ndata->new_rate > ndata->old_rate) 944 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 945 946 return NOTIFY_OK; 947 case POST_RATE_CHANGE: 948 /* scale down */ 949 if (ndata->new_rate < ndata->old_rate) 950 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 951 return NOTIFY_OK; 952 case ABORT_RATE_CHANGE: 953 /* scale up */ 954 if (ndata->new_rate > ndata->old_rate) 955 rk3x_i2c_adapt_div(i2c, ndata->old_rate); 956 return NOTIFY_OK; 957 default: 958 return NOTIFY_DONE; 959 } 960 } 961 962 /** 963 * Setup I2C registers for an I2C operation specified by msgs, num. 964 * 965 * Must be called with i2c->lock held. 966 * 967 * @msgs: I2C msgs to process 968 * @num: Number of msgs 969 * 970 * returns: Number of I2C msgs processed or negative in case of error 971 */ 972 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num) 973 { 974 u32 addr = (msgs[0].addr & 0x7f) << 1; 975 int ret = 0; 976 977 /* 978 * The I2C adapter can issue a small (len < 4) write packet before 979 * reading. This speeds up SMBus-style register reads. 980 * The MRXADDR/MRXRADDR hold the slave address and the slave register 981 * address in this case. 982 */ 983 984 if (num >= 2 && msgs[0].len < 4 && 985 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) { 986 u32 reg_addr = 0; 987 int i; 988 989 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n", 990 addr >> 1); 991 992 /* Fill MRXRADDR with the register address(es) */ 993 for (i = 0; i < msgs[0].len; ++i) { 994 reg_addr |= msgs[0].buf[i] << (i * 8); 995 reg_addr |= REG_MRXADDR_VALID(i); 996 } 997 998 /* msgs[0] is handled by hw. */ 999 i2c->msg = &msgs[1]; 1000 1001 i2c->mode = REG_CON_MOD_REGISTER_TX; 1002 1003 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR); 1004 i2c_writel(i2c, reg_addr, REG_MRXRADDR); 1005 1006 ret = 2; 1007 } else { 1008 /* 1009 * We'll have to do it the boring way and process the msgs 1010 * one-by-one. 1011 */ 1012 1013 if (msgs[0].flags & I2C_M_RD) { 1014 addr |= 1; /* set read bit */ 1015 1016 /* 1017 * We have to transmit the slave addr first. Use 1018 * MOD_REGISTER_TX for that purpose. 1019 */ 1020 i2c->mode = REG_CON_MOD_REGISTER_TX; 1021 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), 1022 REG_MRXADDR); 1023 i2c_writel(i2c, 0, REG_MRXRADDR); 1024 } else { 1025 i2c->mode = REG_CON_MOD_TX; 1026 } 1027 1028 i2c->msg = &msgs[0]; 1029 1030 ret = 1; 1031 } 1032 1033 i2c->addr = msgs[0].addr; 1034 i2c->busy = true; 1035 i2c->state = STATE_START; 1036 i2c->processed = 0; 1037 i2c->error = 0; 1038 1039 rk3x_i2c_clean_ipd(i2c); 1040 1041 return ret; 1042 } 1043 1044 static int rk3x_i2c_xfer(struct i2c_adapter *adap, 1045 struct i2c_msg *msgs, int num) 1046 { 1047 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data; 1048 unsigned long timeout, flags; 1049 u32 val; 1050 int ret = 0; 1051 int i; 1052 1053 spin_lock_irqsave(&i2c->lock, flags); 1054 1055 clk_enable(i2c->clk); 1056 clk_enable(i2c->pclk); 1057 1058 i2c->is_last_msg = false; 1059 1060 /* 1061 * Process msgs. We can handle more than one message at once (see 1062 * rk3x_i2c_setup()). 1063 */ 1064 for (i = 0; i < num; i += ret) { 1065 ret = rk3x_i2c_setup(i2c, msgs + i, num - i); 1066 1067 if (ret < 0) { 1068 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n"); 1069 break; 1070 } 1071 1072 if (i + ret >= num) 1073 i2c->is_last_msg = true; 1074 1075 spin_unlock_irqrestore(&i2c->lock, flags); 1076 1077 rk3x_i2c_start(i2c); 1078 1079 timeout = wait_event_timeout(i2c->wait, !i2c->busy, 1080 msecs_to_jiffies(WAIT_TIMEOUT)); 1081 1082 spin_lock_irqsave(&i2c->lock, flags); 1083 1084 if (timeout == 0) { 1085 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n", 1086 i2c_readl(i2c, REG_IPD), i2c->state); 1087 1088 /* Force a STOP condition without interrupt */ 1089 i2c_writel(i2c, 0, REG_IEN); 1090 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; 1091 val |= REG_CON_EN | REG_CON_STOP; 1092 i2c_writel(i2c, val, REG_CON); 1093 1094 i2c->state = STATE_IDLE; 1095 1096 ret = -ETIMEDOUT; 1097 break; 1098 } 1099 1100 if (i2c->error) { 1101 ret = i2c->error; 1102 break; 1103 } 1104 } 1105 1106 clk_disable(i2c->pclk); 1107 clk_disable(i2c->clk); 1108 1109 spin_unlock_irqrestore(&i2c->lock, flags); 1110 1111 return ret < 0 ? ret : num; 1112 } 1113 1114 static u32 rk3x_i2c_func(struct i2c_adapter *adap) 1115 { 1116 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 1117 } 1118 1119 static const struct i2c_algorithm rk3x_i2c_algorithm = { 1120 .master_xfer = rk3x_i2c_xfer, 1121 .functionality = rk3x_i2c_func, 1122 }; 1123 1124 static const struct rk3x_i2c_soc_data rk3066_soc_data = { 1125 .grf_offset = 0x154, 1126 .calc_timings = rk3x_i2c_v0_calc_timings, 1127 }; 1128 1129 static const struct rk3x_i2c_soc_data rk3188_soc_data = { 1130 .grf_offset = 0x0a4, 1131 .calc_timings = rk3x_i2c_v0_calc_timings, 1132 }; 1133 1134 static const struct rk3x_i2c_soc_data rk3228_soc_data = { 1135 .grf_offset = -1, 1136 .calc_timings = rk3x_i2c_v0_calc_timings, 1137 }; 1138 1139 static const struct rk3x_i2c_soc_data rk3288_soc_data = { 1140 .grf_offset = -1, 1141 .calc_timings = rk3x_i2c_v0_calc_timings, 1142 }; 1143 1144 static const struct rk3x_i2c_soc_data rk3399_soc_data = { 1145 .grf_offset = -1, 1146 .calc_timings = rk3x_i2c_v1_calc_timings, 1147 }; 1148 1149 static const struct of_device_id rk3x_i2c_match[] = { 1150 { 1151 .compatible = "rockchip,rk3066-i2c", 1152 .data = (void *)&rk3066_soc_data 1153 }, 1154 { 1155 .compatible = "rockchip,rk3188-i2c", 1156 .data = (void *)&rk3188_soc_data 1157 }, 1158 { 1159 .compatible = "rockchip,rk3228-i2c", 1160 .data = (void *)&rk3228_soc_data 1161 }, 1162 { 1163 .compatible = "rockchip,rk3288-i2c", 1164 .data = (void *)&rk3288_soc_data 1165 }, 1166 { 1167 .compatible = "rockchip,rk3399-i2c", 1168 .data = (void *)&rk3399_soc_data 1169 }, 1170 {}, 1171 }; 1172 MODULE_DEVICE_TABLE(of, rk3x_i2c_match); 1173 1174 static int rk3x_i2c_probe(struct platform_device *pdev) 1175 { 1176 struct device_node *np = pdev->dev.of_node; 1177 const struct of_device_id *match; 1178 struct rk3x_i2c *i2c; 1179 struct resource *mem; 1180 int ret = 0; 1181 int bus_nr; 1182 u32 value; 1183 int irq; 1184 unsigned long clk_rate; 1185 1186 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL); 1187 if (!i2c) 1188 return -ENOMEM; 1189 1190 match = of_match_node(rk3x_i2c_match, np); 1191 i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data; 1192 1193 /* use common interface to get I2C timing properties */ 1194 i2c_parse_fw_timings(&pdev->dev, &i2c->t, true); 1195 1196 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); 1197 i2c->adap.owner = THIS_MODULE; 1198 i2c->adap.algo = &rk3x_i2c_algorithm; 1199 i2c->adap.retries = 3; 1200 i2c->adap.dev.of_node = np; 1201 i2c->adap.algo_data = i2c; 1202 i2c->adap.dev.parent = &pdev->dev; 1203 1204 i2c->dev = &pdev->dev; 1205 1206 spin_lock_init(&i2c->lock); 1207 init_waitqueue_head(&i2c->wait); 1208 1209 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1210 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 1211 if (IS_ERR(i2c->regs)) 1212 return PTR_ERR(i2c->regs); 1213 1214 /* Try to set the I2C adapter number from dt */ 1215 bus_nr = of_alias_get_id(np, "i2c"); 1216 1217 /* 1218 * Switch to new interface if the SoC also offers the old one. 1219 * The control bit is located in the GRF register space. 1220 */ 1221 if (i2c->soc_data->grf_offset >= 0) { 1222 struct regmap *grf; 1223 1224 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1225 if (IS_ERR(grf)) { 1226 dev_err(&pdev->dev, 1227 "rk3x-i2c needs 'rockchip,grf' property\n"); 1228 return PTR_ERR(grf); 1229 } 1230 1231 if (bus_nr < 0) { 1232 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias"); 1233 return -EINVAL; 1234 } 1235 1236 /* 27+i: write mask, 11+i: value */ 1237 value = BIT(27 + bus_nr) | BIT(11 + bus_nr); 1238 1239 ret = regmap_write(grf, i2c->soc_data->grf_offset, value); 1240 if (ret != 0) { 1241 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret); 1242 return ret; 1243 } 1244 } 1245 1246 /* IRQ setup */ 1247 irq = platform_get_irq(pdev, 0); 1248 if (irq < 0) { 1249 dev_err(&pdev->dev, "cannot find rk3x IRQ\n"); 1250 return irq; 1251 } 1252 1253 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq, 1254 0, dev_name(&pdev->dev), i2c); 1255 if (ret < 0) { 1256 dev_err(&pdev->dev, "cannot request IRQ\n"); 1257 return ret; 1258 } 1259 1260 platform_set_drvdata(pdev, i2c); 1261 1262 if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) { 1263 /* Only one clock to use for bus clock and peripheral clock */ 1264 i2c->clk = devm_clk_get(&pdev->dev, NULL); 1265 i2c->pclk = i2c->clk; 1266 } else { 1267 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1268 i2c->pclk = devm_clk_get(&pdev->dev, "pclk"); 1269 } 1270 1271 if (IS_ERR(i2c->clk)) { 1272 ret = PTR_ERR(i2c->clk); 1273 if (ret != -EPROBE_DEFER) 1274 dev_err(&pdev->dev, "Can't get bus clk: %d\n", ret); 1275 return ret; 1276 } 1277 if (IS_ERR(i2c->pclk)) { 1278 ret = PTR_ERR(i2c->pclk); 1279 if (ret != -EPROBE_DEFER) 1280 dev_err(&pdev->dev, "Can't get periph clk: %d\n", ret); 1281 return ret; 1282 } 1283 1284 ret = clk_prepare(i2c->clk); 1285 if (ret < 0) { 1286 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret); 1287 return ret; 1288 } 1289 ret = clk_prepare(i2c->pclk); 1290 if (ret < 0) { 1291 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret); 1292 goto err_clk; 1293 } 1294 1295 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb; 1296 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb); 1297 if (ret != 0) { 1298 dev_err(&pdev->dev, "Unable to register clock notifier\n"); 1299 goto err_pclk; 1300 } 1301 1302 clk_rate = clk_get_rate(i2c->clk); 1303 rk3x_i2c_adapt_div(i2c, clk_rate); 1304 1305 ret = i2c_add_adapter(&i2c->adap); 1306 if (ret < 0) { 1307 dev_err(&pdev->dev, "Could not register adapter\n"); 1308 goto err_clk_notifier; 1309 } 1310 1311 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs); 1312 1313 return 0; 1314 1315 err_clk_notifier: 1316 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 1317 err_pclk: 1318 clk_unprepare(i2c->pclk); 1319 err_clk: 1320 clk_unprepare(i2c->clk); 1321 return ret; 1322 } 1323 1324 static int rk3x_i2c_remove(struct platform_device *pdev) 1325 { 1326 struct rk3x_i2c *i2c = platform_get_drvdata(pdev); 1327 1328 i2c_del_adapter(&i2c->adap); 1329 1330 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 1331 clk_unprepare(i2c->pclk); 1332 clk_unprepare(i2c->clk); 1333 1334 return 0; 1335 } 1336 1337 static struct platform_driver rk3x_i2c_driver = { 1338 .probe = rk3x_i2c_probe, 1339 .remove = rk3x_i2c_remove, 1340 .driver = { 1341 .name = "rk3x-i2c", 1342 .of_match_table = rk3x_i2c_match, 1343 }, 1344 }; 1345 1346 module_platform_driver(rk3x_i2c_driver); 1347 1348 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver"); 1349 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>"); 1350 MODULE_LICENSE("GPL v2"); 1351