xref: /openbmc/linux/drivers/i2c/busses/i2c-riic.c (revision c67e8ec0) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas RIIC driver
4  *
5  * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
6  * Copyright (C) 2013 Renesas Solutions Corp.
7  */
8 
9 /*
10  * This i2c core has a lot of interrupts, namely 8. We use their chaining as
11  * some kind of state machine.
12  *
13  * 1) The main xfer routine kicks off a transmission by putting the start bit
14  * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
15  * since we need to send the slave address + RW bit in every case.
16  *
17  * 2) TIE sends slave address + RW bit and selects how to continue.
18  *
19  * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
20  * are done, we switch over to the transmission done interrupt (TEIE) and mark
21  * the message as completed (includes sending STOP) there.
22  *
23  * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
24  * needed to start clocking, then we keep receiving until we are done. Note
25  * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
26  * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
27  * message to create the final NACK as sketched in the datasheet. This caused
28  * some subtle races (when byte n was processed and byte n+1 was already
29  * waiting), though, and I started with the safe approach.
30  *
31  * 4) If we got a NACK somewhere, we flag the error and stop the transmission
32  * via NAKIE.
33  *
34  * Also check the comments in the interrupt routines for some gory details.
35  */
36 
37 #include <linux/clk.h>
38 #include <linux/completion.h>
39 #include <linux/err.h>
40 #include <linux/i2c.h>
41 #include <linux/interrupt.h>
42 #include <linux/io.h>
43 #include <linux/module.h>
44 #include <linux/of.h>
45 #include <linux/platform_device.h>
46 
47 #define RIIC_ICCR1	0x00
48 #define RIIC_ICCR2	0x04
49 #define RIIC_ICMR1	0x08
50 #define RIIC_ICMR3	0x10
51 #define RIIC_ICSER	0x18
52 #define RIIC_ICIER	0x1c
53 #define RIIC_ICSR2	0x24
54 #define RIIC_ICBRL	0x34
55 #define RIIC_ICBRH	0x38
56 #define RIIC_ICDRT	0x3c
57 #define RIIC_ICDRR	0x40
58 
59 #define ICCR1_ICE	0x80
60 #define ICCR1_IICRST	0x40
61 #define ICCR1_SOWP	0x10
62 
63 #define ICCR2_BBSY	0x80
64 #define ICCR2_SP	0x08
65 #define ICCR2_RS	0x04
66 #define ICCR2_ST	0x02
67 
68 #define ICMR1_CKS_MASK	0x70
69 #define ICMR1_BCWP	0x08
70 #define ICMR1_CKS(_x)	((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
71 
72 #define ICMR3_RDRFS	0x20
73 #define ICMR3_ACKWP	0x10
74 #define ICMR3_ACKBT	0x08
75 
76 #define ICIER_TIE	0x80
77 #define ICIER_TEIE	0x40
78 #define ICIER_RIE	0x20
79 #define ICIER_NAKIE	0x10
80 #define ICIER_SPIE	0x08
81 
82 #define ICSR2_NACKF	0x10
83 
84 #define ICBR_RESERVED	0xe0 /* Should be 1 on writes */
85 
86 #define RIIC_INIT_MSG	-1
87 
88 struct riic_dev {
89 	void __iomem *base;
90 	u8 *buf;
91 	struct i2c_msg *msg;
92 	int bytes_left;
93 	int err;
94 	int is_last;
95 	struct completion msg_done;
96 	struct i2c_adapter adapter;
97 	struct clk *clk;
98 };
99 
100 struct riic_irq_desc {
101 	int res_num;
102 	irq_handler_t isr;
103 	char *name;
104 };
105 
106 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
107 {
108 	writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
109 }
110 
111 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
112 {
113 	struct riic_dev *riic = i2c_get_adapdata(adap);
114 	unsigned long time_left;
115 	int i, ret;
116 	u8 start_bit;
117 
118 	ret = clk_prepare_enable(riic->clk);
119 	if (ret)
120 		return ret;
121 
122 	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
123 		riic->err = -EBUSY;
124 		goto out;
125 	}
126 
127 	reinit_completion(&riic->msg_done);
128 	riic->err = 0;
129 
130 	writeb(0, riic->base + RIIC_ICSR2);
131 
132 	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
133 		riic->bytes_left = RIIC_INIT_MSG;
134 		riic->buf = msgs[i].buf;
135 		riic->msg = &msgs[i];
136 		riic->is_last = (i == num - 1);
137 
138 		writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
139 
140 		writeb(start_bit, riic->base + RIIC_ICCR2);
141 
142 		time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
143 		if (time_left == 0)
144 			riic->err = -ETIMEDOUT;
145 
146 		if (riic->err)
147 			break;
148 
149 		start_bit = ICCR2_RS;
150 	}
151 
152  out:
153 	clk_disable_unprepare(riic->clk);
154 
155 	return riic->err ?: num;
156 }
157 
158 static irqreturn_t riic_tdre_isr(int irq, void *data)
159 {
160 	struct riic_dev *riic = data;
161 	u8 val;
162 
163 	if (!riic->bytes_left)
164 		return IRQ_NONE;
165 
166 	if (riic->bytes_left == RIIC_INIT_MSG) {
167 		if (riic->msg->flags & I2C_M_RD)
168 			/* On read, switch over to receive interrupt */
169 			riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
170 		else
171 			/* On write, initialize length */
172 			riic->bytes_left = riic->msg->len;
173 
174 		val = i2c_8bit_addr_from_msg(riic->msg);
175 	} else {
176 		val = *riic->buf;
177 		riic->buf++;
178 		riic->bytes_left--;
179 	}
180 
181 	/*
182 	 * Switch to transmission ended interrupt when done. Do check here
183 	 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
184 	 * 0 length then)
185 	 */
186 	if (riic->bytes_left == 0)
187 		riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
188 
189 	/*
190 	 * This acks the TIE interrupt. We get another TIE immediately if our
191 	 * value could be moved to the shadow shift register right away. So
192 	 * this must be after updates to ICIER (where we want to disable TIE)!
193 	 */
194 	writeb(val, riic->base + RIIC_ICDRT);
195 
196 	return IRQ_HANDLED;
197 }
198 
199 static irqreturn_t riic_tend_isr(int irq, void *data)
200 {
201 	struct riic_dev *riic = data;
202 
203 	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
204 		/* We got a NACKIE */
205 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
206 		riic->err = -ENXIO;
207 	} else if (riic->bytes_left) {
208 		return IRQ_NONE;
209 	}
210 
211 	if (riic->is_last || riic->err) {
212 		riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
213 		writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
214 	} else {
215 		/* Transfer is complete, but do not send STOP */
216 		riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
217 		complete(&riic->msg_done);
218 	}
219 
220 	return IRQ_HANDLED;
221 }
222 
223 static irqreturn_t riic_rdrf_isr(int irq, void *data)
224 {
225 	struct riic_dev *riic = data;
226 
227 	if (!riic->bytes_left)
228 		return IRQ_NONE;
229 
230 	if (riic->bytes_left == RIIC_INIT_MSG) {
231 		riic->bytes_left = riic->msg->len;
232 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
233 		return IRQ_HANDLED;
234 	}
235 
236 	if (riic->bytes_left == 1) {
237 		/* STOP must come before we set ACKBT! */
238 		if (riic->is_last) {
239 			riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
240 			writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
241 		}
242 
243 		riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
244 
245 	} else {
246 		riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
247 	}
248 
249 	/* Reading acks the RIE interrupt */
250 	*riic->buf = readb(riic->base + RIIC_ICDRR);
251 	riic->buf++;
252 	riic->bytes_left--;
253 
254 	return IRQ_HANDLED;
255 }
256 
257 static irqreturn_t riic_stop_isr(int irq, void *data)
258 {
259 	struct riic_dev *riic = data;
260 
261 	/* read back registers to confirm writes have fully propagated */
262 	writeb(0, riic->base + RIIC_ICSR2);
263 	readb(riic->base + RIIC_ICSR2);
264 	writeb(0, riic->base + RIIC_ICIER);
265 	readb(riic->base + RIIC_ICIER);
266 
267 	complete(&riic->msg_done);
268 
269 	return IRQ_HANDLED;
270 }
271 
272 static u32 riic_func(struct i2c_adapter *adap)
273 {
274 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
275 }
276 
277 static const struct i2c_algorithm riic_algo = {
278 	.master_xfer	= riic_xfer,
279 	.functionality	= riic_func,
280 };
281 
282 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
283 {
284 	int ret;
285 	unsigned long rate;
286 	int total_ticks, cks, brl, brh;
287 
288 	ret = clk_prepare_enable(riic->clk);
289 	if (ret)
290 		return ret;
291 
292 	if (t->bus_freq_hz > 400000) {
293 		dev_err(&riic->adapter.dev,
294 			"unsupported bus speed (%dHz). 400000 max\n",
295 			t->bus_freq_hz);
296 		clk_disable_unprepare(riic->clk);
297 		return -EINVAL;
298 	}
299 
300 	rate = clk_get_rate(riic->clk);
301 
302 	/*
303 	 * Assume the default register settings:
304 	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
305 	 *  FER.NFE = 1 (noise circuit enabled)
306 	 *  MR3.NF = 0 (1 cycle of noise filtered out)
307 	 *
308 	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
309 	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
310 	 */
311 
312 	/*
313 	 * Determine reference clock rate. We must be able to get the desired
314 	 * frequency with only 62 clock ticks max (31 high, 31 low).
315 	 * Aim for a duty of 60% LOW, 40% HIGH.
316 	 */
317 	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
318 
319 	for (cks = 0; cks < 7; cks++) {
320 		/*
321 		 * 60% low time must be less than BRL + 2 + 1
322 		 * BRL max register value is 0x1F.
323 		 */
324 		brl = ((total_ticks * 6) / 10);
325 		if (brl <= (0x1F + 3))
326 			break;
327 
328 		total_ticks /= 2;
329 		rate /= 2;
330 	}
331 
332 	if (brl > (0x1F + 3)) {
333 		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
334 			(unsigned long)t->bus_freq_hz);
335 		clk_disable_unprepare(riic->clk);
336 		return -EINVAL;
337 	}
338 
339 	brh = total_ticks - brl;
340 
341 	/* Remove automatic clock ticks for sync circuit and NF */
342 	if (cks == 0) {
343 		brl -= 4;
344 		brh -= 4;
345 	} else {
346 		brl -= 3;
347 		brh -= 3;
348 	}
349 
350 	/*
351 	 * Remove clock ticks for rise and fall times. Convert ns to clock
352 	 * ticks.
353 	 */
354 	brl -= t->scl_fall_ns / (1000000000 / rate);
355 	brh -= t->scl_rise_ns / (1000000000 / rate);
356 
357 	/* Adjust for min register values for when SCLE=1 and NFE=1 */
358 	if (brl < 1)
359 		brl = 1;
360 	if (brh < 1)
361 		brh = 1;
362 
363 	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
364 		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
365 		 t->scl_fall_ns / (1000000000 / rate),
366 		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
367 
368 	/* Changing the order of accessing IICRST and ICE may break things! */
369 	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
370 	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
371 
372 	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
373 	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
374 	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
375 
376 	writeb(0, riic->base + RIIC_ICSER);
377 	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
378 
379 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
380 
381 	clk_disable_unprepare(riic->clk);
382 
383 	return 0;
384 }
385 
386 static struct riic_irq_desc riic_irqs[] = {
387 	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
388 	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
389 	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
390 	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
391 	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
392 };
393 
394 static int riic_i2c_probe(struct platform_device *pdev)
395 {
396 	struct riic_dev *riic;
397 	struct i2c_adapter *adap;
398 	struct resource *res;
399 	struct i2c_timings i2c_t;
400 	int i, ret;
401 
402 	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
403 	if (!riic)
404 		return -ENOMEM;
405 
406 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407 	riic->base = devm_ioremap_resource(&pdev->dev, res);
408 	if (IS_ERR(riic->base))
409 		return PTR_ERR(riic->base);
410 
411 	riic->clk = devm_clk_get(&pdev->dev, NULL);
412 	if (IS_ERR(riic->clk)) {
413 		dev_err(&pdev->dev, "missing controller clock");
414 		return PTR_ERR(riic->clk);
415 	}
416 
417 	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
418 		res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
419 		if (!res)
420 			return -ENODEV;
421 
422 		ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
423 					0, riic_irqs[i].name, riic);
424 		if (ret) {
425 			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
426 			return ret;
427 		}
428 	}
429 
430 	adap = &riic->adapter;
431 	i2c_set_adapdata(adap, riic);
432 	strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
433 	adap->owner = THIS_MODULE;
434 	adap->algo = &riic_algo;
435 	adap->dev.parent = &pdev->dev;
436 	adap->dev.of_node = pdev->dev.of_node;
437 
438 	init_completion(&riic->msg_done);
439 
440 	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
441 
442 	ret = riic_init_hw(riic, &i2c_t);
443 	if (ret)
444 		return ret;
445 
446 
447 	ret = i2c_add_adapter(adap);
448 	if (ret)
449 		return ret;
450 
451 	platform_set_drvdata(pdev, riic);
452 
453 	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
454 		 i2c_t.bus_freq_hz);
455 	return 0;
456 }
457 
458 static int riic_i2c_remove(struct platform_device *pdev)
459 {
460 	struct riic_dev *riic = platform_get_drvdata(pdev);
461 
462 	writeb(0, riic->base + RIIC_ICIER);
463 	i2c_del_adapter(&riic->adapter);
464 
465 	return 0;
466 }
467 
468 static const struct of_device_id riic_i2c_dt_ids[] = {
469 	{ .compatible = "renesas,riic-rz" },
470 	{ /* Sentinel */ },
471 };
472 
473 static struct platform_driver riic_i2c_driver = {
474 	.probe		= riic_i2c_probe,
475 	.remove		= riic_i2c_remove,
476 	.driver		= {
477 		.name	= "i2c-riic",
478 		.of_match_table = riic_i2c_dt_ids,
479 	},
480 };
481 
482 module_platform_driver(riic_i2c_driver);
483 
484 MODULE_DESCRIPTION("Renesas RIIC adapter");
485 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
486 MODULE_LICENSE("GPL v2");
487 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
488