xref: /openbmc/linux/drivers/i2c/busses/i2c-riic.c (revision ba61bb17) 
1 /*
2  * Renesas RIIC driver
3  *
4  * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
5  * Copyright (C) 2013 Renesas Solutions Corp.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  */
11 
12 /*
13  * This i2c core has a lot of interrupts, namely 8. We use their chaining as
14  * some kind of state machine.
15  *
16  * 1) The main xfer routine kicks off a transmission by putting the start bit
17  * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
18  * since we need to send the slave address + RW bit in every case.
19  *
20  * 2) TIE sends slave address + RW bit and selects how to continue.
21  *
22  * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
23  * are done, we switch over to the transmission done interrupt (TEIE) and mark
24  * the message as completed (includes sending STOP) there.
25  *
26  * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
27  * needed to start clocking, then we keep receiving until we are done. Note
28  * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
29  * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
30  * message to create the final NACK as sketched in the datasheet. This caused
31  * some subtle races (when byte n was processed and byte n+1 was already
32  * waiting), though, and I started with the safe approach.
33  *
34  * 4) If we got a NACK somewhere, we flag the error and stop the transmission
35  * via NAKIE.
36  *
37  * Also check the comments in the interrupt routines for some gory details.
38  */
39 
40 #include <linux/clk.h>
41 #include <linux/completion.h>
42 #include <linux/err.h>
43 #include <linux/i2c.h>
44 #include <linux/interrupt.h>
45 #include <linux/io.h>
46 #include <linux/module.h>
47 #include <linux/of.h>
48 #include <linux/platform_device.h>
49 
50 #define RIIC_ICCR1	0x00
51 #define RIIC_ICCR2	0x04
52 #define RIIC_ICMR1	0x08
53 #define RIIC_ICMR3	0x10
54 #define RIIC_ICSER	0x18
55 #define RIIC_ICIER	0x1c
56 #define RIIC_ICSR2	0x24
57 #define RIIC_ICBRL	0x34
58 #define RIIC_ICBRH	0x38
59 #define RIIC_ICDRT	0x3c
60 #define RIIC_ICDRR	0x40
61 
62 #define ICCR1_ICE	0x80
63 #define ICCR1_IICRST	0x40
64 #define ICCR1_SOWP	0x10
65 
66 #define ICCR2_BBSY	0x80
67 #define ICCR2_SP	0x08
68 #define ICCR2_RS	0x04
69 #define ICCR2_ST	0x02
70 
71 #define ICMR1_CKS_MASK	0x70
72 #define ICMR1_BCWP	0x08
73 #define ICMR1_CKS(_x)	((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
74 
75 #define ICMR3_RDRFS	0x20
76 #define ICMR3_ACKWP	0x10
77 #define ICMR3_ACKBT	0x08
78 
79 #define ICIER_TIE	0x80
80 #define ICIER_TEIE	0x40
81 #define ICIER_RIE	0x20
82 #define ICIER_NAKIE	0x10
83 #define ICIER_SPIE	0x08
84 
85 #define ICSR2_NACKF	0x10
86 
87 #define ICBR_RESERVED	0xe0 /* Should be 1 on writes */
88 
89 #define RIIC_INIT_MSG	-1
90 
91 struct riic_dev {
92 	void __iomem *base;
93 	u8 *buf;
94 	struct i2c_msg *msg;
95 	int bytes_left;
96 	int err;
97 	int is_last;
98 	struct completion msg_done;
99 	struct i2c_adapter adapter;
100 	struct clk *clk;
101 };
102 
103 struct riic_irq_desc {
104 	int res_num;
105 	irq_handler_t isr;
106 	char *name;
107 };
108 
109 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
110 {
111 	writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
112 }
113 
114 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
115 {
116 	struct riic_dev *riic = i2c_get_adapdata(adap);
117 	unsigned long time_left;
118 	int i, ret;
119 	u8 start_bit;
120 
121 	ret = clk_prepare_enable(riic->clk);
122 	if (ret)
123 		return ret;
124 
125 	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
126 		riic->err = -EBUSY;
127 		goto out;
128 	}
129 
130 	reinit_completion(&riic->msg_done);
131 	riic->err = 0;
132 
133 	writeb(0, riic->base + RIIC_ICSR2);
134 
135 	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
136 		riic->bytes_left = RIIC_INIT_MSG;
137 		riic->buf = msgs[i].buf;
138 		riic->msg = &msgs[i];
139 		riic->is_last = (i == num - 1);
140 
141 		writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
142 
143 		writeb(start_bit, riic->base + RIIC_ICCR2);
144 
145 		time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
146 		if (time_left == 0)
147 			riic->err = -ETIMEDOUT;
148 
149 		if (riic->err)
150 			break;
151 
152 		start_bit = ICCR2_RS;
153 	}
154 
155  out:
156 	clk_disable_unprepare(riic->clk);
157 
158 	return riic->err ?: num;
159 }
160 
161 static irqreturn_t riic_tdre_isr(int irq, void *data)
162 {
163 	struct riic_dev *riic = data;
164 	u8 val;
165 
166 	if (!riic->bytes_left)
167 		return IRQ_NONE;
168 
169 	if (riic->bytes_left == RIIC_INIT_MSG) {
170 		if (riic->msg->flags & I2C_M_RD)
171 			/* On read, switch over to receive interrupt */
172 			riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
173 		else
174 			/* On write, initialize length */
175 			riic->bytes_left = riic->msg->len;
176 
177 		val = i2c_8bit_addr_from_msg(riic->msg);
178 	} else {
179 		val = *riic->buf;
180 		riic->buf++;
181 		riic->bytes_left--;
182 	}
183 
184 	/*
185 	 * Switch to transmission ended interrupt when done. Do check here
186 	 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
187 	 * 0 length then)
188 	 */
189 	if (riic->bytes_left == 0)
190 		riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
191 
192 	/*
193 	 * This acks the TIE interrupt. We get another TIE immediately if our
194 	 * value could be moved to the shadow shift register right away. So
195 	 * this must be after updates to ICIER (where we want to disable TIE)!
196 	 */
197 	writeb(val, riic->base + RIIC_ICDRT);
198 
199 	return IRQ_HANDLED;
200 }
201 
202 static irqreturn_t riic_tend_isr(int irq, void *data)
203 {
204 	struct riic_dev *riic = data;
205 
206 	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
207 		/* We got a NACKIE */
208 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
209 		riic->err = -ENXIO;
210 	} else if (riic->bytes_left) {
211 		return IRQ_NONE;
212 	}
213 
214 	if (riic->is_last || riic->err) {
215 		riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
216 		writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
217 	} else {
218 		/* Transfer is complete, but do not send STOP */
219 		riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
220 		complete(&riic->msg_done);
221 	}
222 
223 	return IRQ_HANDLED;
224 }
225 
226 static irqreturn_t riic_rdrf_isr(int irq, void *data)
227 {
228 	struct riic_dev *riic = data;
229 
230 	if (!riic->bytes_left)
231 		return IRQ_NONE;
232 
233 	if (riic->bytes_left == RIIC_INIT_MSG) {
234 		riic->bytes_left = riic->msg->len;
235 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
236 		return IRQ_HANDLED;
237 	}
238 
239 	if (riic->bytes_left == 1) {
240 		/* STOP must come before we set ACKBT! */
241 		if (riic->is_last) {
242 			riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
243 			writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
244 		}
245 
246 		riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
247 
248 	} else {
249 		riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
250 	}
251 
252 	/* Reading acks the RIE interrupt */
253 	*riic->buf = readb(riic->base + RIIC_ICDRR);
254 	riic->buf++;
255 	riic->bytes_left--;
256 
257 	return IRQ_HANDLED;
258 }
259 
260 static irqreturn_t riic_stop_isr(int irq, void *data)
261 {
262 	struct riic_dev *riic = data;
263 
264 	/* read back registers to confirm writes have fully propagated */
265 	writeb(0, riic->base + RIIC_ICSR2);
266 	readb(riic->base + RIIC_ICSR2);
267 	writeb(0, riic->base + RIIC_ICIER);
268 	readb(riic->base + RIIC_ICIER);
269 
270 	complete(&riic->msg_done);
271 
272 	return IRQ_HANDLED;
273 }
274 
275 static u32 riic_func(struct i2c_adapter *adap)
276 {
277 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
278 }
279 
280 static const struct i2c_algorithm riic_algo = {
281 	.master_xfer	= riic_xfer,
282 	.functionality	= riic_func,
283 };
284 
285 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
286 {
287 	int ret;
288 	unsigned long rate;
289 	int total_ticks, cks, brl, brh;
290 
291 	ret = clk_prepare_enable(riic->clk);
292 	if (ret)
293 		return ret;
294 
295 	if (t->bus_freq_hz > 400000) {
296 		dev_err(&riic->adapter.dev,
297 			"unsupported bus speed (%dHz). 400000 max\n",
298 			t->bus_freq_hz);
299 		clk_disable_unprepare(riic->clk);
300 		return -EINVAL;
301 	}
302 
303 	rate = clk_get_rate(riic->clk);
304 
305 	/*
306 	 * Assume the default register settings:
307 	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
308 	 *  FER.NFE = 1 (noise circuit enabled)
309 	 *  MR3.NF = 0 (1 cycle of noise filtered out)
310 	 *
311 	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
312 	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
313 	 */
314 
315 	/*
316 	 * Determine reference clock rate. We must be able to get the desired
317 	 * frequency with only 62 clock ticks max (31 high, 31 low).
318 	 * Aim for a duty of 60% LOW, 40% HIGH.
319 	 */
320 	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
321 
322 	for (cks = 0; cks < 7; cks++) {
323 		/*
324 		 * 60% low time must be less than BRL + 2 + 1
325 		 * BRL max register value is 0x1F.
326 		 */
327 		brl = ((total_ticks * 6) / 10);
328 		if (brl <= (0x1F + 3))
329 			break;
330 
331 		total_ticks /= 2;
332 		rate /= 2;
333 	}
334 
335 	if (brl > (0x1F + 3)) {
336 		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
337 			(unsigned long)t->bus_freq_hz);
338 		clk_disable_unprepare(riic->clk);
339 		return -EINVAL;
340 	}
341 
342 	brh = total_ticks - brl;
343 
344 	/* Remove automatic clock ticks for sync circuit and NF */
345 	if (cks == 0) {
346 		brl -= 4;
347 		brh -= 4;
348 	} else {
349 		brl -= 3;
350 		brh -= 3;
351 	}
352 
353 	/*
354 	 * Remove clock ticks for rise and fall times. Convert ns to clock
355 	 * ticks.
356 	 */
357 	brl -= t->scl_fall_ns / (1000000000 / rate);
358 	brh -= t->scl_rise_ns / (1000000000 / rate);
359 
360 	/* Adjust for min register values for when SCLE=1 and NFE=1 */
361 	if (brl < 1)
362 		brl = 1;
363 	if (brh < 1)
364 		brh = 1;
365 
366 	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
367 		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
368 		 t->scl_fall_ns / (1000000000 / rate),
369 		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
370 
371 	/* Changing the order of accessing IICRST and ICE may break things! */
372 	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
373 	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
374 
375 	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
376 	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
377 	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
378 
379 	writeb(0, riic->base + RIIC_ICSER);
380 	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
381 
382 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
383 
384 	clk_disable_unprepare(riic->clk);
385 
386 	return 0;
387 }
388 
389 static struct riic_irq_desc riic_irqs[] = {
390 	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
391 	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
392 	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
393 	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
394 	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
395 };
396 
397 static int riic_i2c_probe(struct platform_device *pdev)
398 {
399 	struct riic_dev *riic;
400 	struct i2c_adapter *adap;
401 	struct resource *res;
402 	struct i2c_timings i2c_t;
403 	int i, ret;
404 
405 	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
406 	if (!riic)
407 		return -ENOMEM;
408 
409 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
410 	riic->base = devm_ioremap_resource(&pdev->dev, res);
411 	if (IS_ERR(riic->base))
412 		return PTR_ERR(riic->base);
413 
414 	riic->clk = devm_clk_get(&pdev->dev, NULL);
415 	if (IS_ERR(riic->clk)) {
416 		dev_err(&pdev->dev, "missing controller clock");
417 		return PTR_ERR(riic->clk);
418 	}
419 
420 	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
421 		res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
422 		if (!res)
423 			return -ENODEV;
424 
425 		ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
426 					0, riic_irqs[i].name, riic);
427 		if (ret) {
428 			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
429 			return ret;
430 		}
431 	}
432 
433 	adap = &riic->adapter;
434 	i2c_set_adapdata(adap, riic);
435 	strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
436 	adap->owner = THIS_MODULE;
437 	adap->algo = &riic_algo;
438 	adap->dev.parent = &pdev->dev;
439 	adap->dev.of_node = pdev->dev.of_node;
440 
441 	init_completion(&riic->msg_done);
442 
443 	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
444 
445 	ret = riic_init_hw(riic, &i2c_t);
446 	if (ret)
447 		return ret;
448 
449 
450 	ret = i2c_add_adapter(adap);
451 	if (ret)
452 		return ret;
453 
454 	platform_set_drvdata(pdev, riic);
455 
456 	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
457 		 i2c_t.bus_freq_hz);
458 	return 0;
459 }
460 
461 static int riic_i2c_remove(struct platform_device *pdev)
462 {
463 	struct riic_dev *riic = platform_get_drvdata(pdev);
464 
465 	writeb(0, riic->base + RIIC_ICIER);
466 	i2c_del_adapter(&riic->adapter);
467 
468 	return 0;
469 }
470 
471 static const struct of_device_id riic_i2c_dt_ids[] = {
472 	{ .compatible = "renesas,riic-rz" },
473 	{ /* Sentinel */ },
474 };
475 
476 static struct platform_driver riic_i2c_driver = {
477 	.probe		= riic_i2c_probe,
478 	.remove		= riic_i2c_remove,
479 	.driver		= {
480 		.name	= "i2c-riic",
481 		.of_match_table = riic_i2c_dt_ids,
482 	},
483 };
484 
485 module_platform_driver(riic_i2c_driver);
486 
487 MODULE_DESCRIPTION("Renesas RIIC adapter");
488 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
489 MODULE_LICENSE("GPL v2");
490 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
491