1 /* 2 * Renesas RIIC driver 3 * 4 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com> 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 */ 11 12 /* 13 * This i2c core has a lot of interrupts, namely 8. We use their chaining as 14 * some kind of state machine. 15 * 16 * 1) The main xfer routine kicks off a transmission by putting the start bit 17 * (or repeated start) on the bus and enabling the transmit interrupt (TIE) 18 * since we need to send the slave address + RW bit in every case. 19 * 20 * 2) TIE sends slave address + RW bit and selects how to continue. 21 * 22 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we 23 * are done, we switch over to the transmission done interrupt (TEIE) and mark 24 * the message as completed (includes sending STOP) there. 25 * 26 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is 27 * needed to start clocking, then we keep receiving until we are done. Note 28 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by 29 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a 30 * message to create the final NACK as sketched in the datasheet. This caused 31 * some subtle races (when byte n was processed and byte n+1 was already 32 * waiting), though, and I started with the safe approach. 33 * 34 * 4) If we got a NACK somewhere, we flag the error and stop the transmission 35 * via NAKIE. 36 * 37 * Also check the comments in the interrupt routines for some gory details. 38 */ 39 40 #include <linux/clk.h> 41 #include <linux/completion.h> 42 #include <linux/err.h> 43 #include <linux/i2c.h> 44 #include <linux/interrupt.h> 45 #include <linux/io.h> 46 #include <linux/module.h> 47 #include <linux/of.h> 48 #include <linux/platform_device.h> 49 50 #define RIIC_ICCR1 0x00 51 #define RIIC_ICCR2 0x04 52 #define RIIC_ICMR1 0x08 53 #define RIIC_ICMR3 0x10 54 #define RIIC_ICSER 0x18 55 #define RIIC_ICIER 0x1c 56 #define RIIC_ICSR2 0x24 57 #define RIIC_ICBRL 0x34 58 #define RIIC_ICBRH 0x38 59 #define RIIC_ICDRT 0x3c 60 #define RIIC_ICDRR 0x40 61 62 #define ICCR1_ICE 0x80 63 #define ICCR1_IICRST 0x40 64 #define ICCR1_SOWP 0x10 65 66 #define ICCR2_BBSY 0x80 67 #define ICCR2_SP 0x08 68 #define ICCR2_RS 0x04 69 #define ICCR2_ST 0x02 70 71 #define ICMR1_CKS_MASK 0x70 72 #define ICMR1_BCWP 0x08 73 #define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP) 74 75 #define ICMR3_RDRFS 0x20 76 #define ICMR3_ACKWP 0x10 77 #define ICMR3_ACKBT 0x08 78 79 #define ICIER_TIE 0x80 80 #define ICIER_TEIE 0x40 81 #define ICIER_RIE 0x20 82 #define ICIER_NAKIE 0x10 83 #define ICIER_SPIE 0x08 84 85 #define ICSR2_NACKF 0x10 86 87 /* ICBRx (@ PCLK 33MHz) */ 88 #define ICBR_RESERVED 0xe0 /* Should be 1 on writes */ 89 #define ICBRL_SP100K (19 | ICBR_RESERVED) 90 #define ICBRH_SP100K (16 | ICBR_RESERVED) 91 #define ICBRL_SP400K (21 | ICBR_RESERVED) 92 #define ICBRH_SP400K (9 | ICBR_RESERVED) 93 94 #define RIIC_INIT_MSG -1 95 96 struct riic_dev { 97 void __iomem *base; 98 u8 *buf; 99 struct i2c_msg *msg; 100 int bytes_left; 101 int err; 102 int is_last; 103 struct completion msg_done; 104 struct i2c_adapter adapter; 105 struct clk *clk; 106 }; 107 108 struct riic_irq_desc { 109 int res_num; 110 irq_handler_t isr; 111 char *name; 112 }; 113 114 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg) 115 { 116 writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg); 117 } 118 119 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 120 { 121 struct riic_dev *riic = i2c_get_adapdata(adap); 122 unsigned long time_left; 123 int i, ret; 124 u8 start_bit; 125 126 ret = clk_prepare_enable(riic->clk); 127 if (ret) 128 return ret; 129 130 if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) { 131 riic->err = -EBUSY; 132 goto out; 133 } 134 135 reinit_completion(&riic->msg_done); 136 riic->err = 0; 137 138 writeb(0, riic->base + RIIC_ICSR2); 139 140 for (i = 0, start_bit = ICCR2_ST; i < num; i++) { 141 riic->bytes_left = RIIC_INIT_MSG; 142 riic->buf = msgs[i].buf; 143 riic->msg = &msgs[i]; 144 riic->is_last = (i == num - 1); 145 146 writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER); 147 148 writeb(start_bit, riic->base + RIIC_ICCR2); 149 150 time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout); 151 if (time_left == 0) 152 riic->err = -ETIMEDOUT; 153 154 if (riic->err) 155 break; 156 157 start_bit = ICCR2_RS; 158 } 159 160 out: 161 clk_disable_unprepare(riic->clk); 162 163 return riic->err ?: num; 164 } 165 166 static irqreturn_t riic_tdre_isr(int irq, void *data) 167 { 168 struct riic_dev *riic = data; 169 u8 val; 170 171 if (!riic->bytes_left) 172 return IRQ_NONE; 173 174 if (riic->bytes_left == RIIC_INIT_MSG) { 175 val = !!(riic->msg->flags & I2C_M_RD); 176 if (val) 177 /* On read, switch over to receive interrupt */ 178 riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER); 179 else 180 /* On write, initialize length */ 181 riic->bytes_left = riic->msg->len; 182 183 val |= (riic->msg->addr << 1); 184 } else { 185 val = *riic->buf; 186 riic->buf++; 187 riic->bytes_left--; 188 } 189 190 /* 191 * Switch to transmission ended interrupt when done. Do check here 192 * after bytes_left was initialized to support SMBUS_QUICK (new msg has 193 * 0 length then) 194 */ 195 if (riic->bytes_left == 0) 196 riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER); 197 198 /* 199 * This acks the TIE interrupt. We get another TIE immediately if our 200 * value could be moved to the shadow shift register right away. So 201 * this must be after updates to ICIER (where we want to disable TIE)! 202 */ 203 writeb(val, riic->base + RIIC_ICDRT); 204 205 return IRQ_HANDLED; 206 } 207 208 static irqreturn_t riic_tend_isr(int irq, void *data) 209 { 210 struct riic_dev *riic = data; 211 212 if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) { 213 /* We got a NACKIE */ 214 readb(riic->base + RIIC_ICDRR); /* dummy read */ 215 riic->err = -ENXIO; 216 } else if (riic->bytes_left) { 217 return IRQ_NONE; 218 } 219 220 if (riic->is_last || riic->err) { 221 riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER); 222 writeb(ICCR2_SP, riic->base + RIIC_ICCR2); 223 } else { 224 /* Transfer is complete, but do not send STOP */ 225 riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER); 226 complete(&riic->msg_done); 227 } 228 229 return IRQ_HANDLED; 230 } 231 232 static irqreturn_t riic_rdrf_isr(int irq, void *data) 233 { 234 struct riic_dev *riic = data; 235 236 if (!riic->bytes_left) 237 return IRQ_NONE; 238 239 if (riic->bytes_left == RIIC_INIT_MSG) { 240 riic->bytes_left = riic->msg->len; 241 readb(riic->base + RIIC_ICDRR); /* dummy read */ 242 return IRQ_HANDLED; 243 } 244 245 if (riic->bytes_left == 1) { 246 /* STOP must come before we set ACKBT! */ 247 if (riic->is_last) { 248 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER); 249 writeb(ICCR2_SP, riic->base + RIIC_ICCR2); 250 } 251 252 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3); 253 254 } else { 255 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3); 256 } 257 258 /* Reading acks the RIE interrupt */ 259 *riic->buf = readb(riic->base + RIIC_ICDRR); 260 riic->buf++; 261 riic->bytes_left--; 262 263 return IRQ_HANDLED; 264 } 265 266 static irqreturn_t riic_stop_isr(int irq, void *data) 267 { 268 struct riic_dev *riic = data; 269 270 /* read back registers to confirm writes have fully propagated */ 271 writeb(0, riic->base + RIIC_ICSR2); 272 readb(riic->base + RIIC_ICSR2); 273 writeb(0, riic->base + RIIC_ICIER); 274 readb(riic->base + RIIC_ICIER); 275 276 complete(&riic->msg_done); 277 278 return IRQ_HANDLED; 279 } 280 281 static u32 riic_func(struct i2c_adapter *adap) 282 { 283 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 284 } 285 286 static const struct i2c_algorithm riic_algo = { 287 .master_xfer = riic_xfer, 288 .functionality = riic_func, 289 }; 290 291 static int riic_init_hw(struct riic_dev *riic, u32 spd) 292 { 293 int ret; 294 unsigned long rate; 295 296 ret = clk_prepare_enable(riic->clk); 297 if (ret) 298 return ret; 299 300 /* 301 * TODO: Implement formula to calculate the timing values depending on 302 * variable parent clock rate and arbitrary bus speed 303 */ 304 rate = clk_get_rate(riic->clk); 305 if (rate != 33325000) { 306 dev_err(&riic->adapter.dev, 307 "invalid parent clk (%lu). Must be 33325000Hz\n", rate); 308 clk_disable_unprepare(riic->clk); 309 return -EINVAL; 310 } 311 312 /* Changing the order of accessing IICRST and ICE may break things! */ 313 writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1); 314 riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1); 315 316 switch (spd) { 317 case 100000: 318 writeb(ICMR1_CKS(3), riic->base + RIIC_ICMR1); 319 writeb(ICBRH_SP100K, riic->base + RIIC_ICBRH); 320 writeb(ICBRL_SP100K, riic->base + RIIC_ICBRL); 321 break; 322 case 400000: 323 writeb(ICMR1_CKS(1), riic->base + RIIC_ICMR1); 324 writeb(ICBRH_SP400K, riic->base + RIIC_ICBRH); 325 writeb(ICBRL_SP400K, riic->base + RIIC_ICBRL); 326 break; 327 default: 328 dev_err(&riic->adapter.dev, 329 "unsupported bus speed (%dHz). Use 100000 or 400000\n", spd); 330 clk_disable_unprepare(riic->clk); 331 return -EINVAL; 332 } 333 334 writeb(0, riic->base + RIIC_ICSER); 335 writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3); 336 337 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); 338 339 clk_disable_unprepare(riic->clk); 340 341 return 0; 342 } 343 344 static struct riic_irq_desc riic_irqs[] = { 345 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" }, 346 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" }, 347 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" }, 348 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" }, 349 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" }, 350 }; 351 352 static int riic_i2c_probe(struct platform_device *pdev) 353 { 354 struct device_node *np = pdev->dev.of_node; 355 struct riic_dev *riic; 356 struct i2c_adapter *adap; 357 struct resource *res; 358 u32 bus_rate = 0; 359 int i, ret; 360 361 riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL); 362 if (!riic) 363 return -ENOMEM; 364 365 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 366 riic->base = devm_ioremap_resource(&pdev->dev, res); 367 if (IS_ERR(riic->base)) 368 return PTR_ERR(riic->base); 369 370 riic->clk = devm_clk_get(&pdev->dev, NULL); 371 if (IS_ERR(riic->clk)) { 372 dev_err(&pdev->dev, "missing controller clock"); 373 return PTR_ERR(riic->clk); 374 } 375 376 for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) { 377 res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num); 378 if (!res) 379 return -ENODEV; 380 381 ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr, 382 0, riic_irqs[i].name, riic); 383 if (ret) { 384 dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name); 385 return ret; 386 } 387 } 388 389 adap = &riic->adapter; 390 i2c_set_adapdata(adap, riic); 391 strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); 392 adap->owner = THIS_MODULE; 393 adap->algo = &riic_algo; 394 adap->dev.parent = &pdev->dev; 395 adap->dev.of_node = pdev->dev.of_node; 396 397 init_completion(&riic->msg_done); 398 399 of_property_read_u32(np, "clock-frequency", &bus_rate); 400 ret = riic_init_hw(riic, bus_rate); 401 if (ret) 402 return ret; 403 404 405 ret = i2c_add_adapter(adap); 406 if (ret) 407 return ret; 408 409 platform_set_drvdata(pdev, riic); 410 411 dev_info(&pdev->dev, "registered with %dHz bus speed\n", bus_rate); 412 return 0; 413 } 414 415 static int riic_i2c_remove(struct platform_device *pdev) 416 { 417 struct riic_dev *riic = platform_get_drvdata(pdev); 418 419 writeb(0, riic->base + RIIC_ICIER); 420 i2c_del_adapter(&riic->adapter); 421 422 return 0; 423 } 424 425 static const struct of_device_id riic_i2c_dt_ids[] = { 426 { .compatible = "renesas,riic-rz" }, 427 { /* Sentinel */ }, 428 }; 429 430 static struct platform_driver riic_i2c_driver = { 431 .probe = riic_i2c_probe, 432 .remove = riic_i2c_remove, 433 .driver = { 434 .name = "i2c-riic", 435 .of_match_table = riic_i2c_dt_ids, 436 }, 437 }; 438 439 module_platform_driver(riic_i2c_driver); 440 441 MODULE_DESCRIPTION("Renesas RIIC adapter"); 442 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>"); 443 MODULE_LICENSE("GPL v2"); 444 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids); 445