xref: /openbmc/linux/drivers/i2c/busses/i2c-riic.c (revision 60772e48) 
1 /*
2  * Renesas RIIC driver
3  *
4  * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
5  * Copyright (C) 2013 Renesas Solutions Corp.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  */
11 
12 /*
13  * This i2c core has a lot of interrupts, namely 8. We use their chaining as
14  * some kind of state machine.
15  *
16  * 1) The main xfer routine kicks off a transmission by putting the start bit
17  * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
18  * since we need to send the slave address + RW bit in every case.
19  *
20  * 2) TIE sends slave address + RW bit and selects how to continue.
21  *
22  * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
23  * are done, we switch over to the transmission done interrupt (TEIE) and mark
24  * the message as completed (includes sending STOP) there.
25  *
26  * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
27  * needed to start clocking, then we keep receiving until we are done. Note
28  * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
29  * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
30  * message to create the final NACK as sketched in the datasheet. This caused
31  * some subtle races (when byte n was processed and byte n+1 was already
32  * waiting), though, and I started with the safe approach.
33  *
34  * 4) If we got a NACK somewhere, we flag the error and stop the transmission
35  * via NAKIE.
36  *
37  * Also check the comments in the interrupt routines for some gory details.
38  */
39 
40 #include <linux/clk.h>
41 #include <linux/completion.h>
42 #include <linux/err.h>
43 #include <linux/i2c.h>
44 #include <linux/interrupt.h>
45 #include <linux/io.h>
46 #include <linux/module.h>
47 #include <linux/of.h>
48 #include <linux/platform_device.h>
49 
50 #define RIIC_ICCR1	0x00
51 #define RIIC_ICCR2	0x04
52 #define RIIC_ICMR1	0x08
53 #define RIIC_ICMR3	0x10
54 #define RIIC_ICSER	0x18
55 #define RIIC_ICIER	0x1c
56 #define RIIC_ICSR2	0x24
57 #define RIIC_ICBRL	0x34
58 #define RIIC_ICBRH	0x38
59 #define RIIC_ICDRT	0x3c
60 #define RIIC_ICDRR	0x40
61 
62 #define ICCR1_ICE	0x80
63 #define ICCR1_IICRST	0x40
64 #define ICCR1_SOWP	0x10
65 
66 #define ICCR2_BBSY	0x80
67 #define ICCR2_SP	0x08
68 #define ICCR2_RS	0x04
69 #define ICCR2_ST	0x02
70 
71 #define ICMR1_CKS_MASK	0x70
72 #define ICMR1_BCWP	0x08
73 #define ICMR1_CKS(_x)	((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
74 
75 #define ICMR3_RDRFS	0x20
76 #define ICMR3_ACKWP	0x10
77 #define ICMR3_ACKBT	0x08
78 
79 #define ICIER_TIE	0x80
80 #define ICIER_TEIE	0x40
81 #define ICIER_RIE	0x20
82 #define ICIER_NAKIE	0x10
83 #define ICIER_SPIE	0x08
84 
85 #define ICSR2_NACKF	0x10
86 
87 #define ICBR_RESERVED	0xe0 /* Should be 1 on writes */
88 
89 #define RIIC_INIT_MSG	-1
90 
91 struct riic_dev {
92 	void __iomem *base;
93 	u8 *buf;
94 	struct i2c_msg *msg;
95 	int bytes_left;
96 	int err;
97 	int is_last;
98 	struct completion msg_done;
99 	struct i2c_adapter adapter;
100 	struct clk *clk;
101 };
102 
103 struct riic_irq_desc {
104 	int res_num;
105 	irq_handler_t isr;
106 	char *name;
107 };
108 
109 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
110 {
111 	writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
112 }
113 
114 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
115 {
116 	struct riic_dev *riic = i2c_get_adapdata(adap);
117 	unsigned long time_left;
118 	int i, ret;
119 	u8 start_bit;
120 
121 	ret = clk_prepare_enable(riic->clk);
122 	if (ret)
123 		return ret;
124 
125 	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
126 		riic->err = -EBUSY;
127 		goto out;
128 	}
129 
130 	reinit_completion(&riic->msg_done);
131 	riic->err = 0;
132 
133 	writeb(0, riic->base + RIIC_ICSR2);
134 
135 	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
136 		riic->bytes_left = RIIC_INIT_MSG;
137 		riic->buf = msgs[i].buf;
138 		riic->msg = &msgs[i];
139 		riic->is_last = (i == num - 1);
140 
141 		writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
142 
143 		writeb(start_bit, riic->base + RIIC_ICCR2);
144 
145 		time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
146 		if (time_left == 0)
147 			riic->err = -ETIMEDOUT;
148 
149 		if (riic->err)
150 			break;
151 
152 		start_bit = ICCR2_RS;
153 	}
154 
155  out:
156 	clk_disable_unprepare(riic->clk);
157 
158 	return riic->err ?: num;
159 }
160 
161 static irqreturn_t riic_tdre_isr(int irq, void *data)
162 {
163 	struct riic_dev *riic = data;
164 	u8 val;
165 
166 	if (!riic->bytes_left)
167 		return IRQ_NONE;
168 
169 	if (riic->bytes_left == RIIC_INIT_MSG) {
170 		val = !!(riic->msg->flags & I2C_M_RD);
171 		if (val)
172 			/* On read, switch over to receive interrupt */
173 			riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
174 		else
175 			/* On write, initialize length */
176 			riic->bytes_left = riic->msg->len;
177 
178 		val |= (riic->msg->addr << 1);
179 	} else {
180 		val = *riic->buf;
181 		riic->buf++;
182 		riic->bytes_left--;
183 	}
184 
185 	/*
186 	 * Switch to transmission ended interrupt when done. Do check here
187 	 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
188 	 * 0 length then)
189 	 */
190 	if (riic->bytes_left == 0)
191 		riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
192 
193 	/*
194 	 * This acks the TIE interrupt. We get another TIE immediately if our
195 	 * value could be moved to the shadow shift register right away. So
196 	 * this must be after updates to ICIER (where we want to disable TIE)!
197 	 */
198 	writeb(val, riic->base + RIIC_ICDRT);
199 
200 	return IRQ_HANDLED;
201 }
202 
203 static irqreturn_t riic_tend_isr(int irq, void *data)
204 {
205 	struct riic_dev *riic = data;
206 
207 	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
208 		/* We got a NACKIE */
209 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
210 		riic->err = -ENXIO;
211 	} else if (riic->bytes_left) {
212 		return IRQ_NONE;
213 	}
214 
215 	if (riic->is_last || riic->err) {
216 		riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
217 		writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
218 	} else {
219 		/* Transfer is complete, but do not send STOP */
220 		riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
221 		complete(&riic->msg_done);
222 	}
223 
224 	return IRQ_HANDLED;
225 }
226 
227 static irqreturn_t riic_rdrf_isr(int irq, void *data)
228 {
229 	struct riic_dev *riic = data;
230 
231 	if (!riic->bytes_left)
232 		return IRQ_NONE;
233 
234 	if (riic->bytes_left == RIIC_INIT_MSG) {
235 		riic->bytes_left = riic->msg->len;
236 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
237 		return IRQ_HANDLED;
238 	}
239 
240 	if (riic->bytes_left == 1) {
241 		/* STOP must come before we set ACKBT! */
242 		if (riic->is_last) {
243 			riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
244 			writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
245 		}
246 
247 		riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
248 
249 	} else {
250 		riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
251 	}
252 
253 	/* Reading acks the RIE interrupt */
254 	*riic->buf = readb(riic->base + RIIC_ICDRR);
255 	riic->buf++;
256 	riic->bytes_left--;
257 
258 	return IRQ_HANDLED;
259 }
260 
261 static irqreturn_t riic_stop_isr(int irq, void *data)
262 {
263 	struct riic_dev *riic = data;
264 
265 	/* read back registers to confirm writes have fully propagated */
266 	writeb(0, riic->base + RIIC_ICSR2);
267 	readb(riic->base + RIIC_ICSR2);
268 	writeb(0, riic->base + RIIC_ICIER);
269 	readb(riic->base + RIIC_ICIER);
270 
271 	complete(&riic->msg_done);
272 
273 	return IRQ_HANDLED;
274 }
275 
276 static u32 riic_func(struct i2c_adapter *adap)
277 {
278 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
279 }
280 
281 static const struct i2c_algorithm riic_algo = {
282 	.master_xfer	= riic_xfer,
283 	.functionality	= riic_func,
284 };
285 
286 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
287 {
288 	int ret;
289 	unsigned long rate;
290 	int total_ticks, cks, brl, brh;
291 
292 	ret = clk_prepare_enable(riic->clk);
293 	if (ret)
294 		return ret;
295 
296 	if (t->bus_freq_hz > 400000) {
297 		dev_err(&riic->adapter.dev,
298 			"unsupported bus speed (%dHz). 400000 max\n",
299 			t->bus_freq_hz);
300 		clk_disable_unprepare(riic->clk);
301 		return -EINVAL;
302 	}
303 
304 	rate = clk_get_rate(riic->clk);
305 
306 	/*
307 	 * Assume the default register settings:
308 	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
309 	 *  FER.NFE = 1 (noise circuit enabled)
310 	 *  MR3.NF = 0 (1 cycle of noise filtered out)
311 	 *
312 	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
313 	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
314 	 */
315 
316 	/*
317 	 * Determine reference clock rate. We must be able to get the desired
318 	 * frequency with only 62 clock ticks max (31 high, 31 low).
319 	 * Aim for a duty of 60% LOW, 40% HIGH.
320 	 */
321 	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
322 
323 	for (cks = 0; cks < 7; cks++) {
324 		/*
325 		 * 60% low time must be less than BRL + 2 + 1
326 		 * BRL max register value is 0x1F.
327 		 */
328 		brl = ((total_ticks * 6) / 10);
329 		if (brl <= (0x1F + 3))
330 			break;
331 
332 		total_ticks /= 2;
333 		rate /= 2;
334 	}
335 
336 	if (brl > (0x1F + 3)) {
337 		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
338 			(unsigned long)t->bus_freq_hz);
339 		clk_disable_unprepare(riic->clk);
340 		return -EINVAL;
341 	}
342 
343 	brh = total_ticks - brl;
344 
345 	/* Remove automatic clock ticks for sync circuit and NF */
346 	if (cks == 0) {
347 		brl -= 4;
348 		brh -= 4;
349 	} else {
350 		brl -= 3;
351 		brh -= 3;
352 	}
353 
354 	/*
355 	 * Remove clock ticks for rise and fall times. Convert ns to clock
356 	 * ticks.
357 	 */
358 	brl -= t->scl_fall_ns / (1000000000 / rate);
359 	brh -= t->scl_rise_ns / (1000000000 / rate);
360 
361 	/* Adjust for min register values for when SCLE=1 and NFE=1 */
362 	if (brl < 1)
363 		brl = 1;
364 	if (brh < 1)
365 		brh = 1;
366 
367 	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
368 		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
369 		 t->scl_fall_ns / (1000000000 / rate),
370 		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
371 
372 	/* Changing the order of accessing IICRST and ICE may break things! */
373 	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
374 	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
375 
376 	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
377 	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
378 	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
379 
380 	writeb(0, riic->base + RIIC_ICSER);
381 	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
382 
383 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
384 
385 	clk_disable_unprepare(riic->clk);
386 
387 	return 0;
388 }
389 
390 static struct riic_irq_desc riic_irqs[] = {
391 	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
392 	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
393 	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
394 	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
395 	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
396 };
397 
398 static int riic_i2c_probe(struct platform_device *pdev)
399 {
400 	struct riic_dev *riic;
401 	struct i2c_adapter *adap;
402 	struct resource *res;
403 	struct i2c_timings i2c_t;
404 	int i, ret;
405 
406 	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
407 	if (!riic)
408 		return -ENOMEM;
409 
410 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
411 	riic->base = devm_ioremap_resource(&pdev->dev, res);
412 	if (IS_ERR(riic->base))
413 		return PTR_ERR(riic->base);
414 
415 	riic->clk = devm_clk_get(&pdev->dev, NULL);
416 	if (IS_ERR(riic->clk)) {
417 		dev_err(&pdev->dev, "missing controller clock");
418 		return PTR_ERR(riic->clk);
419 	}
420 
421 	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
422 		res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
423 		if (!res)
424 			return -ENODEV;
425 
426 		ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
427 					0, riic_irqs[i].name, riic);
428 		if (ret) {
429 			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
430 			return ret;
431 		}
432 	}
433 
434 	adap = &riic->adapter;
435 	i2c_set_adapdata(adap, riic);
436 	strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
437 	adap->owner = THIS_MODULE;
438 	adap->algo = &riic_algo;
439 	adap->dev.parent = &pdev->dev;
440 	adap->dev.of_node = pdev->dev.of_node;
441 
442 	init_completion(&riic->msg_done);
443 
444 	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
445 
446 	ret = riic_init_hw(riic, &i2c_t);
447 	if (ret)
448 		return ret;
449 
450 
451 	ret = i2c_add_adapter(adap);
452 	if (ret)
453 		return ret;
454 
455 	platform_set_drvdata(pdev, riic);
456 
457 	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
458 		 i2c_t.bus_freq_hz);
459 	return 0;
460 }
461 
462 static int riic_i2c_remove(struct platform_device *pdev)
463 {
464 	struct riic_dev *riic = platform_get_drvdata(pdev);
465 
466 	writeb(0, riic->base + RIIC_ICIER);
467 	i2c_del_adapter(&riic->adapter);
468 
469 	return 0;
470 }
471 
472 static const struct of_device_id riic_i2c_dt_ids[] = {
473 	{ .compatible = "renesas,riic-rz" },
474 	{ /* Sentinel */ },
475 };
476 
477 static struct platform_driver riic_i2c_driver = {
478 	.probe		= riic_i2c_probe,
479 	.remove		= riic_i2c_remove,
480 	.driver		= {
481 		.name	= "i2c-riic",
482 		.of_match_table = riic_i2c_dt_ids,
483 	},
484 };
485 
486 module_platform_driver(riic_i2c_driver);
487 
488 MODULE_DESCRIPTION("Renesas RIIC adapter");
489 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
490 MODULE_LICENSE("GPL v2");
491 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
492