xref: /openbmc/linux/drivers/i2c/busses/i2c-riic.c (revision 4fc4dca8) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas RIIC driver
4  *
5  * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
6  * Copyright (C) 2013 Renesas Solutions Corp.
7  */
8 
9 /*
10  * This i2c core has a lot of interrupts, namely 8. We use their chaining as
11  * some kind of state machine.
12  *
13  * 1) The main xfer routine kicks off a transmission by putting the start bit
14  * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
15  * since we need to send the slave address + RW bit in every case.
16  *
17  * 2) TIE sends slave address + RW bit and selects how to continue.
18  *
19  * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
20  * are done, we switch over to the transmission done interrupt (TEIE) and mark
21  * the message as completed (includes sending STOP) there.
22  *
23  * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
24  * needed to start clocking, then we keep receiving until we are done. Note
25  * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
26  * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
27  * message to create the final NACK as sketched in the datasheet. This caused
28  * some subtle races (when byte n was processed and byte n+1 was already
29  * waiting), though, and I started with the safe approach.
30  *
31  * 4) If we got a NACK somewhere, we flag the error and stop the transmission
32  * via NAKIE.
33  *
34  * Also check the comments in the interrupt routines for some gory details.
35  */
36 
37 #include <linux/clk.h>
38 #include <linux/completion.h>
39 #include <linux/err.h>
40 #include <linux/i2c.h>
41 #include <linux/interrupt.h>
42 #include <linux/io.h>
43 #include <linux/module.h>
44 #include <linux/of.h>
45 #include <linux/platform_device.h>
46 #include <linux/pm_runtime.h>
47 
48 #define RIIC_ICCR1	0x00
49 #define RIIC_ICCR2	0x04
50 #define RIIC_ICMR1	0x08
51 #define RIIC_ICMR3	0x10
52 #define RIIC_ICSER	0x18
53 #define RIIC_ICIER	0x1c
54 #define RIIC_ICSR2	0x24
55 #define RIIC_ICBRL	0x34
56 #define RIIC_ICBRH	0x38
57 #define RIIC_ICDRT	0x3c
58 #define RIIC_ICDRR	0x40
59 
60 #define ICCR1_ICE	0x80
61 #define ICCR1_IICRST	0x40
62 #define ICCR1_SOWP	0x10
63 
64 #define ICCR2_BBSY	0x80
65 #define ICCR2_SP	0x08
66 #define ICCR2_RS	0x04
67 #define ICCR2_ST	0x02
68 
69 #define ICMR1_CKS_MASK	0x70
70 #define ICMR1_BCWP	0x08
71 #define ICMR1_CKS(_x)	((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
72 
73 #define ICMR3_RDRFS	0x20
74 #define ICMR3_ACKWP	0x10
75 #define ICMR3_ACKBT	0x08
76 
77 #define ICIER_TIE	0x80
78 #define ICIER_TEIE	0x40
79 #define ICIER_RIE	0x20
80 #define ICIER_NAKIE	0x10
81 #define ICIER_SPIE	0x08
82 
83 #define ICSR2_NACKF	0x10
84 
85 #define ICBR_RESERVED	0xe0 /* Should be 1 on writes */
86 
87 #define RIIC_INIT_MSG	-1
88 
89 struct riic_dev {
90 	void __iomem *base;
91 	u8 *buf;
92 	struct i2c_msg *msg;
93 	int bytes_left;
94 	int err;
95 	int is_last;
96 	struct completion msg_done;
97 	struct i2c_adapter adapter;
98 	struct clk *clk;
99 };
100 
101 struct riic_irq_desc {
102 	int res_num;
103 	irq_handler_t isr;
104 	char *name;
105 };
106 
107 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
108 {
109 	writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
110 }
111 
112 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
113 {
114 	struct riic_dev *riic = i2c_get_adapdata(adap);
115 	unsigned long time_left;
116 	int i;
117 	u8 start_bit;
118 
119 	pm_runtime_get_sync(adap->dev.parent);
120 
121 	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
122 		riic->err = -EBUSY;
123 		goto out;
124 	}
125 
126 	reinit_completion(&riic->msg_done);
127 	riic->err = 0;
128 
129 	writeb(0, riic->base + RIIC_ICSR2);
130 
131 	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
132 		riic->bytes_left = RIIC_INIT_MSG;
133 		riic->buf = msgs[i].buf;
134 		riic->msg = &msgs[i];
135 		riic->is_last = (i == num - 1);
136 
137 		writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
138 
139 		writeb(start_bit, riic->base + RIIC_ICCR2);
140 
141 		time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
142 		if (time_left == 0)
143 			riic->err = -ETIMEDOUT;
144 
145 		if (riic->err)
146 			break;
147 
148 		start_bit = ICCR2_RS;
149 	}
150 
151  out:
152 	pm_runtime_put(adap->dev.parent);
153 
154 	return riic->err ?: num;
155 }
156 
157 static irqreturn_t riic_tdre_isr(int irq, void *data)
158 {
159 	struct riic_dev *riic = data;
160 	u8 val;
161 
162 	if (!riic->bytes_left)
163 		return IRQ_NONE;
164 
165 	if (riic->bytes_left == RIIC_INIT_MSG) {
166 		if (riic->msg->flags & I2C_M_RD)
167 			/* On read, switch over to receive interrupt */
168 			riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
169 		else
170 			/* On write, initialize length */
171 			riic->bytes_left = riic->msg->len;
172 
173 		val = i2c_8bit_addr_from_msg(riic->msg);
174 	} else {
175 		val = *riic->buf;
176 		riic->buf++;
177 		riic->bytes_left--;
178 	}
179 
180 	/*
181 	 * Switch to transmission ended interrupt when done. Do check here
182 	 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
183 	 * 0 length then)
184 	 */
185 	if (riic->bytes_left == 0)
186 		riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
187 
188 	/*
189 	 * This acks the TIE interrupt. We get another TIE immediately if our
190 	 * value could be moved to the shadow shift register right away. So
191 	 * this must be after updates to ICIER (where we want to disable TIE)!
192 	 */
193 	writeb(val, riic->base + RIIC_ICDRT);
194 
195 	return IRQ_HANDLED;
196 }
197 
198 static irqreturn_t riic_tend_isr(int irq, void *data)
199 {
200 	struct riic_dev *riic = data;
201 
202 	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
203 		/* We got a NACKIE */
204 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
205 		riic->err = -ENXIO;
206 	} else if (riic->bytes_left) {
207 		return IRQ_NONE;
208 	}
209 
210 	if (riic->is_last || riic->err) {
211 		riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
212 		writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
213 	} else {
214 		/* Transfer is complete, but do not send STOP */
215 		riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
216 		complete(&riic->msg_done);
217 	}
218 
219 	return IRQ_HANDLED;
220 }
221 
222 static irqreturn_t riic_rdrf_isr(int irq, void *data)
223 {
224 	struct riic_dev *riic = data;
225 
226 	if (!riic->bytes_left)
227 		return IRQ_NONE;
228 
229 	if (riic->bytes_left == RIIC_INIT_MSG) {
230 		riic->bytes_left = riic->msg->len;
231 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
232 		return IRQ_HANDLED;
233 	}
234 
235 	if (riic->bytes_left == 1) {
236 		/* STOP must come before we set ACKBT! */
237 		if (riic->is_last) {
238 			riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
239 			writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
240 		}
241 
242 		riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
243 
244 	} else {
245 		riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
246 	}
247 
248 	/* Reading acks the RIE interrupt */
249 	*riic->buf = readb(riic->base + RIIC_ICDRR);
250 	riic->buf++;
251 	riic->bytes_left--;
252 
253 	return IRQ_HANDLED;
254 }
255 
256 static irqreturn_t riic_stop_isr(int irq, void *data)
257 {
258 	struct riic_dev *riic = data;
259 
260 	/* read back registers to confirm writes have fully propagated */
261 	writeb(0, riic->base + RIIC_ICSR2);
262 	readb(riic->base + RIIC_ICSR2);
263 	writeb(0, riic->base + RIIC_ICIER);
264 	readb(riic->base + RIIC_ICIER);
265 
266 	complete(&riic->msg_done);
267 
268 	return IRQ_HANDLED;
269 }
270 
271 static u32 riic_func(struct i2c_adapter *adap)
272 {
273 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
274 }
275 
276 static const struct i2c_algorithm riic_algo = {
277 	.master_xfer	= riic_xfer,
278 	.functionality	= riic_func,
279 };
280 
281 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
282 {
283 	int ret = 0;
284 	unsigned long rate;
285 	int total_ticks, cks, brl, brh;
286 
287 	pm_runtime_get_sync(riic->adapter.dev.parent);
288 
289 	if (t->bus_freq_hz > 400000) {
290 		dev_err(&riic->adapter.dev,
291 			"unsupported bus speed (%dHz). 400000 max\n",
292 			t->bus_freq_hz);
293 		ret = -EINVAL;
294 		goto out;
295 	}
296 
297 	rate = clk_get_rate(riic->clk);
298 
299 	/*
300 	 * Assume the default register settings:
301 	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
302 	 *  FER.NFE = 1 (noise circuit enabled)
303 	 *  MR3.NF = 0 (1 cycle of noise filtered out)
304 	 *
305 	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
306 	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
307 	 */
308 
309 	/*
310 	 * Determine reference clock rate. We must be able to get the desired
311 	 * frequency with only 62 clock ticks max (31 high, 31 low).
312 	 * Aim for a duty of 60% LOW, 40% HIGH.
313 	 */
314 	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
315 
316 	for (cks = 0; cks < 7; cks++) {
317 		/*
318 		 * 60% low time must be less than BRL + 2 + 1
319 		 * BRL max register value is 0x1F.
320 		 */
321 		brl = ((total_ticks * 6) / 10);
322 		if (brl <= (0x1F + 3))
323 			break;
324 
325 		total_ticks /= 2;
326 		rate /= 2;
327 	}
328 
329 	if (brl > (0x1F + 3)) {
330 		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
331 			(unsigned long)t->bus_freq_hz);
332 		ret = -EINVAL;
333 		goto out;
334 	}
335 
336 	brh = total_ticks - brl;
337 
338 	/* Remove automatic clock ticks for sync circuit and NF */
339 	if (cks == 0) {
340 		brl -= 4;
341 		brh -= 4;
342 	} else {
343 		brl -= 3;
344 		brh -= 3;
345 	}
346 
347 	/*
348 	 * Remove clock ticks for rise and fall times. Convert ns to clock
349 	 * ticks.
350 	 */
351 	brl -= t->scl_fall_ns / (1000000000 / rate);
352 	brh -= t->scl_rise_ns / (1000000000 / rate);
353 
354 	/* Adjust for min register values for when SCLE=1 and NFE=1 */
355 	if (brl < 1)
356 		brl = 1;
357 	if (brh < 1)
358 		brh = 1;
359 
360 	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
361 		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
362 		 t->scl_fall_ns / (1000000000 / rate),
363 		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
364 
365 	/* Changing the order of accessing IICRST and ICE may break things! */
366 	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
367 	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
368 
369 	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
370 	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
371 	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
372 
373 	writeb(0, riic->base + RIIC_ICSER);
374 	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
375 
376 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
377 
378 out:
379 	pm_runtime_put(riic->adapter.dev.parent);
380 	return ret;
381 }
382 
383 static struct riic_irq_desc riic_irqs[] = {
384 	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
385 	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
386 	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
387 	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
388 	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
389 };
390 
391 static int riic_i2c_probe(struct platform_device *pdev)
392 {
393 	struct riic_dev *riic;
394 	struct i2c_adapter *adap;
395 	struct resource *res;
396 	struct i2c_timings i2c_t;
397 	int i, ret;
398 
399 	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
400 	if (!riic)
401 		return -ENOMEM;
402 
403 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
404 	riic->base = devm_ioremap_resource(&pdev->dev, res);
405 	if (IS_ERR(riic->base))
406 		return PTR_ERR(riic->base);
407 
408 	riic->clk = devm_clk_get(&pdev->dev, NULL);
409 	if (IS_ERR(riic->clk)) {
410 		dev_err(&pdev->dev, "missing controller clock");
411 		return PTR_ERR(riic->clk);
412 	}
413 
414 	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
415 		res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
416 		if (!res)
417 			return -ENODEV;
418 
419 		ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
420 					0, riic_irqs[i].name, riic);
421 		if (ret) {
422 			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
423 			return ret;
424 		}
425 	}
426 
427 	adap = &riic->adapter;
428 	i2c_set_adapdata(adap, riic);
429 	strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
430 	adap->owner = THIS_MODULE;
431 	adap->algo = &riic_algo;
432 	adap->dev.parent = &pdev->dev;
433 	adap->dev.of_node = pdev->dev.of_node;
434 
435 	init_completion(&riic->msg_done);
436 
437 	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
438 
439 	pm_runtime_enable(&pdev->dev);
440 
441 	ret = riic_init_hw(riic, &i2c_t);
442 	if (ret)
443 		goto out;
444 
445 	ret = i2c_add_adapter(adap);
446 	if (ret)
447 		goto out;
448 
449 	platform_set_drvdata(pdev, riic);
450 
451 	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
452 		 i2c_t.bus_freq_hz);
453 	return 0;
454 
455 out:
456 	pm_runtime_disable(&pdev->dev);
457 	return ret;
458 }
459 
460 static int riic_i2c_remove(struct platform_device *pdev)
461 {
462 	struct riic_dev *riic = platform_get_drvdata(pdev);
463 
464 	pm_runtime_get_sync(&pdev->dev);
465 	writeb(0, riic->base + RIIC_ICIER);
466 	pm_runtime_put(&pdev->dev);
467 	i2c_del_adapter(&riic->adapter);
468 	pm_runtime_disable(&pdev->dev);
469 
470 	return 0;
471 }
472 
473 static const struct of_device_id riic_i2c_dt_ids[] = {
474 	{ .compatible = "renesas,riic-rz" },
475 	{ /* Sentinel */ },
476 };
477 
478 static struct platform_driver riic_i2c_driver = {
479 	.probe		= riic_i2c_probe,
480 	.remove		= riic_i2c_remove,
481 	.driver		= {
482 		.name	= "i2c-riic",
483 		.of_match_table = riic_i2c_dt_ids,
484 	},
485 };
486 
487 module_platform_driver(riic_i2c_driver);
488 
489 MODULE_DESCRIPTION("Renesas RIIC adapter");
490 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
491 MODULE_LICENSE("GPL v2");
492 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
493