1 /* 2 * Driver for the Renesas R-Car I2C unit 3 * 4 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> 5 * Copyright (C) 2011-2015 Renesas Electronics Corporation 6 * 7 * Copyright (C) 2012-14 Renesas Solutions Corp. 8 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 9 * 10 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 11 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; version 2 of the License. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 #include <linux/clk.h> 23 #include <linux/delay.h> 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/err.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/i2c.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/of_device.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 38 /* register offsets */ 39 #define ICSCR 0x00 /* slave ctrl */ 40 #define ICMCR 0x04 /* master ctrl */ 41 #define ICSSR 0x08 /* slave status */ 42 #define ICMSR 0x0C /* master status */ 43 #define ICSIER 0x10 /* slave irq enable */ 44 #define ICMIER 0x14 /* master irq enable */ 45 #define ICCCR 0x18 /* clock dividers */ 46 #define ICSAR 0x1C /* slave address */ 47 #define ICMAR 0x20 /* master address */ 48 #define ICRXTX 0x24 /* data port */ 49 #define ICDMAER 0x3c /* DMA enable */ 50 #define ICFBSCR 0x38 /* first bit setup cycle */ 51 52 /* ICSCR */ 53 #define SDBS (1 << 3) /* slave data buffer select */ 54 #define SIE (1 << 2) /* slave interface enable */ 55 #define GCAE (1 << 1) /* general call address enable */ 56 #define FNA (1 << 0) /* forced non acknowledgment */ 57 58 /* ICMCR */ 59 #define MDBS (1 << 7) /* non-fifo mode switch */ 60 #define FSCL (1 << 6) /* override SCL pin */ 61 #define FSDA (1 << 5) /* override SDA pin */ 62 #define OBPC (1 << 4) /* override pins */ 63 #define MIE (1 << 3) /* master if enable */ 64 #define TSBE (1 << 2) 65 #define FSB (1 << 1) /* force stop bit */ 66 #define ESG (1 << 0) /* enable start bit gen */ 67 68 /* ICSSR (also for ICSIER) */ 69 #define GCAR (1 << 6) /* general call received */ 70 #define STM (1 << 5) /* slave transmit mode */ 71 #define SSR (1 << 4) /* stop received */ 72 #define SDE (1 << 3) /* slave data empty */ 73 #define SDT (1 << 2) /* slave data transmitted */ 74 #define SDR (1 << 1) /* slave data received */ 75 #define SAR (1 << 0) /* slave addr received */ 76 77 /* ICMSR (also for ICMIE) */ 78 #define MNR (1 << 6) /* nack received */ 79 #define MAL (1 << 5) /* arbitration lost */ 80 #define MST (1 << 4) /* sent a stop */ 81 #define MDE (1 << 3) 82 #define MDT (1 << 2) 83 #define MDR (1 << 1) 84 #define MAT (1 << 0) /* slave addr xfer done */ 85 86 /* ICDMAER */ 87 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 88 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 89 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 90 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 91 92 /* ICFBSCR */ 93 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */ 94 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 95 96 97 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 98 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 99 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) 100 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 101 102 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 103 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 104 #define RCAR_IRQ_STOP (MST) 105 106 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 107 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 108 109 #define ID_LAST_MSG (1 << 0) 110 #define ID_FIRST_MSG (1 << 1) 111 #define ID_DONE (1 << 2) 112 #define ID_ARBLOST (1 << 3) 113 #define ID_NACK (1 << 4) 114 /* persistent flags */ 115 #define ID_P_NO_RXDMA (1 << 30) /* HW forbids RXDMA sometimes */ 116 #define ID_P_PM_BLOCKED (1 << 31) 117 #define ID_P_MASK (ID_P_PM_BLOCKED | ID_P_NO_RXDMA) 118 119 enum rcar_i2c_type { 120 I2C_RCAR_GEN1, 121 I2C_RCAR_GEN2, 122 I2C_RCAR_GEN3, 123 }; 124 125 struct rcar_i2c_priv { 126 void __iomem *io; 127 struct i2c_adapter adap; 128 struct i2c_msg *msg; 129 int msgs_left; 130 struct clk *clk; 131 132 wait_queue_head_t wait; 133 134 int pos; 135 u32 icccr; 136 u32 flags; 137 u8 recovery_icmcr; /* protected by adapter lock */ 138 enum rcar_i2c_type devtype; 139 struct i2c_client *slave; 140 141 struct resource *res; 142 struct dma_chan *dma_tx; 143 struct dma_chan *dma_rx; 144 struct scatterlist sg; 145 enum dma_data_direction dma_direction; 146 147 struct reset_control *rstc; 148 }; 149 150 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 151 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 152 153 #define LOOP_TIMEOUT 1024 154 155 156 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 157 { 158 writel(val, priv->io + reg); 159 } 160 161 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 162 { 163 return readl(priv->io + reg); 164 } 165 166 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 167 { 168 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 169 170 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 171 172 }; 173 174 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 175 { 176 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 177 178 if (val) 179 priv->recovery_icmcr |= FSCL; 180 else 181 priv->recovery_icmcr &= ~FSCL; 182 183 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 184 }; 185 186 /* No get_sda, because the HW only reports its bus free logic, not SDA itself */ 187 188 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 189 { 190 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 191 192 if (val) 193 priv->recovery_icmcr |= FSDA; 194 else 195 priv->recovery_icmcr &= ~FSDA; 196 197 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 198 }; 199 200 static struct i2c_bus_recovery_info rcar_i2c_bri = { 201 .get_scl = rcar_i2c_get_scl, 202 .set_scl = rcar_i2c_set_scl, 203 .set_sda = rcar_i2c_set_sda, 204 .recover_bus = i2c_generic_scl_recovery, 205 }; 206 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 207 { 208 /* reset master mode */ 209 rcar_i2c_write(priv, ICMIER, 0); 210 rcar_i2c_write(priv, ICMCR, MDBS); 211 rcar_i2c_write(priv, ICMSR, 0); 212 /* start clock */ 213 rcar_i2c_write(priv, ICCCR, priv->icccr); 214 } 215 216 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 217 { 218 int i, ret; 219 220 for (i = 0; i < LOOP_TIMEOUT; i++) { 221 /* make sure that bus is not busy */ 222 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 223 return 0; 224 udelay(1); 225 } 226 227 /* Waiting did not help, try to recover */ 228 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 229 ret = i2c_recover_bus(&priv->adap); 230 231 /* No failure when recovering, so check bus busy bit again */ 232 if (ret == 0) 233 ret = (rcar_i2c_read(priv, ICMCR) & FSDA) ? -EBUSY : 0; 234 235 return ret; 236 } 237 238 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) 239 { 240 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 241 unsigned long rate; 242 struct device *dev = rcar_i2c_priv_to_dev(priv); 243 244 /* Fall back to previously used values if not supplied */ 245 t->bus_freq_hz = t->bus_freq_hz ?: 100000; 246 t->scl_fall_ns = t->scl_fall_ns ?: 35; 247 t->scl_rise_ns = t->scl_rise_ns ?: 200; 248 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; 249 250 switch (priv->devtype) { 251 case I2C_RCAR_GEN1: 252 cdf_width = 2; 253 break; 254 case I2C_RCAR_GEN2: 255 case I2C_RCAR_GEN3: 256 cdf_width = 3; 257 break; 258 default: 259 dev_err(dev, "device type error\n"); 260 return -EIO; 261 } 262 263 /* 264 * calculate SCL clock 265 * see 266 * ICCCR 267 * 268 * ick = clkp / (1 + CDF) 269 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 270 * 271 * ick : I2C internal clock < 20 MHz 272 * ticf : I2C SCL falling time 273 * tr : I2C SCL rising time 274 * intd : LSI internal delay 275 * clkp : peripheral_clk 276 * F[] : integer up-valuation 277 */ 278 rate = clk_get_rate(priv->clk); 279 cdf = rate / 20000000; 280 if (cdf >= 1U << cdf_width) { 281 dev_err(dev, "Input clock %lu too high\n", rate); 282 return -EIO; 283 } 284 ick = rate / (cdf + 1); 285 286 /* 287 * it is impossible to calculate large scale 288 * number on u32. separate it 289 * 290 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 291 * = F[sum * ick / 1000000000] 292 * = F[(ick / 1000000) * sum / 1000] 293 */ 294 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; 295 round = (ick + 500000) / 1000000 * sum; 296 round = (round + 500) / 1000; 297 298 /* 299 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 300 * 301 * Calculation result (= SCL) should be less than 302 * bus_speed for hardware safety 303 * 304 * We could use something along the lines of 305 * div = ick / (bus_speed + 1) + 1; 306 * scgd = (div - 20 - round + 7) / 8; 307 * scl = ick / (20 + (scgd * 8) + round); 308 * (not fully verified) but that would get pretty involved 309 */ 310 for (scgd = 0; scgd < 0x40; scgd++) { 311 scl = ick / (20 + (scgd * 8) + round); 312 if (scl <= t->bus_freq_hz) 313 goto scgd_find; 314 } 315 dev_err(dev, "it is impossible to calculate best SCL\n"); 316 return -EIO; 317 318 scgd_find: 319 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 320 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); 321 322 /* keep icccr value */ 323 priv->icccr = scgd << cdf_width | cdf; 324 325 return 0; 326 } 327 328 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 329 { 330 int read = !!rcar_i2c_is_recv(priv); 331 332 priv->pos = 0; 333 if (priv->msgs_left == 1) 334 priv->flags |= ID_LAST_MSG; 335 336 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 337 /* 338 * We don't have a test case but the HW engineers say that the write order 339 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 340 * it didn't cause a drawback for me, let's rather be safe than sorry. 341 */ 342 if (priv->flags & ID_FIRST_MSG) { 343 rcar_i2c_write(priv, ICMSR, 0); 344 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 345 } else { 346 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 347 rcar_i2c_write(priv, ICMSR, 0); 348 } 349 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 350 } 351 352 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 353 { 354 priv->msg++; 355 priv->msgs_left--; 356 priv->flags &= ID_P_MASK; 357 rcar_i2c_prepare_msg(priv); 358 } 359 360 /* 361 * interrupt functions 362 */ 363 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 364 { 365 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 366 ? priv->dma_rx : priv->dma_tx; 367 368 /* Disable DMA Master Received/Transmitted */ 369 rcar_i2c_write(priv, ICDMAER, 0); 370 371 /* Reset default delay */ 372 rcar_i2c_write(priv, ICFBSCR, TCYC06); 373 374 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 375 sg_dma_len(&priv->sg), priv->dma_direction); 376 377 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 378 if (priv->devtype == I2C_RCAR_GEN3 && 379 priv->dma_direction == DMA_FROM_DEVICE) 380 priv->flags |= ID_P_NO_RXDMA; 381 382 priv->dma_direction = DMA_NONE; 383 } 384 385 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 386 { 387 if (priv->dma_direction == DMA_NONE) 388 return; 389 else if (priv->dma_direction == DMA_FROM_DEVICE) 390 dmaengine_terminate_all(priv->dma_rx); 391 else if (priv->dma_direction == DMA_TO_DEVICE) 392 dmaengine_terminate_all(priv->dma_tx); 393 394 rcar_i2c_dma_unmap(priv); 395 } 396 397 static void rcar_i2c_dma_callback(void *data) 398 { 399 struct rcar_i2c_priv *priv = data; 400 401 priv->pos += sg_dma_len(&priv->sg); 402 403 rcar_i2c_dma_unmap(priv); 404 } 405 406 static void rcar_i2c_dma(struct rcar_i2c_priv *priv) 407 { 408 struct device *dev = rcar_i2c_priv_to_dev(priv); 409 struct i2c_msg *msg = priv->msg; 410 bool read = msg->flags & I2C_M_RD; 411 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 412 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 413 struct dma_async_tx_descriptor *txdesc; 414 dma_addr_t dma_addr; 415 dma_cookie_t cookie; 416 unsigned char *buf; 417 int len; 418 419 /* Do various checks to see if DMA is feasible at all */ 420 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) || 421 (read && priv->flags & ID_P_NO_RXDMA)) 422 return; 423 424 if (read) { 425 /* 426 * The last two bytes needs to be fetched using PIO in 427 * order for the STOP phase to work. 428 */ 429 buf = priv->msg->buf; 430 len = priv->msg->len - 2; 431 } else { 432 /* 433 * First byte in message was sent using PIO. 434 */ 435 buf = priv->msg->buf + 1; 436 len = priv->msg->len - 1; 437 } 438 439 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 440 if (dma_mapping_error(chan->device->dev, dma_addr)) { 441 dev_dbg(dev, "dma map failed, using PIO\n"); 442 return; 443 } 444 445 sg_dma_len(&priv->sg) = len; 446 sg_dma_address(&priv->sg) = dma_addr; 447 448 priv->dma_direction = dir; 449 450 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 451 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 452 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 453 if (!txdesc) { 454 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 455 rcar_i2c_cleanup_dma(priv); 456 return; 457 } 458 459 txdesc->callback = rcar_i2c_dma_callback; 460 txdesc->callback_param = priv; 461 462 cookie = dmaengine_submit(txdesc); 463 if (dma_submit_error(cookie)) { 464 dev_dbg(dev, "submitting dma failed, using PIO\n"); 465 rcar_i2c_cleanup_dma(priv); 466 return; 467 } 468 469 /* Set delay for DMA operations */ 470 rcar_i2c_write(priv, ICFBSCR, TCYC17); 471 472 /* Enable DMA Master Received/Transmitted */ 473 if (read) 474 rcar_i2c_write(priv, ICDMAER, RMDMAE); 475 else 476 rcar_i2c_write(priv, ICDMAER, TMDMAE); 477 478 dma_async_issue_pending(chan); 479 } 480 481 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 482 { 483 struct i2c_msg *msg = priv->msg; 484 485 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 486 if (!(msr & MDE)) 487 return; 488 489 if (priv->pos < msg->len) { 490 /* 491 * Prepare next data to ICRXTX register. 492 * This data will go to _SHIFT_ register. 493 * 494 * * 495 * [ICRXTX] -> [SHIFT] -> [I2C bus] 496 */ 497 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 498 priv->pos++; 499 500 /* 501 * Try to use DMA to transmit the rest of the data if 502 * address transfer phase just finished. 503 */ 504 if (msr & MAT) 505 rcar_i2c_dma(priv); 506 } else { 507 /* 508 * The last data was pushed to ICRXTX on _PREV_ empty irq. 509 * It is on _SHIFT_ register, and will sent to I2C bus. 510 * 511 * * 512 * [ICRXTX] -> [SHIFT] -> [I2C bus] 513 */ 514 515 if (priv->flags & ID_LAST_MSG) { 516 /* 517 * If current msg is the _LAST_ msg, 518 * prepare stop condition here. 519 * ID_DONE will be set on STOP irq. 520 */ 521 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 522 } else { 523 rcar_i2c_next_msg(priv); 524 return; 525 } 526 } 527 528 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 529 } 530 531 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 532 { 533 struct i2c_msg *msg = priv->msg; 534 535 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 536 if (!(msr & MDR)) 537 return; 538 539 if (msr & MAT) { 540 /* 541 * Address transfer phase finished, but no data at this point. 542 * Try to use DMA to receive data. 543 */ 544 rcar_i2c_dma(priv); 545 } else if (priv->pos < msg->len) { 546 /* get received data */ 547 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 548 priv->pos++; 549 } 550 551 /* 552 * If next received data is the _LAST_, go to STOP phase. Might be 553 * overwritten by REP START when setting up a new msg. Not elegant 554 * but the only stable sequence for REP START I have found so far. 555 * If you want to change this code, make sure sending one transfer with 556 * four messages (WR-RD-WR-RD) works! 557 */ 558 if (priv->pos + 1 >= msg->len) 559 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 560 561 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 562 rcar_i2c_next_msg(priv); 563 else 564 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 565 } 566 567 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 568 { 569 u32 ssr_raw, ssr_filtered; 570 u8 value; 571 572 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 573 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 574 575 if (!ssr_filtered) 576 return false; 577 578 /* address detected */ 579 if (ssr_filtered & SAR) { 580 /* read or write request */ 581 if (ssr_raw & STM) { 582 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 583 rcar_i2c_write(priv, ICRXTX, value); 584 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 585 } else { 586 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 587 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 588 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 589 } 590 591 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); 592 } 593 594 /* master sent stop */ 595 if (ssr_filtered & SSR) { 596 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 597 rcar_i2c_write(priv, ICSIER, SAR | SSR); 598 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 599 } 600 601 /* master wants to write to us */ 602 if (ssr_filtered & SDR) { 603 int ret; 604 605 value = rcar_i2c_read(priv, ICRXTX); 606 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 607 /* Send NACK in case of error */ 608 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 609 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 610 } 611 612 /* master wants to read from us */ 613 if (ssr_filtered & SDE) { 614 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 615 rcar_i2c_write(priv, ICRXTX, value); 616 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 617 } 618 619 return true; 620 } 621 622 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 623 { 624 struct rcar_i2c_priv *priv = ptr; 625 u32 msr, val; 626 627 /* Clear START or STOP as soon as we can */ 628 val = rcar_i2c_read(priv, ICMCR); 629 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); 630 631 msr = rcar_i2c_read(priv, ICMSR); 632 633 /* Only handle interrupts that are currently enabled */ 634 msr &= rcar_i2c_read(priv, ICMIER); 635 if (!msr) { 636 if (rcar_i2c_slave_irq(priv)) 637 return IRQ_HANDLED; 638 639 return IRQ_NONE; 640 } 641 642 /* Arbitration lost */ 643 if (msr & MAL) { 644 priv->flags |= ID_DONE | ID_ARBLOST; 645 goto out; 646 } 647 648 /* Nack */ 649 if (msr & MNR) { 650 /* HW automatically sends STOP after received NACK */ 651 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 652 priv->flags |= ID_NACK; 653 goto out; 654 } 655 656 /* Stop */ 657 if (msr & MST) { 658 priv->msgs_left--; /* The last message also made it */ 659 priv->flags |= ID_DONE; 660 goto out; 661 } 662 663 if (rcar_i2c_is_recv(priv)) 664 rcar_i2c_irq_recv(priv, msr); 665 else 666 rcar_i2c_irq_send(priv, msr); 667 668 out: 669 if (priv->flags & ID_DONE) { 670 rcar_i2c_write(priv, ICMIER, 0); 671 rcar_i2c_write(priv, ICMSR, 0); 672 wake_up(&priv->wait); 673 } 674 675 return IRQ_HANDLED; 676 } 677 678 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 679 enum dma_transfer_direction dir, 680 dma_addr_t port_addr) 681 { 682 struct dma_chan *chan; 683 struct dma_slave_config cfg; 684 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 685 int ret; 686 687 chan = dma_request_chan(dev, chan_name); 688 if (IS_ERR(chan)) { 689 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 690 chan_name, PTR_ERR(chan)); 691 return chan; 692 } 693 694 memset(&cfg, 0, sizeof(cfg)); 695 cfg.direction = dir; 696 if (dir == DMA_MEM_TO_DEV) { 697 cfg.dst_addr = port_addr; 698 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 699 } else { 700 cfg.src_addr = port_addr; 701 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 702 } 703 704 ret = dmaengine_slave_config(chan, &cfg); 705 if (ret) { 706 dev_dbg(dev, "slave_config failed for %s (%d)\n", 707 chan_name, ret); 708 dma_release_channel(chan); 709 return ERR_PTR(ret); 710 } 711 712 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 713 return chan; 714 } 715 716 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 717 struct i2c_msg *msg) 718 { 719 struct device *dev = rcar_i2c_priv_to_dev(priv); 720 bool read; 721 struct dma_chan *chan; 722 enum dma_transfer_direction dir; 723 724 read = msg->flags & I2C_M_RD; 725 726 chan = read ? priv->dma_rx : priv->dma_tx; 727 if (PTR_ERR(chan) != -EPROBE_DEFER) 728 return; 729 730 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 731 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 732 733 if (read) 734 priv->dma_rx = chan; 735 else 736 priv->dma_tx = chan; 737 } 738 739 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 740 { 741 if (!IS_ERR(priv->dma_tx)) { 742 dma_release_channel(priv->dma_tx); 743 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 744 } 745 746 if (!IS_ERR(priv->dma_rx)) { 747 dma_release_channel(priv->dma_rx); 748 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 749 } 750 } 751 752 /* I2C is a special case, we need to poll the status of a reset */ 753 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 754 { 755 int i, ret; 756 757 ret = reset_control_reset(priv->rstc); 758 if (ret) 759 return ret; 760 761 for (i = 0; i < LOOP_TIMEOUT; i++) { 762 ret = reset_control_status(priv->rstc); 763 if (ret == 0) 764 return 0; 765 udelay(1); 766 } 767 768 return -ETIMEDOUT; 769 } 770 771 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 772 struct i2c_msg *msgs, 773 int num) 774 { 775 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 776 struct device *dev = rcar_i2c_priv_to_dev(priv); 777 int i, ret; 778 long time_left; 779 780 pm_runtime_get_sync(dev); 781 782 /* Gen3 needs a reset before allowing RXDMA once */ 783 if (priv->devtype == I2C_RCAR_GEN3) { 784 priv->flags |= ID_P_NO_RXDMA; 785 if (!IS_ERR(priv->rstc)) { 786 ret = rcar_i2c_do_reset(priv); 787 if (ret == 0) 788 priv->flags &= ~ID_P_NO_RXDMA; 789 } 790 } 791 792 rcar_i2c_init(priv); 793 794 ret = rcar_i2c_bus_barrier(priv); 795 if (ret < 0) 796 goto out; 797 798 for (i = 0; i < num; i++) { 799 /* This HW can't send STOP after address phase */ 800 if (msgs[i].len == 0) { 801 ret = -EOPNOTSUPP; 802 goto out; 803 } 804 rcar_i2c_request_dma(priv, msgs + i); 805 } 806 807 /* init first message */ 808 priv->msg = msgs; 809 priv->msgs_left = num; 810 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 811 rcar_i2c_prepare_msg(priv); 812 813 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 814 num * adap->timeout); 815 if (!time_left) { 816 rcar_i2c_cleanup_dma(priv); 817 rcar_i2c_init(priv); 818 ret = -ETIMEDOUT; 819 } else if (priv->flags & ID_NACK) { 820 ret = -ENXIO; 821 } else if (priv->flags & ID_ARBLOST) { 822 ret = -EAGAIN; 823 } else { 824 ret = num - priv->msgs_left; /* The number of transfer */ 825 } 826 out: 827 pm_runtime_put(dev); 828 829 if (ret < 0 && ret != -ENXIO) 830 dev_err(dev, "error %d : %x\n", ret, priv->flags); 831 832 return ret; 833 } 834 835 static int rcar_reg_slave(struct i2c_client *slave) 836 { 837 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 838 839 if (priv->slave) 840 return -EBUSY; 841 842 if (slave->flags & I2C_CLIENT_TEN) 843 return -EAFNOSUPPORT; 844 845 /* Keep device active for slave address detection logic */ 846 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 847 848 priv->slave = slave; 849 rcar_i2c_write(priv, ICSAR, slave->addr); 850 rcar_i2c_write(priv, ICSSR, 0); 851 rcar_i2c_write(priv, ICSIER, SAR | SSR); 852 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 853 854 return 0; 855 } 856 857 static int rcar_unreg_slave(struct i2c_client *slave) 858 { 859 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 860 861 WARN_ON(!priv->slave); 862 863 rcar_i2c_write(priv, ICSIER, 0); 864 rcar_i2c_write(priv, ICSCR, 0); 865 866 priv->slave = NULL; 867 868 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 869 870 return 0; 871 } 872 873 static u32 rcar_i2c_func(struct i2c_adapter *adap) 874 { 875 /* 876 * This HW can't do: 877 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 878 * I2C_M_NOSTART (automatically sends address after START) 879 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 880 */ 881 return I2C_FUNC_I2C | I2C_FUNC_SLAVE | 882 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 883 } 884 885 static const struct i2c_algorithm rcar_i2c_algo = { 886 .master_xfer = rcar_i2c_master_xfer, 887 .functionality = rcar_i2c_func, 888 .reg_slave = rcar_reg_slave, 889 .unreg_slave = rcar_unreg_slave, 890 }; 891 892 static const struct of_device_id rcar_i2c_dt_ids[] = { 893 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 894 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 895 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 896 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 897 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 898 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 899 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 900 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 901 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 902 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 903 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 904 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 905 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 906 {}, 907 }; 908 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 909 910 static int rcar_i2c_probe(struct platform_device *pdev) 911 { 912 struct rcar_i2c_priv *priv; 913 struct i2c_adapter *adap; 914 struct device *dev = &pdev->dev; 915 struct i2c_timings i2c_t; 916 int irq, ret; 917 918 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 919 if (!priv) 920 return -ENOMEM; 921 922 priv->clk = devm_clk_get(dev, NULL); 923 if (IS_ERR(priv->clk)) { 924 dev_err(dev, "cannot get clock\n"); 925 return PTR_ERR(priv->clk); 926 } 927 928 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 929 930 priv->io = devm_ioremap_resource(dev, priv->res); 931 if (IS_ERR(priv->io)) 932 return PTR_ERR(priv->io); 933 934 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 935 init_waitqueue_head(&priv->wait); 936 937 adap = &priv->adap; 938 adap->nr = pdev->id; 939 adap->algo = &rcar_i2c_algo; 940 adap->class = I2C_CLASS_DEPRECATED; 941 adap->retries = 3; 942 adap->dev.parent = dev; 943 adap->dev.of_node = dev->of_node; 944 adap->bus_recovery_info = &rcar_i2c_bri; 945 i2c_set_adapdata(adap, priv); 946 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 947 948 i2c_parse_fw_timings(dev, &i2c_t, false); 949 950 /* Init DMA */ 951 sg_init_table(&priv->sg, 1); 952 priv->dma_direction = DMA_NONE; 953 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 954 955 /* Activate device for clock calculation */ 956 pm_runtime_enable(dev); 957 pm_runtime_get_sync(dev); 958 ret = rcar_i2c_clock_calculate(priv, &i2c_t); 959 if (ret < 0) 960 goto out_pm_put; 961 962 if (priv->devtype == I2C_RCAR_GEN3) { 963 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 964 if (!IS_ERR(priv->rstc)) { 965 ret = reset_control_status(priv->rstc); 966 if (ret < 0) 967 priv->rstc = ERR_PTR(-ENOTSUPP); 968 } 969 } 970 971 /* Stay always active when multi-master to keep arbitration working */ 972 if (of_property_read_bool(dev->of_node, "multi-master")) 973 priv->flags |= ID_P_PM_BLOCKED; 974 else 975 pm_runtime_put(dev); 976 977 978 irq = platform_get_irq(pdev, 0); 979 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); 980 if (ret < 0) { 981 dev_err(dev, "cannot get irq %d\n", irq); 982 goto out_pm_disable; 983 } 984 985 platform_set_drvdata(pdev, priv); 986 987 ret = i2c_add_numbered_adapter(adap); 988 if (ret < 0) 989 goto out_pm_disable; 990 991 dev_info(dev, "probed\n"); 992 993 return 0; 994 995 out_pm_put: 996 pm_runtime_put(dev); 997 out_pm_disable: 998 pm_runtime_disable(dev); 999 return ret; 1000 } 1001 1002 static int rcar_i2c_remove(struct platform_device *pdev) 1003 { 1004 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1005 struct device *dev = &pdev->dev; 1006 1007 i2c_del_adapter(&priv->adap); 1008 rcar_i2c_release_dma(priv); 1009 if (priv->flags & ID_P_PM_BLOCKED) 1010 pm_runtime_put(dev); 1011 pm_runtime_disable(dev); 1012 1013 return 0; 1014 } 1015 1016 static struct platform_driver rcar_i2c_driver = { 1017 .driver = { 1018 .name = "i2c-rcar", 1019 .of_match_table = rcar_i2c_dt_ids, 1020 }, 1021 .probe = rcar_i2c_probe, 1022 .remove = rcar_i2c_remove, 1023 }; 1024 1025 module_platform_driver(rcar_i2c_driver); 1026 1027 MODULE_LICENSE("GPL v2"); 1028 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1029 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1030