1 /* 2 * drivers/i2c/busses/i2c-rcar.c 3 * 4 * Copyright (C) 2012 Renesas Solutions Corp. 5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 8 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 9 * 10 * This file used out-of-tree driver i2c-rcar.c 11 * Copyright (C) 2011-2012 Renesas Electronics Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 */ 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/err.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/i2c.h> 33 #include <linux/i2c/i2c-rcar.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/platform_device.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/slab.h> 39 #include <linux/spinlock.h> 40 41 /* register offsets */ 42 #define ICSCR 0x00 /* slave ctrl */ 43 #define ICMCR 0x04 /* master ctrl */ 44 #define ICSSR 0x08 /* slave status */ 45 #define ICMSR 0x0C /* master status */ 46 #define ICSIER 0x10 /* slave irq enable */ 47 #define ICMIER 0x14 /* master irq enable */ 48 #define ICCCR 0x18 /* clock dividers */ 49 #define ICSAR 0x1C /* slave address */ 50 #define ICMAR 0x20 /* master address */ 51 #define ICRXTX 0x24 /* data port */ 52 53 /* ICMCR */ 54 #define MDBS (1 << 7) /* non-fifo mode switch */ 55 #define FSCL (1 << 6) /* override SCL pin */ 56 #define FSDA (1 << 5) /* override SDA pin */ 57 #define OBPC (1 << 4) /* override pins */ 58 #define MIE (1 << 3) /* master if enable */ 59 #define TSBE (1 << 2) 60 #define FSB (1 << 1) /* force stop bit */ 61 #define ESG (1 << 0) /* en startbit gen */ 62 63 /* ICMSR */ 64 #define MNR (1 << 6) /* nack received */ 65 #define MAL (1 << 5) /* arbitration lost */ 66 #define MST (1 << 4) /* sent a stop */ 67 #define MDE (1 << 3) 68 #define MDT (1 << 2) 69 #define MDR (1 << 1) 70 #define MAT (1 << 0) /* slave addr xfer done */ 71 72 /* ICMIE */ 73 #define MNRE (1 << 6) /* nack irq en */ 74 #define MALE (1 << 5) /* arblos irq en */ 75 #define MSTE (1 << 4) /* stop irq en */ 76 #define MDEE (1 << 3) 77 #define MDTE (1 << 2) 78 #define MDRE (1 << 1) 79 #define MATE (1 << 0) /* address sent irq en */ 80 81 82 enum { 83 RCAR_BUS_PHASE_ADDR, 84 RCAR_BUS_PHASE_DATA, 85 RCAR_BUS_PHASE_STOP, 86 }; 87 88 enum { 89 RCAR_IRQ_CLOSE, 90 RCAR_IRQ_OPEN_FOR_SEND, 91 RCAR_IRQ_OPEN_FOR_RECV, 92 RCAR_IRQ_OPEN_FOR_STOP, 93 }; 94 95 /* 96 * flags 97 */ 98 #define ID_LAST_MSG (1 << 0) 99 #define ID_IOERROR (1 << 1) 100 #define ID_DONE (1 << 2) 101 #define ID_ARBLOST (1 << 3) 102 #define ID_NACK (1 << 4) 103 104 enum rcar_i2c_type { 105 I2C_RCAR_H1, 106 I2C_RCAR_H2, 107 }; 108 109 struct rcar_i2c_priv { 110 void __iomem *io; 111 struct i2c_adapter adap; 112 struct i2c_msg *msg; 113 114 spinlock_t lock; 115 wait_queue_head_t wait; 116 117 int pos; 118 int irq; 119 u32 icccr; 120 u32 flags; 121 enum rcar_i2c_type devtype; 122 }; 123 124 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 125 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 126 127 #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) 128 #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) 129 130 #define LOOP_TIMEOUT 1024 131 132 /* 133 * basic functions 134 */ 135 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 136 { 137 writel(val, priv->io + reg); 138 } 139 140 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 141 { 142 return readl(priv->io + reg); 143 } 144 145 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 146 { 147 /* 148 * reset slave mode. 149 * slave mode is not used on this driver 150 */ 151 rcar_i2c_write(priv, ICSIER, 0); 152 rcar_i2c_write(priv, ICSAR, 0); 153 rcar_i2c_write(priv, ICSCR, 0); 154 rcar_i2c_write(priv, ICSSR, 0); 155 156 /* reset master mode */ 157 rcar_i2c_write(priv, ICMIER, 0); 158 rcar_i2c_write(priv, ICMCR, 0); 159 rcar_i2c_write(priv, ICMSR, 0); 160 rcar_i2c_write(priv, ICMAR, 0); 161 } 162 163 static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open) 164 { 165 u32 val = MNRE | MALE | MSTE | MATE; /* default */ 166 167 switch (open) { 168 case RCAR_IRQ_OPEN_FOR_SEND: 169 val |= MDEE; /* default + send */ 170 break; 171 case RCAR_IRQ_OPEN_FOR_RECV: 172 val |= MDRE; /* default + read */ 173 break; 174 case RCAR_IRQ_OPEN_FOR_STOP: 175 val = MSTE; /* stop irq only */ 176 break; 177 case RCAR_IRQ_CLOSE: 178 default: 179 val = 0; /* all close */ 180 break; 181 } 182 rcar_i2c_write(priv, ICMIER, val); 183 } 184 185 static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv) 186 { 187 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv); 188 } 189 190 /* 191 * bus control functions 192 */ 193 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 194 { 195 int i; 196 197 for (i = 0; i < LOOP_TIMEOUT; i++) { 198 /* make sure that bus is not busy */ 199 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 200 return 0; 201 udelay(1); 202 } 203 204 return -EBUSY; 205 } 206 207 static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase) 208 { 209 switch (phase) { 210 case RCAR_BUS_PHASE_ADDR: 211 rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG); 212 break; 213 case RCAR_BUS_PHASE_DATA: 214 rcar_i2c_write(priv, ICMCR, MDBS | MIE); 215 break; 216 case RCAR_BUS_PHASE_STOP: 217 rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB); 218 break; 219 } 220 } 221 222 /* 223 * clock function 224 */ 225 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, 226 u32 bus_speed, 227 struct device *dev) 228 { 229 struct clk *clkp = clk_get(NULL, "peripheral_clk"); 230 u32 scgd, cdf; 231 u32 round, ick; 232 u32 scl; 233 u32 cdf_width; 234 235 if (!clkp) { 236 dev_err(dev, "there is no peripheral_clk\n"); 237 return -EIO; 238 } 239 240 switch (priv->devtype) { 241 case I2C_RCAR_H1: 242 cdf_width = 2; 243 break; 244 case I2C_RCAR_H2: 245 cdf_width = 3; 246 break; 247 default: 248 dev_err(dev, "device type error\n"); 249 return -EIO; 250 } 251 252 /* 253 * calculate SCL clock 254 * see 255 * ICCCR 256 * 257 * ick = clkp / (1 + CDF) 258 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 259 * 260 * ick : I2C internal clock < 20 MHz 261 * ticf : I2C SCL falling time = 35 ns here 262 * tr : I2C SCL rising time = 200 ns here 263 * intd : LSI internal delay = 50 ns here 264 * clkp : peripheral_clk 265 * F[] : integer up-valuation 266 */ 267 for (cdf = 0; cdf < (1 << cdf_width); cdf++) { 268 ick = clk_get_rate(clkp) / (1 + cdf); 269 if (ick < 20000000) 270 goto ick_find; 271 } 272 dev_err(dev, "there is no best CDF\n"); 273 return -EIO; 274 275 ick_find: 276 /* 277 * it is impossible to calculate large scale 278 * number on u32. separate it 279 * 280 * F[(ticf + tr + intd) * ick] 281 * = F[(35 + 200 + 50)ns * ick] 282 * = F[285 * ick / 1000000000] 283 * = F[(ick / 1000000) * 285 / 1000] 284 */ 285 round = (ick + 500000) / 1000000 * 285; 286 round = (round + 500) / 1000; 287 288 /* 289 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 290 * 291 * Calculation result (= SCL) should be less than 292 * bus_speed for hardware safety 293 */ 294 for (scgd = 0; scgd < 0x40; scgd++) { 295 scl = ick / (20 + (scgd * 8) + round); 296 if (scl <= bus_speed) 297 goto scgd_find; 298 } 299 dev_err(dev, "it is impossible to calculate best SCL\n"); 300 return -EIO; 301 302 scgd_find: 303 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 304 scl, bus_speed, clk_get_rate(clkp), round, cdf, scgd); 305 306 /* 307 * keep icccr value 308 */ 309 priv->icccr = (scgd << (cdf_width) | cdf); 310 311 return 0; 312 } 313 314 static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv) 315 { 316 rcar_i2c_write(priv, ICCCR, priv->icccr); 317 } 318 319 /* 320 * status functions 321 */ 322 static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv) 323 { 324 return rcar_i2c_read(priv, ICMSR); 325 } 326 327 #define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff) 328 static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit) 329 { 330 rcar_i2c_write(priv, ICMSR, ~bit); 331 } 332 333 /* 334 * recv/send functions 335 */ 336 static int rcar_i2c_recv(struct rcar_i2c_priv *priv) 337 { 338 rcar_i2c_set_addr(priv, 1); 339 rcar_i2c_status_clear(priv); 340 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); 341 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV); 342 343 return 0; 344 } 345 346 static int rcar_i2c_send(struct rcar_i2c_priv *priv) 347 { 348 int ret; 349 350 /* 351 * It should check bus status when send case 352 */ 353 ret = rcar_i2c_bus_barrier(priv); 354 if (ret < 0) 355 return ret; 356 357 rcar_i2c_set_addr(priv, 0); 358 rcar_i2c_status_clear(priv); 359 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); 360 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND); 361 362 return 0; 363 } 364 365 #define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE)) 366 #define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR)) 367 368 /* 369 * interrupt functions 370 */ 371 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 372 { 373 struct i2c_msg *msg = priv->msg; 374 375 /* 376 * FIXME 377 * sometimes, unknown interrupt happened. 378 * Do nothing 379 */ 380 if (!(msr & MDE)) 381 return 0; 382 383 /* 384 * If address transfer phase finished, 385 * goto data phase. 386 */ 387 if (msr & MAT) 388 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); 389 390 if (priv->pos < msg->len) { 391 /* 392 * Prepare next data to ICRXTX register. 393 * This data will go to _SHIFT_ register. 394 * 395 * * 396 * [ICRXTX] -> [SHIFT] -> [I2C bus] 397 */ 398 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 399 priv->pos++; 400 401 } else { 402 /* 403 * The last data was pushed to ICRXTX on _PREV_ empty irq. 404 * It is on _SHIFT_ register, and will sent to I2C bus. 405 * 406 * * 407 * [ICRXTX] -> [SHIFT] -> [I2C bus] 408 */ 409 410 if (priv->flags & ID_LAST_MSG) 411 /* 412 * If current msg is the _LAST_ msg, 413 * prepare stop condition here. 414 * ID_DONE will be set on STOP irq. 415 */ 416 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 417 else 418 /* 419 * If current msg is _NOT_ last msg, 420 * it doesn't call stop phase. 421 * thus, there is no STOP irq. 422 * return ID_DONE here. 423 */ 424 return ID_DONE; 425 } 426 427 rcar_i2c_send_restart(priv); 428 429 return 0; 430 } 431 432 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 433 { 434 struct i2c_msg *msg = priv->msg; 435 436 /* 437 * FIXME 438 * sometimes, unknown interrupt happened. 439 * Do nothing 440 */ 441 if (!(msr & MDR)) 442 return 0; 443 444 if (msr & MAT) { 445 /* 446 * Address transfer phase finished, 447 * but, there is no data at this point. 448 * Do nothing. 449 */ 450 } else if (priv->pos < msg->len) { 451 /* 452 * get received data 453 */ 454 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 455 priv->pos++; 456 } 457 458 /* 459 * If next received data is the _LAST_, 460 * go to STOP phase, 461 * otherwise, go to DATA phase. 462 */ 463 if (priv->pos + 1 >= msg->len) 464 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 465 else 466 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); 467 468 rcar_i2c_recv_restart(priv); 469 470 return 0; 471 } 472 473 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 474 { 475 struct rcar_i2c_priv *priv = ptr; 476 struct device *dev = rcar_i2c_priv_to_dev(priv); 477 u32 msr; 478 479 /*-------------- spin lock -----------------*/ 480 spin_lock(&priv->lock); 481 482 msr = rcar_i2c_status_get(priv); 483 484 /* 485 * Arbitration lost 486 */ 487 if (msr & MAL) { 488 /* 489 * CAUTION 490 * 491 * When arbitration lost, device become _slave_ mode. 492 */ 493 dev_dbg(dev, "Arbitration Lost\n"); 494 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); 495 goto out; 496 } 497 498 /* 499 * Stop 500 */ 501 if (msr & MST) { 502 dev_dbg(dev, "Stop\n"); 503 rcar_i2c_flags_set(priv, ID_DONE); 504 goto out; 505 } 506 507 /* 508 * Nack 509 */ 510 if (msr & MNR) { 511 dev_dbg(dev, "Nack\n"); 512 513 /* go to stop phase */ 514 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 515 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP); 516 rcar_i2c_flags_set(priv, ID_NACK); 517 goto out; 518 } 519 520 /* 521 * recv/send 522 */ 523 if (rcar_i2c_is_recv(priv)) 524 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); 525 else 526 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); 527 528 out: 529 if (rcar_i2c_flags_has(priv, ID_DONE)) { 530 rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE); 531 rcar_i2c_status_clear(priv); 532 wake_up(&priv->wait); 533 } 534 535 spin_unlock(&priv->lock); 536 /*-------------- spin unlock -----------------*/ 537 538 return IRQ_HANDLED; 539 } 540 541 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 542 struct i2c_msg *msgs, 543 int num) 544 { 545 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 546 struct device *dev = rcar_i2c_priv_to_dev(priv); 547 unsigned long flags; 548 int i, ret, timeout; 549 550 pm_runtime_get_sync(dev); 551 552 /*-------------- spin lock -----------------*/ 553 spin_lock_irqsave(&priv->lock, flags); 554 555 rcar_i2c_init(priv); 556 rcar_i2c_clock_start(priv); 557 558 spin_unlock_irqrestore(&priv->lock, flags); 559 /*-------------- spin unlock -----------------*/ 560 561 ret = -EINVAL; 562 for (i = 0; i < num; i++) { 563 /*-------------- spin lock -----------------*/ 564 spin_lock_irqsave(&priv->lock, flags); 565 566 /* init each data */ 567 priv->msg = &msgs[i]; 568 priv->pos = 0; 569 priv->flags = 0; 570 if (priv->msg == &msgs[num - 1]) 571 rcar_i2c_flags_set(priv, ID_LAST_MSG); 572 573 /* start send/recv */ 574 if (rcar_i2c_is_recv(priv)) 575 ret = rcar_i2c_recv(priv); 576 else 577 ret = rcar_i2c_send(priv); 578 579 spin_unlock_irqrestore(&priv->lock, flags); 580 /*-------------- spin unlock -----------------*/ 581 582 if (ret < 0) 583 break; 584 585 /* 586 * wait result 587 */ 588 timeout = wait_event_timeout(priv->wait, 589 rcar_i2c_flags_has(priv, ID_DONE), 590 5 * HZ); 591 if (!timeout) { 592 ret = -ETIMEDOUT; 593 break; 594 } 595 596 /* 597 * error handling 598 */ 599 if (rcar_i2c_flags_has(priv, ID_NACK)) { 600 ret = -EREMOTEIO; 601 break; 602 } 603 604 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { 605 ret = -EAGAIN; 606 break; 607 } 608 609 if (rcar_i2c_flags_has(priv, ID_IOERROR)) { 610 ret = -EIO; 611 break; 612 } 613 614 ret = i + 1; /* The number of transfer */ 615 } 616 617 pm_runtime_put(dev); 618 619 if (ret < 0) 620 dev_err(dev, "error %d : %x\n", ret, priv->flags); 621 622 return ret; 623 } 624 625 static u32 rcar_i2c_func(struct i2c_adapter *adap) 626 { 627 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 628 } 629 630 static const struct i2c_algorithm rcar_i2c_algo = { 631 .master_xfer = rcar_i2c_master_xfer, 632 .functionality = rcar_i2c_func, 633 }; 634 635 static int rcar_i2c_probe(struct platform_device *pdev) 636 { 637 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev); 638 struct rcar_i2c_priv *priv; 639 struct i2c_adapter *adap; 640 struct resource *res; 641 struct device *dev = &pdev->dev; 642 u32 bus_speed; 643 int ret; 644 645 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 646 if (!priv) { 647 dev_err(dev, "no mem for private data\n"); 648 return -ENOMEM; 649 } 650 651 bus_speed = 100000; /* default 100 kHz */ 652 if (pdata && pdata->bus_speed) 653 bus_speed = pdata->bus_speed; 654 655 priv->devtype = platform_get_device_id(pdev)->driver_data; 656 657 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); 658 if (ret < 0) 659 return ret; 660 661 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 662 priv->io = devm_ioremap_resource(dev, res); 663 if (IS_ERR(priv->io)) 664 return PTR_ERR(priv->io); 665 666 priv->irq = platform_get_irq(pdev, 0); 667 init_waitqueue_head(&priv->wait); 668 spin_lock_init(&priv->lock); 669 670 adap = &priv->adap; 671 adap->nr = pdev->id; 672 adap->algo = &rcar_i2c_algo; 673 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 674 adap->retries = 3; 675 adap->dev.parent = dev; 676 i2c_set_adapdata(adap, priv); 677 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 678 679 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, 680 dev_name(dev), priv); 681 if (ret < 0) { 682 dev_err(dev, "cannot get irq %d\n", priv->irq); 683 return ret; 684 } 685 686 ret = i2c_add_numbered_adapter(adap); 687 if (ret < 0) { 688 dev_err(dev, "reg adap failed: %d\n", ret); 689 return ret; 690 } 691 692 pm_runtime_enable(dev); 693 platform_set_drvdata(pdev, priv); 694 695 dev_info(dev, "probed\n"); 696 697 return 0; 698 } 699 700 static int rcar_i2c_remove(struct platform_device *pdev) 701 { 702 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 703 struct device *dev = &pdev->dev; 704 705 i2c_del_adapter(&priv->adap); 706 pm_runtime_disable(dev); 707 708 return 0; 709 } 710 711 static struct platform_device_id rcar_i2c_id_table[] = { 712 { "i2c-rcar", I2C_RCAR_H1 }, 713 { "i2c-rcar_h1", I2C_RCAR_H1 }, 714 { "i2c-rcar_h2", I2C_RCAR_H2 }, 715 {}, 716 }; 717 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table); 718 719 static struct platform_driver rcar_i2c_driver = { 720 .driver = { 721 .name = "i2c-rcar", 722 .owner = THIS_MODULE, 723 }, 724 .probe = rcar_i2c_probe, 725 .remove = rcar_i2c_remove, 726 .id_table = rcar_i2c_id_table, 727 }; 728 729 module_platform_driver(rcar_i2c_driver); 730 731 MODULE_LICENSE("GPL"); 732 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 733 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 734