1 /* 2 * drivers/i2c/busses/i2c-rcar.c 3 * 4 * Copyright (C) 2012 Renesas Solutions Corp. 5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 8 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 9 * 10 * This file used out-of-tree driver i2c-rcar.c 11 * Copyright (C) 2011-2012 Renesas Electronics Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 */ 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/err.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/i2c.h> 32 #include <linux/i2c/i2c-rcar.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/of_device.h> 36 #include <linux/platform_device.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/slab.h> 39 #include <linux/spinlock.h> 40 41 /* register offsets */ 42 #define ICSCR 0x00 /* slave ctrl */ 43 #define ICMCR 0x04 /* master ctrl */ 44 #define ICSSR 0x08 /* slave status */ 45 #define ICMSR 0x0C /* master status */ 46 #define ICSIER 0x10 /* slave irq enable */ 47 #define ICMIER 0x14 /* master irq enable */ 48 #define ICCCR 0x18 /* clock dividers */ 49 #define ICSAR 0x1C /* slave address */ 50 #define ICMAR 0x20 /* master address */ 51 #define ICRXTX 0x24 /* data port */ 52 53 /* ICMCR */ 54 #define MDBS (1 << 7) /* non-fifo mode switch */ 55 #define FSCL (1 << 6) /* override SCL pin */ 56 #define FSDA (1 << 5) /* override SDA pin */ 57 #define OBPC (1 << 4) /* override pins */ 58 #define MIE (1 << 3) /* master if enable */ 59 #define TSBE (1 << 2) 60 #define FSB (1 << 1) /* force stop bit */ 61 #define ESG (1 << 0) /* en startbit gen */ 62 63 /* ICMSR */ 64 #define MNR (1 << 6) /* nack received */ 65 #define MAL (1 << 5) /* arbitration lost */ 66 #define MST (1 << 4) /* sent a stop */ 67 #define MDE (1 << 3) 68 #define MDT (1 << 2) 69 #define MDR (1 << 1) 70 #define MAT (1 << 0) /* slave addr xfer done */ 71 72 /* ICMIE */ 73 #define MNRE (1 << 6) /* nack irq en */ 74 #define MALE (1 << 5) /* arblos irq en */ 75 #define MSTE (1 << 4) /* stop irq en */ 76 #define MDEE (1 << 3) 77 #define MDTE (1 << 2) 78 #define MDRE (1 << 1) 79 #define MATE (1 << 0) /* address sent irq en */ 80 81 82 enum { 83 RCAR_BUS_PHASE_ADDR, 84 RCAR_BUS_PHASE_DATA, 85 RCAR_BUS_PHASE_STOP, 86 }; 87 88 enum { 89 RCAR_IRQ_CLOSE, 90 RCAR_IRQ_OPEN_FOR_SEND, 91 RCAR_IRQ_OPEN_FOR_RECV, 92 RCAR_IRQ_OPEN_FOR_STOP, 93 }; 94 95 /* 96 * flags 97 */ 98 #define ID_LAST_MSG (1 << 0) 99 #define ID_IOERROR (1 << 1) 100 #define ID_DONE (1 << 2) 101 #define ID_ARBLOST (1 << 3) 102 #define ID_NACK (1 << 4) 103 104 enum rcar_i2c_type { 105 I2C_RCAR_GEN1, 106 I2C_RCAR_GEN2, 107 }; 108 109 struct rcar_i2c_priv { 110 void __iomem *io; 111 struct i2c_adapter adap; 112 struct i2c_msg *msg; 113 struct clk *clk; 114 115 spinlock_t lock; 116 wait_queue_head_t wait; 117 118 int pos; 119 int irq; 120 u32 icccr; 121 u32 flags; 122 enum rcar_i2c_type devtype; 123 }; 124 125 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 126 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 127 128 #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) 129 #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) 130 131 #define LOOP_TIMEOUT 1024 132 133 /* 134 * basic functions 135 */ 136 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 137 { 138 writel(val, priv->io + reg); 139 } 140 141 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 142 { 143 return readl(priv->io + reg); 144 } 145 146 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 147 { 148 /* 149 * reset slave mode. 150 * slave mode is not used on this driver 151 */ 152 rcar_i2c_write(priv, ICSIER, 0); 153 rcar_i2c_write(priv, ICSAR, 0); 154 rcar_i2c_write(priv, ICSCR, 0); 155 rcar_i2c_write(priv, ICSSR, 0); 156 157 /* reset master mode */ 158 rcar_i2c_write(priv, ICMIER, 0); 159 rcar_i2c_write(priv, ICMCR, 0); 160 rcar_i2c_write(priv, ICMSR, 0); 161 rcar_i2c_write(priv, ICMAR, 0); 162 } 163 164 static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open) 165 { 166 u32 val = MNRE | MALE | MSTE | MATE; /* default */ 167 168 switch (open) { 169 case RCAR_IRQ_OPEN_FOR_SEND: 170 val |= MDEE; /* default + send */ 171 break; 172 case RCAR_IRQ_OPEN_FOR_RECV: 173 val |= MDRE; /* default + read */ 174 break; 175 case RCAR_IRQ_OPEN_FOR_STOP: 176 val = MSTE; /* stop irq only */ 177 break; 178 case RCAR_IRQ_CLOSE: 179 default: 180 val = 0; /* all close */ 181 break; 182 } 183 rcar_i2c_write(priv, ICMIER, val); 184 } 185 186 static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv) 187 { 188 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv); 189 } 190 191 /* 192 * bus control functions 193 */ 194 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 195 { 196 int i; 197 198 for (i = 0; i < LOOP_TIMEOUT; i++) { 199 /* make sure that bus is not busy */ 200 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 201 return 0; 202 udelay(1); 203 } 204 205 return -EBUSY; 206 } 207 208 static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase) 209 { 210 switch (phase) { 211 case RCAR_BUS_PHASE_ADDR: 212 rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG); 213 break; 214 case RCAR_BUS_PHASE_DATA: 215 rcar_i2c_write(priv, ICMCR, MDBS | MIE); 216 break; 217 case RCAR_BUS_PHASE_STOP: 218 rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB); 219 break; 220 } 221 } 222 223 /* 224 * clock function 225 */ 226 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, 227 u32 bus_speed, 228 struct device *dev) 229 { 230 u32 scgd, cdf; 231 u32 round, ick; 232 u32 scl; 233 u32 cdf_width; 234 unsigned long rate; 235 236 switch (priv->devtype) { 237 case I2C_RCAR_GEN1: 238 cdf_width = 2; 239 break; 240 case I2C_RCAR_GEN2: 241 cdf_width = 3; 242 break; 243 default: 244 dev_err(dev, "device type error\n"); 245 return -EIO; 246 } 247 248 /* 249 * calculate SCL clock 250 * see 251 * ICCCR 252 * 253 * ick = clkp / (1 + CDF) 254 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 255 * 256 * ick : I2C internal clock < 20 MHz 257 * ticf : I2C SCL falling time = 35 ns here 258 * tr : I2C SCL rising time = 200 ns here 259 * intd : LSI internal delay = 50 ns here 260 * clkp : peripheral_clk 261 * F[] : integer up-valuation 262 */ 263 rate = clk_get_rate(priv->clk); 264 cdf = rate / 20000000; 265 if (cdf >= 1 << cdf_width) { 266 dev_err(dev, "Input clock %lu too high\n", rate); 267 return -EIO; 268 } 269 ick = rate / (cdf + 1); 270 271 /* 272 * it is impossible to calculate large scale 273 * number on u32. separate it 274 * 275 * F[(ticf + tr + intd) * ick] 276 * = F[(35 + 200 + 50)ns * ick] 277 * = F[285 * ick / 1000000000] 278 * = F[(ick / 1000000) * 285 / 1000] 279 */ 280 round = (ick + 500000) / 1000000 * 285; 281 round = (round + 500) / 1000; 282 283 /* 284 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 285 * 286 * Calculation result (= SCL) should be less than 287 * bus_speed for hardware safety 288 * 289 * We could use something along the lines of 290 * div = ick / (bus_speed + 1) + 1; 291 * scgd = (div - 20 - round + 7) / 8; 292 * scl = ick / (20 + (scgd * 8) + round); 293 * (not fully verified) but that would get pretty involved 294 */ 295 for (scgd = 0; scgd < 0x40; scgd++) { 296 scl = ick / (20 + (scgd * 8) + round); 297 if (scl <= bus_speed) 298 goto scgd_find; 299 } 300 dev_err(dev, "it is impossible to calculate best SCL\n"); 301 return -EIO; 302 303 scgd_find: 304 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 305 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd); 306 307 /* 308 * keep icccr value 309 */ 310 priv->icccr = scgd << cdf_width | cdf; 311 312 return 0; 313 } 314 315 static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv) 316 { 317 rcar_i2c_write(priv, ICCCR, priv->icccr); 318 } 319 320 /* 321 * status functions 322 */ 323 static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv) 324 { 325 return rcar_i2c_read(priv, ICMSR); 326 } 327 328 #define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff) 329 static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit) 330 { 331 rcar_i2c_write(priv, ICMSR, ~bit); 332 } 333 334 /* 335 * recv/send functions 336 */ 337 static int rcar_i2c_recv(struct rcar_i2c_priv *priv) 338 { 339 rcar_i2c_set_addr(priv, 1); 340 rcar_i2c_status_clear(priv); 341 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); 342 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV); 343 344 return 0; 345 } 346 347 static int rcar_i2c_send(struct rcar_i2c_priv *priv) 348 { 349 int ret; 350 351 /* 352 * It should check bus status when send case 353 */ 354 ret = rcar_i2c_bus_barrier(priv); 355 if (ret < 0) 356 return ret; 357 358 rcar_i2c_set_addr(priv, 0); 359 rcar_i2c_status_clear(priv); 360 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); 361 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND); 362 363 return 0; 364 } 365 366 #define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE)) 367 #define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR)) 368 369 /* 370 * interrupt functions 371 */ 372 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 373 { 374 struct i2c_msg *msg = priv->msg; 375 376 /* 377 * FIXME 378 * sometimes, unknown interrupt happened. 379 * Do nothing 380 */ 381 if (!(msr & MDE)) 382 return 0; 383 384 /* 385 * If address transfer phase finished, 386 * goto data phase. 387 */ 388 if (msr & MAT) 389 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); 390 391 if (priv->pos < msg->len) { 392 /* 393 * Prepare next data to ICRXTX register. 394 * This data will go to _SHIFT_ register. 395 * 396 * * 397 * [ICRXTX] -> [SHIFT] -> [I2C bus] 398 */ 399 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 400 priv->pos++; 401 402 } else { 403 /* 404 * The last data was pushed to ICRXTX on _PREV_ empty irq. 405 * It is on _SHIFT_ register, and will sent to I2C bus. 406 * 407 * * 408 * [ICRXTX] -> [SHIFT] -> [I2C bus] 409 */ 410 411 if (priv->flags & ID_LAST_MSG) 412 /* 413 * If current msg is the _LAST_ msg, 414 * prepare stop condition here. 415 * ID_DONE will be set on STOP irq. 416 */ 417 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 418 else 419 /* 420 * If current msg is _NOT_ last msg, 421 * it doesn't call stop phase. 422 * thus, there is no STOP irq. 423 * return ID_DONE here. 424 */ 425 return ID_DONE; 426 } 427 428 rcar_i2c_send_restart(priv); 429 430 return 0; 431 } 432 433 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 434 { 435 struct i2c_msg *msg = priv->msg; 436 437 /* 438 * FIXME 439 * sometimes, unknown interrupt happened. 440 * Do nothing 441 */ 442 if (!(msr & MDR)) 443 return 0; 444 445 if (msr & MAT) { 446 /* 447 * Address transfer phase finished, 448 * but, there is no data at this point. 449 * Do nothing. 450 */ 451 } else if (priv->pos < msg->len) { 452 /* 453 * get received data 454 */ 455 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 456 priv->pos++; 457 } 458 459 /* 460 * If next received data is the _LAST_, 461 * go to STOP phase, 462 * otherwise, go to DATA phase. 463 */ 464 if (priv->pos + 1 >= msg->len) 465 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 466 else 467 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); 468 469 rcar_i2c_recv_restart(priv); 470 471 return 0; 472 } 473 474 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 475 { 476 struct rcar_i2c_priv *priv = ptr; 477 struct device *dev = rcar_i2c_priv_to_dev(priv); 478 u32 msr; 479 480 /*-------------- spin lock -----------------*/ 481 spin_lock(&priv->lock); 482 483 msr = rcar_i2c_status_get(priv); 484 485 /* 486 * Arbitration lost 487 */ 488 if (msr & MAL) { 489 /* 490 * CAUTION 491 * 492 * When arbitration lost, device become _slave_ mode. 493 */ 494 dev_dbg(dev, "Arbitration Lost\n"); 495 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); 496 goto out; 497 } 498 499 /* 500 * Stop 501 */ 502 if (msr & MST) { 503 dev_dbg(dev, "Stop\n"); 504 rcar_i2c_flags_set(priv, ID_DONE); 505 goto out; 506 } 507 508 /* 509 * Nack 510 */ 511 if (msr & MNR) { 512 dev_dbg(dev, "Nack\n"); 513 514 /* go to stop phase */ 515 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 516 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP); 517 rcar_i2c_flags_set(priv, ID_NACK); 518 goto out; 519 } 520 521 /* 522 * recv/send 523 */ 524 if (rcar_i2c_is_recv(priv)) 525 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); 526 else 527 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); 528 529 out: 530 if (rcar_i2c_flags_has(priv, ID_DONE)) { 531 rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE); 532 rcar_i2c_status_clear(priv); 533 wake_up(&priv->wait); 534 } 535 536 spin_unlock(&priv->lock); 537 /*-------------- spin unlock -----------------*/ 538 539 return IRQ_HANDLED; 540 } 541 542 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 543 struct i2c_msg *msgs, 544 int num) 545 { 546 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 547 struct device *dev = rcar_i2c_priv_to_dev(priv); 548 unsigned long flags; 549 int i, ret, timeout; 550 551 pm_runtime_get_sync(dev); 552 553 /*-------------- spin lock -----------------*/ 554 spin_lock_irqsave(&priv->lock, flags); 555 556 rcar_i2c_init(priv); 557 rcar_i2c_clock_start(priv); 558 559 spin_unlock_irqrestore(&priv->lock, flags); 560 /*-------------- spin unlock -----------------*/ 561 562 ret = -EINVAL; 563 for (i = 0; i < num; i++) { 564 /*-------------- spin lock -----------------*/ 565 spin_lock_irqsave(&priv->lock, flags); 566 567 /* init each data */ 568 priv->msg = &msgs[i]; 569 priv->pos = 0; 570 priv->flags = 0; 571 if (priv->msg == &msgs[num - 1]) 572 rcar_i2c_flags_set(priv, ID_LAST_MSG); 573 574 /* start send/recv */ 575 if (rcar_i2c_is_recv(priv)) 576 ret = rcar_i2c_recv(priv); 577 else 578 ret = rcar_i2c_send(priv); 579 580 spin_unlock_irqrestore(&priv->lock, flags); 581 /*-------------- spin unlock -----------------*/ 582 583 if (ret < 0) 584 break; 585 586 /* 587 * wait result 588 */ 589 timeout = wait_event_timeout(priv->wait, 590 rcar_i2c_flags_has(priv, ID_DONE), 591 5 * HZ); 592 if (!timeout) { 593 ret = -ETIMEDOUT; 594 break; 595 } 596 597 /* 598 * error handling 599 */ 600 if (rcar_i2c_flags_has(priv, ID_NACK)) { 601 ret = -ENXIO; 602 break; 603 } 604 605 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { 606 ret = -EAGAIN; 607 break; 608 } 609 610 if (rcar_i2c_flags_has(priv, ID_IOERROR)) { 611 ret = -EIO; 612 break; 613 } 614 615 ret = i + 1; /* The number of transfer */ 616 } 617 618 pm_runtime_put(dev); 619 620 if (ret < 0 && ret != -ENXIO) 621 dev_err(dev, "error %d : %x\n", ret, priv->flags); 622 623 return ret; 624 } 625 626 static u32 rcar_i2c_func(struct i2c_adapter *adap) 627 { 628 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 629 } 630 631 static const struct i2c_algorithm rcar_i2c_algo = { 632 .master_xfer = rcar_i2c_master_xfer, 633 .functionality = rcar_i2c_func, 634 }; 635 636 static const struct of_device_id rcar_i2c_dt_ids[] = { 637 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, 638 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 639 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 640 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 641 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 642 {}, 643 }; 644 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 645 646 static int rcar_i2c_probe(struct platform_device *pdev) 647 { 648 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev); 649 struct rcar_i2c_priv *priv; 650 struct i2c_adapter *adap; 651 struct resource *res; 652 struct device *dev = &pdev->dev; 653 u32 bus_speed; 654 int ret; 655 656 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 657 if (!priv) { 658 dev_err(dev, "no mem for private data\n"); 659 return -ENOMEM; 660 } 661 662 priv->clk = devm_clk_get(dev, NULL); 663 if (IS_ERR(priv->clk)) { 664 dev_err(dev, "cannot get clock\n"); 665 return PTR_ERR(priv->clk); 666 } 667 668 bus_speed = 100000; /* default 100 kHz */ 669 ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed); 670 if (ret < 0 && pdata && pdata->bus_speed) 671 bus_speed = pdata->bus_speed; 672 673 if (pdev->dev.of_node) 674 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids, 675 dev)->data; 676 else 677 priv->devtype = platform_get_device_id(pdev)->driver_data; 678 679 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); 680 if (ret < 0) 681 return ret; 682 683 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 684 priv->io = devm_ioremap_resource(dev, res); 685 if (IS_ERR(priv->io)) 686 return PTR_ERR(priv->io); 687 688 priv->irq = platform_get_irq(pdev, 0); 689 init_waitqueue_head(&priv->wait); 690 spin_lock_init(&priv->lock); 691 692 adap = &priv->adap; 693 adap->nr = pdev->id; 694 adap->algo = &rcar_i2c_algo; 695 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED; 696 adap->retries = 3; 697 adap->dev.parent = dev; 698 adap->dev.of_node = dev->of_node; 699 i2c_set_adapdata(adap, priv); 700 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 701 702 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, 703 dev_name(dev), priv); 704 if (ret < 0) { 705 dev_err(dev, "cannot get irq %d\n", priv->irq); 706 return ret; 707 } 708 709 ret = i2c_add_numbered_adapter(adap); 710 if (ret < 0) { 711 dev_err(dev, "reg adap failed: %d\n", ret); 712 return ret; 713 } 714 715 pm_runtime_enable(dev); 716 platform_set_drvdata(pdev, priv); 717 718 dev_info(dev, "probed\n"); 719 720 return 0; 721 } 722 723 static int rcar_i2c_remove(struct platform_device *pdev) 724 { 725 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 726 struct device *dev = &pdev->dev; 727 728 i2c_del_adapter(&priv->adap); 729 pm_runtime_disable(dev); 730 731 return 0; 732 } 733 734 static struct platform_device_id rcar_i2c_id_table[] = { 735 { "i2c-rcar", I2C_RCAR_GEN1 }, 736 { "i2c-rcar_gen1", I2C_RCAR_GEN1 }, 737 { "i2c-rcar_gen2", I2C_RCAR_GEN2 }, 738 {}, 739 }; 740 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table); 741 742 static struct platform_driver rcar_i2c_driver = { 743 .driver = { 744 .name = "i2c-rcar", 745 .owner = THIS_MODULE, 746 .of_match_table = rcar_i2c_dt_ids, 747 }, 748 .probe = rcar_i2c_probe, 749 .remove = rcar_i2c_remove, 750 .id_table = rcar_i2c_id_table, 751 }; 752 753 module_platform_driver(rcar_i2c_driver); 754 755 MODULE_LICENSE("GPL"); 756 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 757 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 758