1 /* 2 * Driver for the Renesas R-Car I2C unit 3 * 4 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> 5 * Copyright (C) 2011-2015 Renesas Electronics Corporation 6 * 7 * Copyright (C) 2012-14 Renesas Solutions Corp. 8 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 9 * 10 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 11 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; version 2 of the License. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 #include <linux/bitops.h> 23 #include <linux/clk.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/interrupt.h> 29 #include <linux/io.h> 30 #include <linux/i2c.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/of_device.h> 34 #include <linux/platform_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/reset.h> 37 #include <linux/slab.h> 38 39 /* register offsets */ 40 #define ICSCR 0x00 /* slave ctrl */ 41 #define ICMCR 0x04 /* master ctrl */ 42 #define ICSSR 0x08 /* slave status */ 43 #define ICMSR 0x0C /* master status */ 44 #define ICSIER 0x10 /* slave irq enable */ 45 #define ICMIER 0x14 /* master irq enable */ 46 #define ICCCR 0x18 /* clock dividers */ 47 #define ICSAR 0x1C /* slave address */ 48 #define ICMAR 0x20 /* master address */ 49 #define ICRXTX 0x24 /* data port */ 50 #define ICDMAER 0x3c /* DMA enable */ 51 #define ICFBSCR 0x38 /* first bit setup cycle */ 52 53 /* ICSCR */ 54 #define SDBS (1 << 3) /* slave data buffer select */ 55 #define SIE (1 << 2) /* slave interface enable */ 56 #define GCAE (1 << 1) /* general call address enable */ 57 #define FNA (1 << 0) /* forced non acknowledgment */ 58 59 /* ICMCR */ 60 #define MDBS (1 << 7) /* non-fifo mode switch */ 61 #define FSCL (1 << 6) /* override SCL pin */ 62 #define FSDA (1 << 5) /* override SDA pin */ 63 #define OBPC (1 << 4) /* override pins */ 64 #define MIE (1 << 3) /* master if enable */ 65 #define TSBE (1 << 2) 66 #define FSB (1 << 1) /* force stop bit */ 67 #define ESG (1 << 0) /* enable start bit gen */ 68 69 /* ICSSR (also for ICSIER) */ 70 #define GCAR (1 << 6) /* general call received */ 71 #define STM (1 << 5) /* slave transmit mode */ 72 #define SSR (1 << 4) /* stop received */ 73 #define SDE (1 << 3) /* slave data empty */ 74 #define SDT (1 << 2) /* slave data transmitted */ 75 #define SDR (1 << 1) /* slave data received */ 76 #define SAR (1 << 0) /* slave addr received */ 77 78 /* ICMSR (also for ICMIE) */ 79 #define MNR (1 << 6) /* nack received */ 80 #define MAL (1 << 5) /* arbitration lost */ 81 #define MST (1 << 4) /* sent a stop */ 82 #define MDE (1 << 3) 83 #define MDT (1 << 2) 84 #define MDR (1 << 1) 85 #define MAT (1 << 0) /* slave addr xfer done */ 86 87 /* ICDMAER */ 88 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 89 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 90 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 91 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 92 93 /* ICFBSCR */ 94 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */ 95 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 96 97 98 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 99 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 100 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) 101 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 102 103 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 104 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 105 #define RCAR_IRQ_STOP (MST) 106 107 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 108 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 109 110 #define ID_LAST_MSG (1 << 0) 111 #define ID_FIRST_MSG (1 << 1) 112 #define ID_DONE (1 << 2) 113 #define ID_ARBLOST (1 << 3) 114 #define ID_NACK (1 << 4) 115 /* persistent flags */ 116 #define ID_P_REP_AFTER_RD BIT(29) 117 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 118 #define ID_P_PM_BLOCKED BIT(31) 119 #define ID_P_MASK GENMASK(31, 29) 120 121 enum rcar_i2c_type { 122 I2C_RCAR_GEN1, 123 I2C_RCAR_GEN2, 124 I2C_RCAR_GEN3, 125 }; 126 127 struct rcar_i2c_priv { 128 void __iomem *io; 129 struct i2c_adapter adap; 130 struct i2c_msg *msg; 131 int msgs_left; 132 struct clk *clk; 133 134 wait_queue_head_t wait; 135 136 int pos; 137 u32 icccr; 138 u32 flags; 139 u8 recovery_icmcr; /* protected by adapter lock */ 140 enum rcar_i2c_type devtype; 141 struct i2c_client *slave; 142 143 struct resource *res; 144 struct dma_chan *dma_tx; 145 struct dma_chan *dma_rx; 146 struct scatterlist sg; 147 enum dma_data_direction dma_direction; 148 149 struct reset_control *rstc; 150 }; 151 152 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 153 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 154 155 #define LOOP_TIMEOUT 1024 156 157 158 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 159 { 160 writel(val, priv->io + reg); 161 } 162 163 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 164 { 165 return readl(priv->io + reg); 166 } 167 168 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 169 { 170 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 171 172 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 173 174 }; 175 176 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 177 { 178 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 179 180 if (val) 181 priv->recovery_icmcr |= FSCL; 182 else 183 priv->recovery_icmcr &= ~FSCL; 184 185 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 186 }; 187 188 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 189 { 190 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 191 192 if (val) 193 priv->recovery_icmcr |= FSDA; 194 else 195 priv->recovery_icmcr &= ~FSDA; 196 197 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 198 }; 199 200 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 201 { 202 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 203 204 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 205 206 }; 207 208 static struct i2c_bus_recovery_info rcar_i2c_bri = { 209 .get_scl = rcar_i2c_get_scl, 210 .set_scl = rcar_i2c_set_scl, 211 .set_sda = rcar_i2c_set_sda, 212 .get_bus_free = rcar_i2c_get_bus_free, 213 .recover_bus = i2c_generic_scl_recovery, 214 }; 215 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 216 { 217 /* reset master mode */ 218 rcar_i2c_write(priv, ICMIER, 0); 219 rcar_i2c_write(priv, ICMCR, MDBS); 220 rcar_i2c_write(priv, ICMSR, 0); 221 /* start clock */ 222 rcar_i2c_write(priv, ICCCR, priv->icccr); 223 } 224 225 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 226 { 227 int i; 228 229 for (i = 0; i < LOOP_TIMEOUT; i++) { 230 /* make sure that bus is not busy */ 231 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 232 return 0; 233 udelay(1); 234 } 235 236 /* Waiting did not help, try to recover */ 237 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 238 return i2c_recover_bus(&priv->adap); 239 } 240 241 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) 242 { 243 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 244 unsigned long rate; 245 struct device *dev = rcar_i2c_priv_to_dev(priv); 246 247 /* Fall back to previously used values if not supplied */ 248 t->bus_freq_hz = t->bus_freq_hz ?: 100000; 249 t->scl_fall_ns = t->scl_fall_ns ?: 35; 250 t->scl_rise_ns = t->scl_rise_ns ?: 200; 251 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; 252 253 switch (priv->devtype) { 254 case I2C_RCAR_GEN1: 255 cdf_width = 2; 256 break; 257 case I2C_RCAR_GEN2: 258 case I2C_RCAR_GEN3: 259 cdf_width = 3; 260 break; 261 default: 262 dev_err(dev, "device type error\n"); 263 return -EIO; 264 } 265 266 /* 267 * calculate SCL clock 268 * see 269 * ICCCR 270 * 271 * ick = clkp / (1 + CDF) 272 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 273 * 274 * ick : I2C internal clock < 20 MHz 275 * ticf : I2C SCL falling time 276 * tr : I2C SCL rising time 277 * intd : LSI internal delay 278 * clkp : peripheral_clk 279 * F[] : integer up-valuation 280 */ 281 rate = clk_get_rate(priv->clk); 282 cdf = rate / 20000000; 283 if (cdf >= 1U << cdf_width) { 284 dev_err(dev, "Input clock %lu too high\n", rate); 285 return -EIO; 286 } 287 ick = rate / (cdf + 1); 288 289 /* 290 * it is impossible to calculate large scale 291 * number on u32. separate it 292 * 293 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 294 * = F[sum * ick / 1000000000] 295 * = F[(ick / 1000000) * sum / 1000] 296 */ 297 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; 298 round = (ick + 500000) / 1000000 * sum; 299 round = (round + 500) / 1000; 300 301 /* 302 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 303 * 304 * Calculation result (= SCL) should be less than 305 * bus_speed for hardware safety 306 * 307 * We could use something along the lines of 308 * div = ick / (bus_speed + 1) + 1; 309 * scgd = (div - 20 - round + 7) / 8; 310 * scl = ick / (20 + (scgd * 8) + round); 311 * (not fully verified) but that would get pretty involved 312 */ 313 for (scgd = 0; scgd < 0x40; scgd++) { 314 scl = ick / (20 + (scgd * 8) + round); 315 if (scl <= t->bus_freq_hz) 316 goto scgd_find; 317 } 318 dev_err(dev, "it is impossible to calculate best SCL\n"); 319 return -EIO; 320 321 scgd_find: 322 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 323 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); 324 325 /* keep icccr value */ 326 priv->icccr = scgd << cdf_width | cdf; 327 328 return 0; 329 } 330 331 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 332 { 333 int read = !!rcar_i2c_is_recv(priv); 334 335 priv->pos = 0; 336 if (priv->msgs_left == 1) 337 priv->flags |= ID_LAST_MSG; 338 339 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 340 /* 341 * We don't have a test case but the HW engineers say that the write order 342 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 343 * it didn't cause a drawback for me, let's rather be safe than sorry. 344 */ 345 if (priv->flags & ID_FIRST_MSG) { 346 rcar_i2c_write(priv, ICMSR, 0); 347 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 348 } else { 349 if (priv->flags & ID_P_REP_AFTER_RD) 350 priv->flags &= ~ID_P_REP_AFTER_RD; 351 else 352 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 353 rcar_i2c_write(priv, ICMSR, 0); 354 } 355 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 356 } 357 358 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 359 { 360 priv->msg++; 361 priv->msgs_left--; 362 priv->flags &= ID_P_MASK; 363 rcar_i2c_prepare_msg(priv); 364 } 365 366 /* 367 * interrupt functions 368 */ 369 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 370 { 371 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 372 ? priv->dma_rx : priv->dma_tx; 373 374 /* Disable DMA Master Received/Transmitted */ 375 rcar_i2c_write(priv, ICDMAER, 0); 376 377 /* Reset default delay */ 378 rcar_i2c_write(priv, ICFBSCR, TCYC06); 379 380 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 381 sg_dma_len(&priv->sg), priv->dma_direction); 382 383 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 384 if (priv->devtype == I2C_RCAR_GEN3 && 385 priv->dma_direction == DMA_FROM_DEVICE) 386 priv->flags |= ID_P_NO_RXDMA; 387 388 priv->dma_direction = DMA_NONE; 389 } 390 391 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 392 { 393 if (priv->dma_direction == DMA_NONE) 394 return; 395 else if (priv->dma_direction == DMA_FROM_DEVICE) 396 dmaengine_terminate_all(priv->dma_rx); 397 else if (priv->dma_direction == DMA_TO_DEVICE) 398 dmaengine_terminate_all(priv->dma_tx); 399 400 rcar_i2c_dma_unmap(priv); 401 } 402 403 static void rcar_i2c_dma_callback(void *data) 404 { 405 struct rcar_i2c_priv *priv = data; 406 407 priv->pos += sg_dma_len(&priv->sg); 408 409 rcar_i2c_dma_unmap(priv); 410 } 411 412 static void rcar_i2c_dma(struct rcar_i2c_priv *priv) 413 { 414 struct device *dev = rcar_i2c_priv_to_dev(priv); 415 struct i2c_msg *msg = priv->msg; 416 bool read = msg->flags & I2C_M_RD; 417 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 418 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 419 struct dma_async_tx_descriptor *txdesc; 420 dma_addr_t dma_addr; 421 dma_cookie_t cookie; 422 unsigned char *buf; 423 int len; 424 425 /* Do various checks to see if DMA is feasible at all */ 426 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) || 427 (read && priv->flags & ID_P_NO_RXDMA)) 428 return; 429 430 if (read) { 431 /* 432 * The last two bytes needs to be fetched using PIO in 433 * order for the STOP phase to work. 434 */ 435 buf = priv->msg->buf; 436 len = priv->msg->len - 2; 437 } else { 438 /* 439 * First byte in message was sent using PIO. 440 */ 441 buf = priv->msg->buf + 1; 442 len = priv->msg->len - 1; 443 } 444 445 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 446 if (dma_mapping_error(chan->device->dev, dma_addr)) { 447 dev_dbg(dev, "dma map failed, using PIO\n"); 448 return; 449 } 450 451 sg_dma_len(&priv->sg) = len; 452 sg_dma_address(&priv->sg) = dma_addr; 453 454 priv->dma_direction = dir; 455 456 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 457 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 458 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 459 if (!txdesc) { 460 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 461 rcar_i2c_cleanup_dma(priv); 462 return; 463 } 464 465 txdesc->callback = rcar_i2c_dma_callback; 466 txdesc->callback_param = priv; 467 468 cookie = dmaengine_submit(txdesc); 469 if (dma_submit_error(cookie)) { 470 dev_dbg(dev, "submitting dma failed, using PIO\n"); 471 rcar_i2c_cleanup_dma(priv); 472 return; 473 } 474 475 /* Set delay for DMA operations */ 476 rcar_i2c_write(priv, ICFBSCR, TCYC17); 477 478 /* Enable DMA Master Received/Transmitted */ 479 if (read) 480 rcar_i2c_write(priv, ICDMAER, RMDMAE); 481 else 482 rcar_i2c_write(priv, ICDMAER, TMDMAE); 483 484 dma_async_issue_pending(chan); 485 } 486 487 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 488 { 489 struct i2c_msg *msg = priv->msg; 490 491 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 492 if (!(msr & MDE)) 493 return; 494 495 if (priv->pos < msg->len) { 496 /* 497 * Prepare next data to ICRXTX register. 498 * This data will go to _SHIFT_ register. 499 * 500 * * 501 * [ICRXTX] -> [SHIFT] -> [I2C bus] 502 */ 503 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 504 priv->pos++; 505 506 /* 507 * Try to use DMA to transmit the rest of the data if 508 * address transfer phase just finished. 509 */ 510 if (msr & MAT) 511 rcar_i2c_dma(priv); 512 } else { 513 /* 514 * The last data was pushed to ICRXTX on _PREV_ empty irq. 515 * It is on _SHIFT_ register, and will sent to I2C bus. 516 * 517 * * 518 * [ICRXTX] -> [SHIFT] -> [I2C bus] 519 */ 520 521 if (priv->flags & ID_LAST_MSG) { 522 /* 523 * If current msg is the _LAST_ msg, 524 * prepare stop condition here. 525 * ID_DONE will be set on STOP irq. 526 */ 527 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 528 } else { 529 rcar_i2c_next_msg(priv); 530 return; 531 } 532 } 533 534 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 535 } 536 537 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 538 { 539 struct i2c_msg *msg = priv->msg; 540 541 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 542 if (!(msr & MDR)) 543 return; 544 545 if (msr & MAT) { 546 /* 547 * Address transfer phase finished, but no data at this point. 548 * Try to use DMA to receive data. 549 */ 550 rcar_i2c_dma(priv); 551 } else if (priv->pos < msg->len) { 552 /* get received data */ 553 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 554 priv->pos++; 555 } 556 557 /* If next received data is the _LAST_, go to new phase. */ 558 if (priv->pos + 1 == msg->len) { 559 if (priv->flags & ID_LAST_MSG) { 560 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 561 } else { 562 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 563 priv->flags |= ID_P_REP_AFTER_RD; 564 } 565 } 566 567 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 568 rcar_i2c_next_msg(priv); 569 else 570 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 571 } 572 573 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 574 { 575 u32 ssr_raw, ssr_filtered; 576 u8 value; 577 578 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 579 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 580 581 if (!ssr_filtered) 582 return false; 583 584 /* address detected */ 585 if (ssr_filtered & SAR) { 586 /* read or write request */ 587 if (ssr_raw & STM) { 588 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 589 rcar_i2c_write(priv, ICRXTX, value); 590 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 591 } else { 592 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 593 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 594 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 595 } 596 597 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); 598 } 599 600 /* master sent stop */ 601 if (ssr_filtered & SSR) { 602 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 603 rcar_i2c_write(priv, ICSIER, SAR | SSR); 604 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 605 } 606 607 /* master wants to write to us */ 608 if (ssr_filtered & SDR) { 609 int ret; 610 611 value = rcar_i2c_read(priv, ICRXTX); 612 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 613 /* Send NACK in case of error */ 614 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 615 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 616 } 617 618 /* master wants to read from us */ 619 if (ssr_filtered & SDE) { 620 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 621 rcar_i2c_write(priv, ICRXTX, value); 622 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 623 } 624 625 return true; 626 } 627 628 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 629 { 630 struct rcar_i2c_priv *priv = ptr; 631 u32 msr, val; 632 633 /* Clear START or STOP immediately, except for REPSTART after read */ 634 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) { 635 val = rcar_i2c_read(priv, ICMCR); 636 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); 637 } 638 639 msr = rcar_i2c_read(priv, ICMSR); 640 641 /* Only handle interrupts that are currently enabled */ 642 msr &= rcar_i2c_read(priv, ICMIER); 643 if (!msr) { 644 if (rcar_i2c_slave_irq(priv)) 645 return IRQ_HANDLED; 646 647 return IRQ_NONE; 648 } 649 650 /* Arbitration lost */ 651 if (msr & MAL) { 652 priv->flags |= ID_DONE | ID_ARBLOST; 653 goto out; 654 } 655 656 /* Nack */ 657 if (msr & MNR) { 658 /* HW automatically sends STOP after received NACK */ 659 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 660 priv->flags |= ID_NACK; 661 goto out; 662 } 663 664 /* Stop */ 665 if (msr & MST) { 666 priv->msgs_left--; /* The last message also made it */ 667 priv->flags |= ID_DONE; 668 goto out; 669 } 670 671 if (rcar_i2c_is_recv(priv)) 672 rcar_i2c_irq_recv(priv, msr); 673 else 674 rcar_i2c_irq_send(priv, msr); 675 676 out: 677 if (priv->flags & ID_DONE) { 678 rcar_i2c_write(priv, ICMIER, 0); 679 rcar_i2c_write(priv, ICMSR, 0); 680 wake_up(&priv->wait); 681 } 682 683 return IRQ_HANDLED; 684 } 685 686 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 687 enum dma_transfer_direction dir, 688 dma_addr_t port_addr) 689 { 690 struct dma_chan *chan; 691 struct dma_slave_config cfg; 692 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 693 int ret; 694 695 chan = dma_request_chan(dev, chan_name); 696 if (IS_ERR(chan)) { 697 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 698 chan_name, PTR_ERR(chan)); 699 return chan; 700 } 701 702 memset(&cfg, 0, sizeof(cfg)); 703 cfg.direction = dir; 704 if (dir == DMA_MEM_TO_DEV) { 705 cfg.dst_addr = port_addr; 706 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 707 } else { 708 cfg.src_addr = port_addr; 709 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 710 } 711 712 ret = dmaengine_slave_config(chan, &cfg); 713 if (ret) { 714 dev_dbg(dev, "slave_config failed for %s (%d)\n", 715 chan_name, ret); 716 dma_release_channel(chan); 717 return ERR_PTR(ret); 718 } 719 720 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 721 return chan; 722 } 723 724 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 725 struct i2c_msg *msg) 726 { 727 struct device *dev = rcar_i2c_priv_to_dev(priv); 728 bool read; 729 struct dma_chan *chan; 730 enum dma_transfer_direction dir; 731 732 read = msg->flags & I2C_M_RD; 733 734 chan = read ? priv->dma_rx : priv->dma_tx; 735 if (PTR_ERR(chan) != -EPROBE_DEFER) 736 return; 737 738 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 739 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 740 741 if (read) 742 priv->dma_rx = chan; 743 else 744 priv->dma_tx = chan; 745 } 746 747 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 748 { 749 if (!IS_ERR(priv->dma_tx)) { 750 dma_release_channel(priv->dma_tx); 751 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 752 } 753 754 if (!IS_ERR(priv->dma_rx)) { 755 dma_release_channel(priv->dma_rx); 756 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 757 } 758 } 759 760 /* I2C is a special case, we need to poll the status of a reset */ 761 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 762 { 763 int i, ret; 764 765 ret = reset_control_reset(priv->rstc); 766 if (ret) 767 return ret; 768 769 for (i = 0; i < LOOP_TIMEOUT; i++) { 770 ret = reset_control_status(priv->rstc); 771 if (ret == 0) 772 return 0; 773 udelay(1); 774 } 775 776 return -ETIMEDOUT; 777 } 778 779 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 780 struct i2c_msg *msgs, 781 int num) 782 { 783 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 784 struct device *dev = rcar_i2c_priv_to_dev(priv); 785 int i, ret; 786 long time_left; 787 788 pm_runtime_get_sync(dev); 789 790 /* Gen3 needs a reset before allowing RXDMA once */ 791 if (priv->devtype == I2C_RCAR_GEN3) { 792 priv->flags |= ID_P_NO_RXDMA; 793 if (!IS_ERR(priv->rstc)) { 794 ret = rcar_i2c_do_reset(priv); 795 if (ret == 0) 796 priv->flags &= ~ID_P_NO_RXDMA; 797 } 798 } 799 800 rcar_i2c_init(priv); 801 802 ret = rcar_i2c_bus_barrier(priv); 803 if (ret < 0) 804 goto out; 805 806 for (i = 0; i < num; i++) 807 rcar_i2c_request_dma(priv, msgs + i); 808 809 /* init first message */ 810 priv->msg = msgs; 811 priv->msgs_left = num; 812 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 813 rcar_i2c_prepare_msg(priv); 814 815 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 816 num * adap->timeout); 817 if (!time_left) { 818 rcar_i2c_cleanup_dma(priv); 819 rcar_i2c_init(priv); 820 ret = -ETIMEDOUT; 821 } else if (priv->flags & ID_NACK) { 822 ret = -ENXIO; 823 } else if (priv->flags & ID_ARBLOST) { 824 ret = -EAGAIN; 825 } else { 826 ret = num - priv->msgs_left; /* The number of transfer */ 827 } 828 out: 829 pm_runtime_put(dev); 830 831 if (ret < 0 && ret != -ENXIO) 832 dev_err(dev, "error %d : %x\n", ret, priv->flags); 833 834 return ret; 835 } 836 837 static int rcar_reg_slave(struct i2c_client *slave) 838 { 839 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 840 841 if (priv->slave) 842 return -EBUSY; 843 844 if (slave->flags & I2C_CLIENT_TEN) 845 return -EAFNOSUPPORT; 846 847 /* Keep device active for slave address detection logic */ 848 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 849 850 priv->slave = slave; 851 rcar_i2c_write(priv, ICSAR, slave->addr); 852 rcar_i2c_write(priv, ICSSR, 0); 853 rcar_i2c_write(priv, ICSIER, SAR | SSR); 854 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 855 856 return 0; 857 } 858 859 static int rcar_unreg_slave(struct i2c_client *slave) 860 { 861 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 862 863 WARN_ON(!priv->slave); 864 865 rcar_i2c_write(priv, ICSIER, 0); 866 rcar_i2c_write(priv, ICSCR, 0); 867 868 priv->slave = NULL; 869 870 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 871 872 return 0; 873 } 874 875 static u32 rcar_i2c_func(struct i2c_adapter *adap) 876 { 877 /* 878 * This HW can't do: 879 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 880 * I2C_M_NOSTART (automatically sends address after START) 881 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 882 */ 883 return I2C_FUNC_I2C | I2C_FUNC_SLAVE | 884 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 885 } 886 887 static const struct i2c_algorithm rcar_i2c_algo = { 888 .master_xfer = rcar_i2c_master_xfer, 889 .functionality = rcar_i2c_func, 890 .reg_slave = rcar_reg_slave, 891 .unreg_slave = rcar_unreg_slave, 892 }; 893 894 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 895 .flags = I2C_AQ_NO_ZERO_LEN, 896 }; 897 898 static const struct of_device_id rcar_i2c_dt_ids[] = { 899 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 900 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 901 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 902 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 903 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 904 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 905 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 906 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 907 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 908 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 909 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 910 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 911 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 912 {}, 913 }; 914 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 915 916 static int rcar_i2c_probe(struct platform_device *pdev) 917 { 918 struct rcar_i2c_priv *priv; 919 struct i2c_adapter *adap; 920 struct device *dev = &pdev->dev; 921 struct i2c_timings i2c_t; 922 int irq, ret; 923 924 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 925 if (!priv) 926 return -ENOMEM; 927 928 priv->clk = devm_clk_get(dev, NULL); 929 if (IS_ERR(priv->clk)) { 930 dev_err(dev, "cannot get clock\n"); 931 return PTR_ERR(priv->clk); 932 } 933 934 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 935 936 priv->io = devm_ioremap_resource(dev, priv->res); 937 if (IS_ERR(priv->io)) 938 return PTR_ERR(priv->io); 939 940 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 941 init_waitqueue_head(&priv->wait); 942 943 adap = &priv->adap; 944 adap->nr = pdev->id; 945 adap->algo = &rcar_i2c_algo; 946 adap->class = I2C_CLASS_DEPRECATED; 947 adap->retries = 3; 948 adap->dev.parent = dev; 949 adap->dev.of_node = dev->of_node; 950 adap->bus_recovery_info = &rcar_i2c_bri; 951 adap->quirks = &rcar_i2c_quirks; 952 i2c_set_adapdata(adap, priv); 953 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 954 955 i2c_parse_fw_timings(dev, &i2c_t, false); 956 957 /* Init DMA */ 958 sg_init_table(&priv->sg, 1); 959 priv->dma_direction = DMA_NONE; 960 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 961 962 /* Activate device for clock calculation */ 963 pm_runtime_enable(dev); 964 pm_runtime_get_sync(dev); 965 ret = rcar_i2c_clock_calculate(priv, &i2c_t); 966 if (ret < 0) 967 goto out_pm_put; 968 969 if (priv->devtype == I2C_RCAR_GEN3) { 970 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 971 if (!IS_ERR(priv->rstc)) { 972 ret = reset_control_status(priv->rstc); 973 if (ret < 0) 974 priv->rstc = ERR_PTR(-ENOTSUPP); 975 } 976 } 977 978 /* Stay always active when multi-master to keep arbitration working */ 979 if (of_property_read_bool(dev->of_node, "multi-master")) 980 priv->flags |= ID_P_PM_BLOCKED; 981 else 982 pm_runtime_put(dev); 983 984 985 irq = platform_get_irq(pdev, 0); 986 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); 987 if (ret < 0) { 988 dev_err(dev, "cannot get irq %d\n", irq); 989 goto out_pm_disable; 990 } 991 992 platform_set_drvdata(pdev, priv); 993 994 ret = i2c_add_numbered_adapter(adap); 995 if (ret < 0) 996 goto out_pm_disable; 997 998 dev_info(dev, "probed\n"); 999 1000 return 0; 1001 1002 out_pm_put: 1003 pm_runtime_put(dev); 1004 out_pm_disable: 1005 pm_runtime_disable(dev); 1006 return ret; 1007 } 1008 1009 static int rcar_i2c_remove(struct platform_device *pdev) 1010 { 1011 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1012 struct device *dev = &pdev->dev; 1013 1014 i2c_del_adapter(&priv->adap); 1015 rcar_i2c_release_dma(priv); 1016 if (priv->flags & ID_P_PM_BLOCKED) 1017 pm_runtime_put(dev); 1018 pm_runtime_disable(dev); 1019 1020 return 0; 1021 } 1022 1023 static struct platform_driver rcar_i2c_driver = { 1024 .driver = { 1025 .name = "i2c-rcar", 1026 .of_match_table = rcar_i2c_dt_ids, 1027 }, 1028 .probe = rcar_i2c_probe, 1029 .remove = rcar_i2c_remove, 1030 }; 1031 1032 module_platform_driver(rcar_i2c_driver); 1033 1034 MODULE_LICENSE("GPL v2"); 1035 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1036 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1037