1 /* 2 * drivers/i2c/busses/i2c-rcar.c 3 * 4 * Copyright (C) 2012 Renesas Solutions Corp. 5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 8 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 9 * 10 * This file used out-of-tree driver i2c-rcar.c 11 * Copyright (C) 2011-2012 Renesas Electronics Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 */ 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/err.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/i2c.h> 33 #include <linux/i2c/i2c-rcar.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/of_device.h> 37 #include <linux/platform_device.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/slab.h> 40 #include <linux/spinlock.h> 41 42 /* register offsets */ 43 #define ICSCR 0x00 /* slave ctrl */ 44 #define ICMCR 0x04 /* master ctrl */ 45 #define ICSSR 0x08 /* slave status */ 46 #define ICMSR 0x0C /* master status */ 47 #define ICSIER 0x10 /* slave irq enable */ 48 #define ICMIER 0x14 /* master irq enable */ 49 #define ICCCR 0x18 /* clock dividers */ 50 #define ICSAR 0x1C /* slave address */ 51 #define ICMAR 0x20 /* master address */ 52 #define ICRXTX 0x24 /* data port */ 53 54 /* ICMCR */ 55 #define MDBS (1 << 7) /* non-fifo mode switch */ 56 #define FSCL (1 << 6) /* override SCL pin */ 57 #define FSDA (1 << 5) /* override SDA pin */ 58 #define OBPC (1 << 4) /* override pins */ 59 #define MIE (1 << 3) /* master if enable */ 60 #define TSBE (1 << 2) 61 #define FSB (1 << 1) /* force stop bit */ 62 #define ESG (1 << 0) /* en startbit gen */ 63 64 /* ICMSR */ 65 #define MNR (1 << 6) /* nack received */ 66 #define MAL (1 << 5) /* arbitration lost */ 67 #define MST (1 << 4) /* sent a stop */ 68 #define MDE (1 << 3) 69 #define MDT (1 << 2) 70 #define MDR (1 << 1) 71 #define MAT (1 << 0) /* slave addr xfer done */ 72 73 /* ICMIE */ 74 #define MNRE (1 << 6) /* nack irq en */ 75 #define MALE (1 << 5) /* arblos irq en */ 76 #define MSTE (1 << 4) /* stop irq en */ 77 #define MDEE (1 << 3) 78 #define MDTE (1 << 2) 79 #define MDRE (1 << 1) 80 #define MATE (1 << 0) /* address sent irq en */ 81 82 83 enum { 84 RCAR_BUS_PHASE_ADDR, 85 RCAR_BUS_PHASE_DATA, 86 RCAR_BUS_PHASE_STOP, 87 }; 88 89 enum { 90 RCAR_IRQ_CLOSE, 91 RCAR_IRQ_OPEN_FOR_SEND, 92 RCAR_IRQ_OPEN_FOR_RECV, 93 RCAR_IRQ_OPEN_FOR_STOP, 94 }; 95 96 /* 97 * flags 98 */ 99 #define ID_LAST_MSG (1 << 0) 100 #define ID_IOERROR (1 << 1) 101 #define ID_DONE (1 << 2) 102 #define ID_ARBLOST (1 << 3) 103 #define ID_NACK (1 << 4) 104 105 enum rcar_i2c_type { 106 I2C_RCAR_GEN1, 107 I2C_RCAR_GEN2, 108 }; 109 110 struct rcar_i2c_priv { 111 void __iomem *io; 112 struct i2c_adapter adap; 113 struct i2c_msg *msg; 114 115 spinlock_t lock; 116 wait_queue_head_t wait; 117 118 int pos; 119 int irq; 120 u32 icccr; 121 u32 flags; 122 enum rcar_i2c_type devtype; 123 }; 124 125 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 126 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 127 128 #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) 129 #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) 130 131 #define LOOP_TIMEOUT 1024 132 133 /* 134 * basic functions 135 */ 136 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 137 { 138 writel(val, priv->io + reg); 139 } 140 141 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 142 { 143 return readl(priv->io + reg); 144 } 145 146 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 147 { 148 /* 149 * reset slave mode. 150 * slave mode is not used on this driver 151 */ 152 rcar_i2c_write(priv, ICSIER, 0); 153 rcar_i2c_write(priv, ICSAR, 0); 154 rcar_i2c_write(priv, ICSCR, 0); 155 rcar_i2c_write(priv, ICSSR, 0); 156 157 /* reset master mode */ 158 rcar_i2c_write(priv, ICMIER, 0); 159 rcar_i2c_write(priv, ICMCR, 0); 160 rcar_i2c_write(priv, ICMSR, 0); 161 rcar_i2c_write(priv, ICMAR, 0); 162 } 163 164 static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open) 165 { 166 u32 val = MNRE | MALE | MSTE | MATE; /* default */ 167 168 switch (open) { 169 case RCAR_IRQ_OPEN_FOR_SEND: 170 val |= MDEE; /* default + send */ 171 break; 172 case RCAR_IRQ_OPEN_FOR_RECV: 173 val |= MDRE; /* default + read */ 174 break; 175 case RCAR_IRQ_OPEN_FOR_STOP: 176 val = MSTE; /* stop irq only */ 177 break; 178 case RCAR_IRQ_CLOSE: 179 default: 180 val = 0; /* all close */ 181 break; 182 } 183 rcar_i2c_write(priv, ICMIER, val); 184 } 185 186 static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv) 187 { 188 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv); 189 } 190 191 /* 192 * bus control functions 193 */ 194 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 195 { 196 int i; 197 198 for (i = 0; i < LOOP_TIMEOUT; i++) { 199 /* make sure that bus is not busy */ 200 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 201 return 0; 202 udelay(1); 203 } 204 205 return -EBUSY; 206 } 207 208 static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase) 209 { 210 switch (phase) { 211 case RCAR_BUS_PHASE_ADDR: 212 rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG); 213 break; 214 case RCAR_BUS_PHASE_DATA: 215 rcar_i2c_write(priv, ICMCR, MDBS | MIE); 216 break; 217 case RCAR_BUS_PHASE_STOP: 218 rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB); 219 break; 220 } 221 } 222 223 /* 224 * clock function 225 */ 226 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, 227 u32 bus_speed, 228 struct device *dev) 229 { 230 struct clk *clkp = clk_get(dev, NULL); 231 u32 scgd, cdf; 232 u32 round, ick; 233 u32 scl; 234 u32 cdf_width; 235 unsigned long rate; 236 237 if (IS_ERR(clkp)) { 238 dev_err(dev, "couldn't get clock\n"); 239 return PTR_ERR(clkp); 240 } 241 242 switch (priv->devtype) { 243 case I2C_RCAR_GEN1: 244 cdf_width = 2; 245 break; 246 case I2C_RCAR_GEN2: 247 cdf_width = 3; 248 break; 249 default: 250 dev_err(dev, "device type error\n"); 251 return -EIO; 252 } 253 254 /* 255 * calculate SCL clock 256 * see 257 * ICCCR 258 * 259 * ick = clkp / (1 + CDF) 260 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 261 * 262 * ick : I2C internal clock < 20 MHz 263 * ticf : I2C SCL falling time = 35 ns here 264 * tr : I2C SCL rising time = 200 ns here 265 * intd : LSI internal delay = 50 ns here 266 * clkp : peripheral_clk 267 * F[] : integer up-valuation 268 */ 269 rate = clk_get_rate(clkp); 270 cdf = rate / 20000000; 271 if (cdf >= 1 << cdf_width) { 272 dev_err(dev, "Input clock %lu too high\n", rate); 273 return -EIO; 274 } 275 ick = rate / (cdf + 1); 276 277 /* 278 * it is impossible to calculate large scale 279 * number on u32. separate it 280 * 281 * F[(ticf + tr + intd) * ick] 282 * = F[(35 + 200 + 50)ns * ick] 283 * = F[285 * ick / 1000000000] 284 * = F[(ick / 1000000) * 285 / 1000] 285 */ 286 round = (ick + 500000) / 1000000 * 285; 287 round = (round + 500) / 1000; 288 289 /* 290 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 291 * 292 * Calculation result (= SCL) should be less than 293 * bus_speed for hardware safety 294 * 295 * We could use something along the lines of 296 * div = ick / (bus_speed + 1) + 1; 297 * scgd = (div - 20 - round + 7) / 8; 298 * scl = ick / (20 + (scgd * 8) + round); 299 * (not fully verified) but that would get pretty involved 300 */ 301 for (scgd = 0; scgd < 0x40; scgd++) { 302 scl = ick / (20 + (scgd * 8) + round); 303 if (scl <= bus_speed) 304 goto scgd_find; 305 } 306 dev_err(dev, "it is impossible to calculate best SCL\n"); 307 return -EIO; 308 309 scgd_find: 310 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 311 scl, bus_speed, clk_get_rate(clkp), round, cdf, scgd); 312 313 /* 314 * keep icccr value 315 */ 316 priv->icccr = scgd << cdf_width | cdf; 317 318 return 0; 319 } 320 321 static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv) 322 { 323 rcar_i2c_write(priv, ICCCR, priv->icccr); 324 } 325 326 /* 327 * status functions 328 */ 329 static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv) 330 { 331 return rcar_i2c_read(priv, ICMSR); 332 } 333 334 #define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff) 335 static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit) 336 { 337 rcar_i2c_write(priv, ICMSR, ~bit); 338 } 339 340 /* 341 * recv/send functions 342 */ 343 static int rcar_i2c_recv(struct rcar_i2c_priv *priv) 344 { 345 rcar_i2c_set_addr(priv, 1); 346 rcar_i2c_status_clear(priv); 347 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); 348 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV); 349 350 return 0; 351 } 352 353 static int rcar_i2c_send(struct rcar_i2c_priv *priv) 354 { 355 int ret; 356 357 /* 358 * It should check bus status when send case 359 */ 360 ret = rcar_i2c_bus_barrier(priv); 361 if (ret < 0) 362 return ret; 363 364 rcar_i2c_set_addr(priv, 0); 365 rcar_i2c_status_clear(priv); 366 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); 367 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND); 368 369 return 0; 370 } 371 372 #define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE)) 373 #define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR)) 374 375 /* 376 * interrupt functions 377 */ 378 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 379 { 380 struct i2c_msg *msg = priv->msg; 381 382 /* 383 * FIXME 384 * sometimes, unknown interrupt happened. 385 * Do nothing 386 */ 387 if (!(msr & MDE)) 388 return 0; 389 390 /* 391 * If address transfer phase finished, 392 * goto data phase. 393 */ 394 if (msr & MAT) 395 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); 396 397 if (priv->pos < msg->len) { 398 /* 399 * Prepare next data to ICRXTX register. 400 * This data will go to _SHIFT_ register. 401 * 402 * * 403 * [ICRXTX] -> [SHIFT] -> [I2C bus] 404 */ 405 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 406 priv->pos++; 407 408 } else { 409 /* 410 * The last data was pushed to ICRXTX on _PREV_ empty irq. 411 * It is on _SHIFT_ register, and will sent to I2C bus. 412 * 413 * * 414 * [ICRXTX] -> [SHIFT] -> [I2C bus] 415 */ 416 417 if (priv->flags & ID_LAST_MSG) 418 /* 419 * If current msg is the _LAST_ msg, 420 * prepare stop condition here. 421 * ID_DONE will be set on STOP irq. 422 */ 423 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 424 else 425 /* 426 * If current msg is _NOT_ last msg, 427 * it doesn't call stop phase. 428 * thus, there is no STOP irq. 429 * return ID_DONE here. 430 */ 431 return ID_DONE; 432 } 433 434 rcar_i2c_send_restart(priv); 435 436 return 0; 437 } 438 439 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 440 { 441 struct i2c_msg *msg = priv->msg; 442 443 /* 444 * FIXME 445 * sometimes, unknown interrupt happened. 446 * Do nothing 447 */ 448 if (!(msr & MDR)) 449 return 0; 450 451 if (msr & MAT) { 452 /* 453 * Address transfer phase finished, 454 * but, there is no data at this point. 455 * Do nothing. 456 */ 457 } else if (priv->pos < msg->len) { 458 /* 459 * get received data 460 */ 461 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 462 priv->pos++; 463 } 464 465 /* 466 * If next received data is the _LAST_, 467 * go to STOP phase, 468 * otherwise, go to DATA phase. 469 */ 470 if (priv->pos + 1 >= msg->len) 471 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 472 else 473 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); 474 475 rcar_i2c_recv_restart(priv); 476 477 return 0; 478 } 479 480 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 481 { 482 struct rcar_i2c_priv *priv = ptr; 483 struct device *dev = rcar_i2c_priv_to_dev(priv); 484 u32 msr; 485 486 /*-------------- spin lock -----------------*/ 487 spin_lock(&priv->lock); 488 489 msr = rcar_i2c_status_get(priv); 490 491 /* 492 * Arbitration lost 493 */ 494 if (msr & MAL) { 495 /* 496 * CAUTION 497 * 498 * When arbitration lost, device become _slave_ mode. 499 */ 500 dev_dbg(dev, "Arbitration Lost\n"); 501 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); 502 goto out; 503 } 504 505 /* 506 * Stop 507 */ 508 if (msr & MST) { 509 dev_dbg(dev, "Stop\n"); 510 rcar_i2c_flags_set(priv, ID_DONE); 511 goto out; 512 } 513 514 /* 515 * Nack 516 */ 517 if (msr & MNR) { 518 dev_dbg(dev, "Nack\n"); 519 520 /* go to stop phase */ 521 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); 522 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP); 523 rcar_i2c_flags_set(priv, ID_NACK); 524 goto out; 525 } 526 527 /* 528 * recv/send 529 */ 530 if (rcar_i2c_is_recv(priv)) 531 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); 532 else 533 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); 534 535 out: 536 if (rcar_i2c_flags_has(priv, ID_DONE)) { 537 rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE); 538 rcar_i2c_status_clear(priv); 539 wake_up(&priv->wait); 540 } 541 542 spin_unlock(&priv->lock); 543 /*-------------- spin unlock -----------------*/ 544 545 return IRQ_HANDLED; 546 } 547 548 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 549 struct i2c_msg *msgs, 550 int num) 551 { 552 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 553 struct device *dev = rcar_i2c_priv_to_dev(priv); 554 unsigned long flags; 555 int i, ret, timeout; 556 557 pm_runtime_get_sync(dev); 558 559 /*-------------- spin lock -----------------*/ 560 spin_lock_irqsave(&priv->lock, flags); 561 562 rcar_i2c_init(priv); 563 rcar_i2c_clock_start(priv); 564 565 spin_unlock_irqrestore(&priv->lock, flags); 566 /*-------------- spin unlock -----------------*/ 567 568 ret = -EINVAL; 569 for (i = 0; i < num; i++) { 570 /*-------------- spin lock -----------------*/ 571 spin_lock_irqsave(&priv->lock, flags); 572 573 /* init each data */ 574 priv->msg = &msgs[i]; 575 priv->pos = 0; 576 priv->flags = 0; 577 if (priv->msg == &msgs[num - 1]) 578 rcar_i2c_flags_set(priv, ID_LAST_MSG); 579 580 /* start send/recv */ 581 if (rcar_i2c_is_recv(priv)) 582 ret = rcar_i2c_recv(priv); 583 else 584 ret = rcar_i2c_send(priv); 585 586 spin_unlock_irqrestore(&priv->lock, flags); 587 /*-------------- spin unlock -----------------*/ 588 589 if (ret < 0) 590 break; 591 592 /* 593 * wait result 594 */ 595 timeout = wait_event_timeout(priv->wait, 596 rcar_i2c_flags_has(priv, ID_DONE), 597 5 * HZ); 598 if (!timeout) { 599 ret = -ETIMEDOUT; 600 break; 601 } 602 603 /* 604 * error handling 605 */ 606 if (rcar_i2c_flags_has(priv, ID_NACK)) { 607 ret = -EREMOTEIO; 608 break; 609 } 610 611 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { 612 ret = -EAGAIN; 613 break; 614 } 615 616 if (rcar_i2c_flags_has(priv, ID_IOERROR)) { 617 ret = -EIO; 618 break; 619 } 620 621 ret = i + 1; /* The number of transfer */ 622 } 623 624 pm_runtime_put(dev); 625 626 if (ret < 0) 627 dev_err(dev, "error %d : %x\n", ret, priv->flags); 628 629 return ret; 630 } 631 632 static u32 rcar_i2c_func(struct i2c_adapter *adap) 633 { 634 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 635 } 636 637 static const struct i2c_algorithm rcar_i2c_algo = { 638 .master_xfer = rcar_i2c_master_xfer, 639 .functionality = rcar_i2c_func, 640 }; 641 642 static const struct of_device_id rcar_i2c_dt_ids[] = { 643 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, 644 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 645 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 646 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 647 {}, 648 }; 649 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 650 651 static int rcar_i2c_probe(struct platform_device *pdev) 652 { 653 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev); 654 struct rcar_i2c_priv *priv; 655 struct i2c_adapter *adap; 656 struct resource *res; 657 struct device *dev = &pdev->dev; 658 u32 bus_speed; 659 int ret; 660 661 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 662 if (!priv) { 663 dev_err(dev, "no mem for private data\n"); 664 return -ENOMEM; 665 } 666 667 bus_speed = 100000; /* default 100 kHz */ 668 ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed); 669 if (ret < 0 && pdata && pdata->bus_speed) 670 bus_speed = pdata->bus_speed; 671 672 if (pdev->dev.of_node) 673 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids, 674 dev)->data; 675 else 676 priv->devtype = platform_get_device_id(pdev)->driver_data; 677 678 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); 679 if (ret < 0) 680 return ret; 681 682 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 683 priv->io = devm_ioremap_resource(dev, res); 684 if (IS_ERR(priv->io)) 685 return PTR_ERR(priv->io); 686 687 priv->irq = platform_get_irq(pdev, 0); 688 init_waitqueue_head(&priv->wait); 689 spin_lock_init(&priv->lock); 690 691 adap = &priv->adap; 692 adap->nr = pdev->id; 693 adap->algo = &rcar_i2c_algo; 694 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 695 adap->retries = 3; 696 adap->dev.parent = dev; 697 adap->dev.of_node = dev->of_node; 698 i2c_set_adapdata(adap, priv); 699 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 700 701 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, 702 dev_name(dev), priv); 703 if (ret < 0) { 704 dev_err(dev, "cannot get irq %d\n", priv->irq); 705 return ret; 706 } 707 708 ret = i2c_add_numbered_adapter(adap); 709 if (ret < 0) { 710 dev_err(dev, "reg adap failed: %d\n", ret); 711 return ret; 712 } 713 714 pm_runtime_enable(dev); 715 platform_set_drvdata(pdev, priv); 716 717 dev_info(dev, "probed\n"); 718 719 return 0; 720 } 721 722 static int rcar_i2c_remove(struct platform_device *pdev) 723 { 724 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 725 struct device *dev = &pdev->dev; 726 727 i2c_del_adapter(&priv->adap); 728 pm_runtime_disable(dev); 729 730 return 0; 731 } 732 733 static struct platform_device_id rcar_i2c_id_table[] = { 734 { "i2c-rcar", I2C_RCAR_GEN1 }, 735 { "i2c-rcar_gen1", I2C_RCAR_GEN1 }, 736 { "i2c-rcar_gen2", I2C_RCAR_GEN2 }, 737 {}, 738 }; 739 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table); 740 741 static struct platform_driver rcar_i2c_driver = { 742 .driver = { 743 .name = "i2c-rcar", 744 .owner = THIS_MODULE, 745 .of_match_table = rcar_i2c_dt_ids, 746 }, 747 .probe = rcar_i2c_probe, 748 .remove = rcar_i2c_remove, 749 .id_table = rcar_i2c_id_table, 750 }; 751 752 module_platform_driver(rcar_i2c_driver); 753 754 MODULE_LICENSE("GPL"); 755 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 756 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 757