1 /* 2 * Driver for the Renesas R-Car I2C unit 3 * 4 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> 5 * Copyright (C) 2011-2015 Renesas Electronics Corporation 6 * 7 * Copyright (C) 2012-14 Renesas Solutions Corp. 8 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 9 * 10 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 11 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; version 2 of the License. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 #include <linux/clk.h> 23 #include <linux/delay.h> 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/err.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/i2c.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/of_device.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/slab.h> 36 37 /* register offsets */ 38 #define ICSCR 0x00 /* slave ctrl */ 39 #define ICMCR 0x04 /* master ctrl */ 40 #define ICSSR 0x08 /* slave status */ 41 #define ICMSR 0x0C /* master status */ 42 #define ICSIER 0x10 /* slave irq enable */ 43 #define ICMIER 0x14 /* master irq enable */ 44 #define ICCCR 0x18 /* clock dividers */ 45 #define ICSAR 0x1C /* slave address */ 46 #define ICMAR 0x20 /* master address */ 47 #define ICRXTX 0x24 /* data port */ 48 #define ICDMAER 0x3c /* DMA enable */ 49 #define ICFBSCR 0x38 /* first bit setup cycle */ 50 51 /* ICSCR */ 52 #define SDBS (1 << 3) /* slave data buffer select */ 53 #define SIE (1 << 2) /* slave interface enable */ 54 #define GCAE (1 << 1) /* general call address enable */ 55 #define FNA (1 << 0) /* forced non acknowledgment */ 56 57 /* ICMCR */ 58 #define MDBS (1 << 7) /* non-fifo mode switch */ 59 #define FSCL (1 << 6) /* override SCL pin */ 60 #define FSDA (1 << 5) /* override SDA pin */ 61 #define OBPC (1 << 4) /* override pins */ 62 #define MIE (1 << 3) /* master if enable */ 63 #define TSBE (1 << 2) 64 #define FSB (1 << 1) /* force stop bit */ 65 #define ESG (1 << 0) /* enable start bit gen */ 66 67 /* ICSSR (also for ICSIER) */ 68 #define GCAR (1 << 6) /* general call received */ 69 #define STM (1 << 5) /* slave transmit mode */ 70 #define SSR (1 << 4) /* stop received */ 71 #define SDE (1 << 3) /* slave data empty */ 72 #define SDT (1 << 2) /* slave data transmitted */ 73 #define SDR (1 << 1) /* slave data received */ 74 #define SAR (1 << 0) /* slave addr received */ 75 76 /* ICMSR (also for ICMIE) */ 77 #define MNR (1 << 6) /* nack received */ 78 #define MAL (1 << 5) /* arbitration lost */ 79 #define MST (1 << 4) /* sent a stop */ 80 #define MDE (1 << 3) 81 #define MDT (1 << 2) 82 #define MDR (1 << 1) 83 #define MAT (1 << 0) /* slave addr xfer done */ 84 85 /* ICDMAER */ 86 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 87 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 88 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 89 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 90 91 /* ICFBSCR */ 92 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */ 93 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 94 95 96 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 97 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 98 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) 99 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 100 101 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 102 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 103 #define RCAR_IRQ_STOP (MST) 104 105 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF) 106 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF) 107 108 #define ID_LAST_MSG (1 << 0) 109 #define ID_FIRST_MSG (1 << 1) 110 #define ID_DONE (1 << 2) 111 #define ID_ARBLOST (1 << 3) 112 #define ID_NACK (1 << 4) 113 /* persistent flags */ 114 #define ID_P_PM_BLOCKED (1 << 31) 115 #define ID_P_MASK ID_P_PM_BLOCKED 116 117 enum rcar_i2c_type { 118 I2C_RCAR_GEN1, 119 I2C_RCAR_GEN2, 120 I2C_RCAR_GEN3, 121 }; 122 123 struct rcar_i2c_priv { 124 void __iomem *io; 125 struct i2c_adapter adap; 126 struct i2c_msg *msg; 127 int msgs_left; 128 struct clk *clk; 129 130 wait_queue_head_t wait; 131 132 int pos; 133 u32 icccr; 134 u32 flags; 135 u8 recovery_icmcr; /* protected by adapter lock */ 136 enum rcar_i2c_type devtype; 137 struct i2c_client *slave; 138 139 struct resource *res; 140 struct dma_chan *dma_tx; 141 struct dma_chan *dma_rx; 142 struct scatterlist sg; 143 enum dma_data_direction dma_direction; 144 }; 145 146 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 147 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 148 149 #define LOOP_TIMEOUT 1024 150 151 152 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 153 { 154 writel(val, priv->io + reg); 155 } 156 157 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 158 { 159 return readl(priv->io + reg); 160 } 161 162 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 163 { 164 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 165 166 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 167 168 }; 169 170 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 171 { 172 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 173 174 if (val) 175 priv->recovery_icmcr |= FSCL; 176 else 177 priv->recovery_icmcr &= ~FSCL; 178 179 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 180 }; 181 182 /* No get_sda, because the HW only reports its bus free logic, not SDA itself */ 183 184 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 185 { 186 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 187 188 if (val) 189 priv->recovery_icmcr |= FSDA; 190 else 191 priv->recovery_icmcr &= ~FSDA; 192 193 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 194 }; 195 196 static struct i2c_bus_recovery_info rcar_i2c_bri = { 197 .get_scl = rcar_i2c_get_scl, 198 .set_scl = rcar_i2c_set_scl, 199 .set_sda = rcar_i2c_set_sda, 200 .recover_bus = i2c_generic_scl_recovery, 201 }; 202 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 203 { 204 /* reset master mode */ 205 rcar_i2c_write(priv, ICMIER, 0); 206 rcar_i2c_write(priv, ICMCR, MDBS); 207 rcar_i2c_write(priv, ICMSR, 0); 208 /* start clock */ 209 rcar_i2c_write(priv, ICCCR, priv->icccr); 210 } 211 212 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 213 { 214 int i, ret; 215 216 for (i = 0; i < LOOP_TIMEOUT; i++) { 217 /* make sure that bus is not busy */ 218 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 219 return 0; 220 udelay(1); 221 } 222 223 /* Waiting did not help, try to recover */ 224 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 225 ret = i2c_recover_bus(&priv->adap); 226 227 /* No failure when recovering, so check bus busy bit again */ 228 if (ret == 0) 229 ret = (rcar_i2c_read(priv, ICMCR) & FSDA) ? -EBUSY : 0; 230 231 return ret; 232 } 233 234 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) 235 { 236 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 237 unsigned long rate; 238 struct device *dev = rcar_i2c_priv_to_dev(priv); 239 240 /* Fall back to previously used values if not supplied */ 241 t->bus_freq_hz = t->bus_freq_hz ?: 100000; 242 t->scl_fall_ns = t->scl_fall_ns ?: 35; 243 t->scl_rise_ns = t->scl_rise_ns ?: 200; 244 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; 245 246 switch (priv->devtype) { 247 case I2C_RCAR_GEN1: 248 cdf_width = 2; 249 break; 250 case I2C_RCAR_GEN2: 251 case I2C_RCAR_GEN3: 252 cdf_width = 3; 253 break; 254 default: 255 dev_err(dev, "device type error\n"); 256 return -EIO; 257 } 258 259 /* 260 * calculate SCL clock 261 * see 262 * ICCCR 263 * 264 * ick = clkp / (1 + CDF) 265 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 266 * 267 * ick : I2C internal clock < 20 MHz 268 * ticf : I2C SCL falling time 269 * tr : I2C SCL rising time 270 * intd : LSI internal delay 271 * clkp : peripheral_clk 272 * F[] : integer up-valuation 273 */ 274 rate = clk_get_rate(priv->clk); 275 cdf = rate / 20000000; 276 if (cdf >= 1U << cdf_width) { 277 dev_err(dev, "Input clock %lu too high\n", rate); 278 return -EIO; 279 } 280 ick = rate / (cdf + 1); 281 282 /* 283 * it is impossible to calculate large scale 284 * number on u32. separate it 285 * 286 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 287 * = F[sum * ick / 1000000000] 288 * = F[(ick / 1000000) * sum / 1000] 289 */ 290 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; 291 round = (ick + 500000) / 1000000 * sum; 292 round = (round + 500) / 1000; 293 294 /* 295 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 296 * 297 * Calculation result (= SCL) should be less than 298 * bus_speed for hardware safety 299 * 300 * We could use something along the lines of 301 * div = ick / (bus_speed + 1) + 1; 302 * scgd = (div - 20 - round + 7) / 8; 303 * scl = ick / (20 + (scgd * 8) + round); 304 * (not fully verified) but that would get pretty involved 305 */ 306 for (scgd = 0; scgd < 0x40; scgd++) { 307 scl = ick / (20 + (scgd * 8) + round); 308 if (scl <= t->bus_freq_hz) 309 goto scgd_find; 310 } 311 dev_err(dev, "it is impossible to calculate best SCL\n"); 312 return -EIO; 313 314 scgd_find: 315 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 316 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); 317 318 /* keep icccr value */ 319 priv->icccr = scgd << cdf_width | cdf; 320 321 return 0; 322 } 323 324 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 325 { 326 int read = !!rcar_i2c_is_recv(priv); 327 328 priv->pos = 0; 329 if (priv->msgs_left == 1) 330 priv->flags |= ID_LAST_MSG; 331 332 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); 333 /* 334 * We don't have a test case but the HW engineers say that the write order 335 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 336 * it didn't cause a drawback for me, let's rather be safe than sorry. 337 */ 338 if (priv->flags & ID_FIRST_MSG) { 339 rcar_i2c_write(priv, ICMSR, 0); 340 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 341 } else { 342 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 343 rcar_i2c_write(priv, ICMSR, 0); 344 } 345 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 346 } 347 348 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 349 { 350 priv->msg++; 351 priv->msgs_left--; 352 priv->flags &= ID_P_MASK; 353 rcar_i2c_prepare_msg(priv); 354 } 355 356 /* 357 * interrupt functions 358 */ 359 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 360 { 361 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 362 ? priv->dma_rx : priv->dma_tx; 363 364 /* Disable DMA Master Received/Transmitted */ 365 rcar_i2c_write(priv, ICDMAER, 0); 366 367 /* Reset default delay */ 368 rcar_i2c_write(priv, ICFBSCR, TCYC06); 369 370 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 371 sg_dma_len(&priv->sg), priv->dma_direction); 372 373 priv->dma_direction = DMA_NONE; 374 } 375 376 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 377 { 378 if (priv->dma_direction == DMA_NONE) 379 return; 380 else if (priv->dma_direction == DMA_FROM_DEVICE) 381 dmaengine_terminate_all(priv->dma_rx); 382 else if (priv->dma_direction == DMA_TO_DEVICE) 383 dmaengine_terminate_all(priv->dma_tx); 384 385 rcar_i2c_dma_unmap(priv); 386 } 387 388 static void rcar_i2c_dma_callback(void *data) 389 { 390 struct rcar_i2c_priv *priv = data; 391 392 priv->pos += sg_dma_len(&priv->sg); 393 394 rcar_i2c_dma_unmap(priv); 395 } 396 397 static void rcar_i2c_dma(struct rcar_i2c_priv *priv) 398 { 399 struct device *dev = rcar_i2c_priv_to_dev(priv); 400 struct i2c_msg *msg = priv->msg; 401 bool read = msg->flags & I2C_M_RD; 402 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 403 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 404 struct dma_async_tx_descriptor *txdesc; 405 dma_addr_t dma_addr; 406 dma_cookie_t cookie; 407 unsigned char *buf; 408 int len; 409 410 /* Do not use DMA if it's not available or for messages < 8 bytes */ 411 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE)) 412 return; 413 414 if (read) { 415 /* 416 * The last two bytes needs to be fetched using PIO in 417 * order for the STOP phase to work. 418 */ 419 buf = priv->msg->buf; 420 len = priv->msg->len - 2; 421 } else { 422 /* 423 * First byte in message was sent using PIO. 424 */ 425 buf = priv->msg->buf + 1; 426 len = priv->msg->len - 1; 427 } 428 429 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 430 if (dma_mapping_error(chan->device->dev, dma_addr)) { 431 dev_dbg(dev, "dma map failed, using PIO\n"); 432 return; 433 } 434 435 sg_dma_len(&priv->sg) = len; 436 sg_dma_address(&priv->sg) = dma_addr; 437 438 priv->dma_direction = dir; 439 440 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 441 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 442 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 443 if (!txdesc) { 444 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 445 rcar_i2c_cleanup_dma(priv); 446 return; 447 } 448 449 txdesc->callback = rcar_i2c_dma_callback; 450 txdesc->callback_param = priv; 451 452 cookie = dmaengine_submit(txdesc); 453 if (dma_submit_error(cookie)) { 454 dev_dbg(dev, "submitting dma failed, using PIO\n"); 455 rcar_i2c_cleanup_dma(priv); 456 return; 457 } 458 459 /* Set delay for DMA operations */ 460 rcar_i2c_write(priv, ICFBSCR, TCYC17); 461 462 /* Enable DMA Master Received/Transmitted */ 463 if (read) 464 rcar_i2c_write(priv, ICDMAER, RMDMAE); 465 else 466 rcar_i2c_write(priv, ICDMAER, TMDMAE); 467 468 dma_async_issue_pending(chan); 469 } 470 471 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 472 { 473 struct i2c_msg *msg = priv->msg; 474 475 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 476 if (!(msr & MDE)) 477 return; 478 479 if (priv->pos < msg->len) { 480 /* 481 * Prepare next data to ICRXTX register. 482 * This data will go to _SHIFT_ register. 483 * 484 * * 485 * [ICRXTX] -> [SHIFT] -> [I2C bus] 486 */ 487 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 488 priv->pos++; 489 490 /* 491 * Try to use DMA to transmit the rest of the data if 492 * address transfer phase just finished. 493 */ 494 if (msr & MAT) 495 rcar_i2c_dma(priv); 496 } else { 497 /* 498 * The last data was pushed to ICRXTX on _PREV_ empty irq. 499 * It is on _SHIFT_ register, and will sent to I2C bus. 500 * 501 * * 502 * [ICRXTX] -> [SHIFT] -> [I2C bus] 503 */ 504 505 if (priv->flags & ID_LAST_MSG) { 506 /* 507 * If current msg is the _LAST_ msg, 508 * prepare stop condition here. 509 * ID_DONE will be set on STOP irq. 510 */ 511 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 512 } else { 513 rcar_i2c_next_msg(priv); 514 return; 515 } 516 } 517 518 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 519 } 520 521 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 522 { 523 struct i2c_msg *msg = priv->msg; 524 525 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 526 if (!(msr & MDR)) 527 return; 528 529 if (msr & MAT) { 530 /* 531 * Address transfer phase finished, but no data at this point. 532 * Try to use DMA to receive data. 533 */ 534 rcar_i2c_dma(priv); 535 } else if (priv->pos < msg->len) { 536 /* get received data */ 537 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 538 priv->pos++; 539 } 540 541 /* 542 * If next received data is the _LAST_, go to STOP phase. Might be 543 * overwritten by REP START when setting up a new msg. Not elegant 544 * but the only stable sequence for REP START I have found so far. 545 */ 546 if (priv->pos + 1 >= msg->len) 547 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 548 549 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 550 rcar_i2c_next_msg(priv); 551 else 552 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 553 } 554 555 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 556 { 557 u32 ssr_raw, ssr_filtered; 558 u8 value; 559 560 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 561 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 562 563 if (!ssr_filtered) 564 return false; 565 566 /* address detected */ 567 if (ssr_filtered & SAR) { 568 /* read or write request */ 569 if (ssr_raw & STM) { 570 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 571 rcar_i2c_write(priv, ICRXTX, value); 572 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 573 } else { 574 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 575 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 576 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 577 } 578 579 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); 580 } 581 582 /* master sent stop */ 583 if (ssr_filtered & SSR) { 584 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 585 rcar_i2c_write(priv, ICSIER, SAR | SSR); 586 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 587 } 588 589 /* master wants to write to us */ 590 if (ssr_filtered & SDR) { 591 int ret; 592 593 value = rcar_i2c_read(priv, ICRXTX); 594 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 595 /* Send NACK in case of error */ 596 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 597 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 598 } 599 600 /* master wants to read from us */ 601 if (ssr_filtered & SDE) { 602 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 603 rcar_i2c_write(priv, ICRXTX, value); 604 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 605 } 606 607 return true; 608 } 609 610 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 611 { 612 struct rcar_i2c_priv *priv = ptr; 613 u32 msr, val; 614 615 /* Clear START or STOP as soon as we can */ 616 val = rcar_i2c_read(priv, ICMCR); 617 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); 618 619 msr = rcar_i2c_read(priv, ICMSR); 620 621 /* Only handle interrupts that are currently enabled */ 622 msr &= rcar_i2c_read(priv, ICMIER); 623 if (!msr) { 624 if (rcar_i2c_slave_irq(priv)) 625 return IRQ_HANDLED; 626 627 return IRQ_NONE; 628 } 629 630 /* Arbitration lost */ 631 if (msr & MAL) { 632 priv->flags |= ID_DONE | ID_ARBLOST; 633 goto out; 634 } 635 636 /* Nack */ 637 if (msr & MNR) { 638 /* HW automatically sends STOP after received NACK */ 639 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 640 priv->flags |= ID_NACK; 641 goto out; 642 } 643 644 /* Stop */ 645 if (msr & MST) { 646 priv->msgs_left--; /* The last message also made it */ 647 priv->flags |= ID_DONE; 648 goto out; 649 } 650 651 if (rcar_i2c_is_recv(priv)) 652 rcar_i2c_irq_recv(priv, msr); 653 else 654 rcar_i2c_irq_send(priv, msr); 655 656 out: 657 if (priv->flags & ID_DONE) { 658 rcar_i2c_write(priv, ICMIER, 0); 659 rcar_i2c_write(priv, ICMSR, 0); 660 wake_up(&priv->wait); 661 } 662 663 return IRQ_HANDLED; 664 } 665 666 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 667 enum dma_transfer_direction dir, 668 dma_addr_t port_addr) 669 { 670 struct dma_chan *chan; 671 struct dma_slave_config cfg; 672 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 673 int ret; 674 675 chan = dma_request_chan(dev, chan_name); 676 if (IS_ERR(chan)) { 677 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 678 chan_name, PTR_ERR(chan)); 679 return chan; 680 } 681 682 memset(&cfg, 0, sizeof(cfg)); 683 cfg.direction = dir; 684 if (dir == DMA_MEM_TO_DEV) { 685 cfg.dst_addr = port_addr; 686 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 687 } else { 688 cfg.src_addr = port_addr; 689 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 690 } 691 692 ret = dmaengine_slave_config(chan, &cfg); 693 if (ret) { 694 dev_dbg(dev, "slave_config failed for %s (%d)\n", 695 chan_name, ret); 696 dma_release_channel(chan); 697 return ERR_PTR(ret); 698 } 699 700 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 701 return chan; 702 } 703 704 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 705 struct i2c_msg *msg) 706 { 707 struct device *dev = rcar_i2c_priv_to_dev(priv); 708 bool read; 709 struct dma_chan *chan; 710 enum dma_transfer_direction dir; 711 712 read = msg->flags & I2C_M_RD; 713 714 chan = read ? priv->dma_rx : priv->dma_tx; 715 if (PTR_ERR(chan) != -EPROBE_DEFER) 716 return; 717 718 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 719 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 720 721 if (read) 722 priv->dma_rx = chan; 723 else 724 priv->dma_tx = chan; 725 } 726 727 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 728 { 729 if (!IS_ERR(priv->dma_tx)) { 730 dma_release_channel(priv->dma_tx); 731 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 732 } 733 734 if (!IS_ERR(priv->dma_rx)) { 735 dma_release_channel(priv->dma_rx); 736 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 737 } 738 } 739 740 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 741 struct i2c_msg *msgs, 742 int num) 743 { 744 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 745 struct device *dev = rcar_i2c_priv_to_dev(priv); 746 int i, ret; 747 long time_left; 748 749 pm_runtime_get_sync(dev); 750 751 rcar_i2c_init(priv); 752 753 ret = rcar_i2c_bus_barrier(priv); 754 if (ret < 0) 755 goto out; 756 757 for (i = 0; i < num; i++) { 758 /* This HW can't send STOP after address phase */ 759 if (msgs[i].len == 0) { 760 ret = -EOPNOTSUPP; 761 goto out; 762 } 763 rcar_i2c_request_dma(priv, msgs + i); 764 } 765 766 /* init first message */ 767 priv->msg = msgs; 768 priv->msgs_left = num; 769 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 770 rcar_i2c_prepare_msg(priv); 771 772 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 773 num * adap->timeout); 774 if (!time_left) { 775 rcar_i2c_cleanup_dma(priv); 776 rcar_i2c_init(priv); 777 ret = -ETIMEDOUT; 778 } else if (priv->flags & ID_NACK) { 779 ret = -ENXIO; 780 } else if (priv->flags & ID_ARBLOST) { 781 ret = -EAGAIN; 782 } else { 783 ret = num - priv->msgs_left; /* The number of transfer */ 784 } 785 out: 786 pm_runtime_put(dev); 787 788 if (ret < 0 && ret != -ENXIO) 789 dev_err(dev, "error %d : %x\n", ret, priv->flags); 790 791 return ret; 792 } 793 794 static int rcar_reg_slave(struct i2c_client *slave) 795 { 796 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 797 798 if (priv->slave) 799 return -EBUSY; 800 801 if (slave->flags & I2C_CLIENT_TEN) 802 return -EAFNOSUPPORT; 803 804 /* Keep device active for slave address detection logic */ 805 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 806 807 priv->slave = slave; 808 rcar_i2c_write(priv, ICSAR, slave->addr); 809 rcar_i2c_write(priv, ICSSR, 0); 810 rcar_i2c_write(priv, ICSIER, SAR | SSR); 811 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 812 813 return 0; 814 } 815 816 static int rcar_unreg_slave(struct i2c_client *slave) 817 { 818 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 819 820 WARN_ON(!priv->slave); 821 822 rcar_i2c_write(priv, ICSIER, 0); 823 rcar_i2c_write(priv, ICSCR, 0); 824 825 priv->slave = NULL; 826 827 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 828 829 return 0; 830 } 831 832 static u32 rcar_i2c_func(struct i2c_adapter *adap) 833 { 834 /* 835 * This HW can't do: 836 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 837 * I2C_M_NOSTART (automatically sends address after START) 838 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 839 */ 840 return I2C_FUNC_I2C | I2C_FUNC_SLAVE | 841 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 842 } 843 844 static const struct i2c_algorithm rcar_i2c_algo = { 845 .master_xfer = rcar_i2c_master_xfer, 846 .functionality = rcar_i2c_func, 847 .reg_slave = rcar_reg_slave, 848 .unreg_slave = rcar_unreg_slave, 849 }; 850 851 static const struct of_device_id rcar_i2c_dt_ids[] = { 852 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 853 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 854 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 855 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 856 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 857 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 858 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 859 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 860 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 861 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 862 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 863 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 864 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 865 {}, 866 }; 867 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 868 869 static int rcar_i2c_probe(struct platform_device *pdev) 870 { 871 struct rcar_i2c_priv *priv; 872 struct i2c_adapter *adap; 873 struct device *dev = &pdev->dev; 874 struct i2c_timings i2c_t; 875 int irq, ret; 876 877 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 878 if (!priv) 879 return -ENOMEM; 880 881 priv->clk = devm_clk_get(dev, NULL); 882 if (IS_ERR(priv->clk)) { 883 dev_err(dev, "cannot get clock\n"); 884 return PTR_ERR(priv->clk); 885 } 886 887 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 888 889 priv->io = devm_ioremap_resource(dev, priv->res); 890 if (IS_ERR(priv->io)) 891 return PTR_ERR(priv->io); 892 893 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 894 init_waitqueue_head(&priv->wait); 895 896 adap = &priv->adap; 897 adap->nr = pdev->id; 898 adap->algo = &rcar_i2c_algo; 899 adap->class = I2C_CLASS_DEPRECATED; 900 adap->retries = 3; 901 adap->dev.parent = dev; 902 adap->dev.of_node = dev->of_node; 903 adap->bus_recovery_info = &rcar_i2c_bri; 904 i2c_set_adapdata(adap, priv); 905 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 906 907 i2c_parse_fw_timings(dev, &i2c_t, false); 908 909 /* Init DMA */ 910 sg_init_table(&priv->sg, 1); 911 priv->dma_direction = DMA_NONE; 912 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 913 914 /* Activate device for clock calculation */ 915 pm_runtime_enable(dev); 916 pm_runtime_get_sync(dev); 917 ret = rcar_i2c_clock_calculate(priv, &i2c_t); 918 if (ret < 0) 919 goto out_pm_put; 920 921 /* Stay always active when multi-master to keep arbitration working */ 922 if (of_property_read_bool(dev->of_node, "multi-master")) 923 priv->flags |= ID_P_PM_BLOCKED; 924 else 925 pm_runtime_put(dev); 926 927 928 irq = platform_get_irq(pdev, 0); 929 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); 930 if (ret < 0) { 931 dev_err(dev, "cannot get irq %d\n", irq); 932 goto out_pm_disable; 933 } 934 935 platform_set_drvdata(pdev, priv); 936 937 ret = i2c_add_numbered_adapter(adap); 938 if (ret < 0) 939 goto out_pm_disable; 940 941 dev_info(dev, "probed\n"); 942 943 return 0; 944 945 out_pm_put: 946 pm_runtime_put(dev); 947 out_pm_disable: 948 pm_runtime_disable(dev); 949 return ret; 950 } 951 952 static int rcar_i2c_remove(struct platform_device *pdev) 953 { 954 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 955 struct device *dev = &pdev->dev; 956 957 i2c_del_adapter(&priv->adap); 958 rcar_i2c_release_dma(priv); 959 if (priv->flags & ID_P_PM_BLOCKED) 960 pm_runtime_put(dev); 961 pm_runtime_disable(dev); 962 963 return 0; 964 } 965 966 static struct platform_driver rcar_i2c_driver = { 967 .driver = { 968 .name = "i2c-rcar", 969 .of_match_table = rcar_i2c_dt_ids, 970 }, 971 .probe = rcar_i2c_probe, 972 .remove = rcar_i2c_remove, 973 }; 974 975 module_platform_driver(rcar_i2c_driver); 976 977 MODULE_LICENSE("GPL v2"); 978 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 979 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 980