1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 45 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 46 47 /* ICSCR */ 48 #define SDBS BIT(3) /* slave data buffer select */ 49 #define SIE BIT(2) /* slave interface enable */ 50 #define GCAE BIT(1) /* general call address enable */ 51 #define FNA BIT(0) /* forced non acknowledgment */ 52 53 /* ICMCR */ 54 #define MDBS BIT(7) /* non-fifo mode switch */ 55 #define FSCL BIT(6) /* override SCL pin */ 56 #define FSDA BIT(5) /* override SDA pin */ 57 #define OBPC BIT(4) /* override pins */ 58 #define MIE BIT(3) /* master if enable */ 59 #define TSBE BIT(2) 60 #define FSB BIT(1) /* force stop bit */ 61 #define ESG BIT(0) /* enable start bit gen */ 62 63 /* ICSSR (also for ICSIER) */ 64 #define GCAR BIT(6) /* general call received */ 65 #define STM BIT(5) /* slave transmit mode */ 66 #define SSR BIT(4) /* stop received */ 67 #define SDE BIT(3) /* slave data empty */ 68 #define SDT BIT(2) /* slave data transmitted */ 69 #define SDR BIT(1) /* slave data received */ 70 #define SAR BIT(0) /* slave addr received */ 71 72 /* ICMSR (also for ICMIE) */ 73 #define MNR BIT(6) /* nack received */ 74 #define MAL BIT(5) /* arbitration lost */ 75 #define MST BIT(4) /* sent a stop */ 76 #define MDE BIT(3) 77 #define MDT BIT(2) 78 #define MDR BIT(1) 79 #define MAT BIT(0) /* slave addr xfer done */ 80 81 /* ICDMAER */ 82 #define RSDMAE BIT(3) /* DMA Slave Received Enable */ 83 #define TSDMAE BIT(2) /* DMA Slave Transmitted Enable */ 84 #define RMDMAE BIT(1) /* DMA Master Received Enable */ 85 #define TMDMAE BIT(0) /* DMA Master Transmitted Enable */ 86 87 /* ICFBSCR */ 88 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 89 90 #define RCAR_MIN_DMA_LEN 8 91 92 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 93 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 94 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 95 96 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 97 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 98 #define RCAR_IRQ_STOP (MST) 99 100 #define ID_LAST_MSG BIT(0) 101 #define ID_REP_AFTER_RD BIT(1) 102 #define ID_DONE BIT(2) 103 #define ID_ARBLOST BIT(3) 104 #define ID_NACK BIT(4) 105 #define ID_EPROTO BIT(5) 106 /* persistent flags */ 107 #define ID_P_NOT_ATOMIC BIT(28) 108 #define ID_P_HOST_NOTIFY BIT(29) 109 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 110 #define ID_P_PM_BLOCKED BIT(31) 111 #define ID_P_MASK GENMASK(31, 28) 112 113 enum rcar_i2c_type { 114 I2C_RCAR_GEN1, 115 I2C_RCAR_GEN2, 116 I2C_RCAR_GEN3, 117 I2C_RCAR_GEN4, 118 }; 119 120 struct rcar_i2c_priv { 121 u32 flags; 122 void __iomem *io; 123 struct i2c_adapter adap; 124 struct i2c_msg *msg; 125 int msgs_left; 126 struct clk *clk; 127 128 wait_queue_head_t wait; 129 130 int pos; 131 u32 icccr; 132 u8 recovery_icmcr; /* protected by adapter lock */ 133 enum rcar_i2c_type devtype; 134 struct i2c_client *slave; 135 136 struct resource *res; 137 struct dma_chan *dma_tx; 138 struct dma_chan *dma_rx; 139 struct scatterlist sg; 140 enum dma_data_direction dma_direction; 141 142 struct reset_control *rstc; 143 int irq; 144 145 struct i2c_client *host_notify_client; 146 }; 147 148 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 149 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 150 151 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 152 { 153 writel(val, priv->io + reg); 154 } 155 156 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 157 { 158 return readl(priv->io + reg); 159 } 160 161 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val) 162 { 163 writel(~val & 0x7f, priv->io + ICMSR); 164 } 165 166 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 167 { 168 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 169 170 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 171 172 }; 173 174 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 175 { 176 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 177 178 if (val) 179 priv->recovery_icmcr |= FSCL; 180 else 181 priv->recovery_icmcr &= ~FSCL; 182 183 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 184 }; 185 186 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 187 { 188 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 189 190 if (val) 191 priv->recovery_icmcr |= FSDA; 192 else 193 priv->recovery_icmcr &= ~FSDA; 194 195 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 196 }; 197 198 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 199 { 200 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 201 202 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 203 204 }; 205 206 static struct i2c_bus_recovery_info rcar_i2c_bri = { 207 .get_scl = rcar_i2c_get_scl, 208 .set_scl = rcar_i2c_set_scl, 209 .set_sda = rcar_i2c_set_sda, 210 .get_bus_free = rcar_i2c_get_bus_free, 211 .recover_bus = i2c_generic_scl_recovery, 212 }; 213 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 214 { 215 /* reset master mode */ 216 rcar_i2c_write(priv, ICMIER, 0); 217 rcar_i2c_write(priv, ICMCR, MDBS); 218 rcar_i2c_write(priv, ICMSR, 0); 219 /* start clock */ 220 rcar_i2c_write(priv, ICCCR, priv->icccr); 221 222 if (priv->devtype == I2C_RCAR_GEN3) 223 rcar_i2c_write(priv, ICFBSCR, TCYC17); 224 225 } 226 227 static void rcar_i2c_reset_slave(struct rcar_i2c_priv *priv) 228 { 229 rcar_i2c_write(priv, ICSIER, 0); 230 rcar_i2c_write(priv, ICSSR, 0); 231 rcar_i2c_write(priv, ICSCR, SDBS); 232 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 233 } 234 235 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 236 { 237 int ret; 238 u32 val; 239 240 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 241 priv->adap.timeout); 242 if (ret) { 243 /* Waiting did not help, try to recover */ 244 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 245 ret = i2c_recover_bus(&priv->adap); 246 } 247 248 return ret; 249 } 250 251 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 252 { 253 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 254 unsigned long rate; 255 struct device *dev = rcar_i2c_priv_to_dev(priv); 256 struct i2c_timings t = { 257 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 258 .scl_fall_ns = 35, 259 .scl_rise_ns = 200, 260 .scl_int_delay_ns = 50, 261 }; 262 263 /* Fall back to previously used values if not supplied */ 264 i2c_parse_fw_timings(dev, &t, false); 265 266 switch (priv->devtype) { 267 case I2C_RCAR_GEN1: 268 cdf_width = 2; 269 break; 270 case I2C_RCAR_GEN2: 271 case I2C_RCAR_GEN3: 272 cdf_width = 3; 273 break; 274 default: 275 dev_err(dev, "device type error\n"); 276 return -EIO; 277 } 278 279 /* 280 * calculate SCL clock 281 * see 282 * ICCCR 283 * 284 * ick = clkp / (1 + CDF) 285 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 286 * 287 * ick : I2C internal clock < 20 MHz 288 * ticf : I2C SCL falling time 289 * tr : I2C SCL rising time 290 * intd : LSI internal delay 291 * clkp : peripheral_clk 292 * F[] : integer up-valuation 293 */ 294 rate = clk_get_rate(priv->clk); 295 cdf = rate / 20000000; 296 if (cdf >= 1U << cdf_width) { 297 dev_err(dev, "Input clock %lu too high\n", rate); 298 return -EIO; 299 } 300 ick = rate / (cdf + 1); 301 302 /* 303 * it is impossible to calculate large scale 304 * number on u32. separate it 305 * 306 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 307 * = F[sum * ick / 1000000000] 308 * = F[(ick / 1000000) * sum / 1000] 309 */ 310 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 311 round = (ick + 500000) / 1000000 * sum; 312 round = (round + 500) / 1000; 313 314 /* 315 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 316 * 317 * Calculation result (= SCL) should be less than 318 * bus_speed for hardware safety 319 * 320 * We could use something along the lines of 321 * div = ick / (bus_speed + 1) + 1; 322 * scgd = (div - 20 - round + 7) / 8; 323 * scl = ick / (20 + (scgd * 8) + round); 324 * (not fully verified) but that would get pretty involved 325 */ 326 for (scgd = 0; scgd < 0x40; scgd++) { 327 scl = ick / (20 + (scgd * 8) + round); 328 if (scl <= t.bus_freq_hz) 329 goto scgd_find; 330 } 331 dev_err(dev, "it is impossible to calculate best SCL\n"); 332 return -EIO; 333 334 scgd_find: 335 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 336 scl, t.bus_freq_hz, rate, round, cdf, scgd); 337 338 /* keep icccr value */ 339 priv->icccr = scgd << cdf_width | cdf; 340 341 return 0; 342 } 343 344 /* 345 * We don't have a test case but the HW engineers say that the write order of 346 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR 347 * handling is outside of this function. First messages clear ICMSR before this 348 * function, interrupt handlers clear the relevant bits after this function. 349 */ 350 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 351 { 352 int read = !!rcar_i2c_is_recv(priv); 353 bool rep_start = !(priv->flags & ID_REP_AFTER_RD); 354 355 priv->pos = 0; 356 priv->flags &= ID_P_MASK; 357 358 if (priv->msgs_left == 1) 359 priv->flags |= ID_LAST_MSG; 360 361 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 362 if (priv->flags & ID_P_NOT_ATOMIC) 363 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 364 365 if (rep_start) 366 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 367 } 368 369 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv, 370 struct i2c_msg *msgs, int num) 371 { 372 priv->msg = msgs; 373 priv->msgs_left = num; 374 rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */ 375 rcar_i2c_prepare_msg(priv); 376 } 377 378 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 379 { 380 priv->msg++; 381 priv->msgs_left--; 382 rcar_i2c_prepare_msg(priv); 383 /* ICMSR handling must come afterwards in the irq handler */ 384 } 385 386 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate) 387 { 388 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 389 ? priv->dma_rx : priv->dma_tx; 390 391 /* only allowed from thread context! */ 392 if (terminate) 393 dmaengine_terminate_sync(chan); 394 395 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 396 sg_dma_len(&priv->sg), priv->dma_direction); 397 398 /* Gen3+ can only do one RXDMA per transfer and we just completed it */ 399 if (priv->devtype >= I2C_RCAR_GEN3 && 400 priv->dma_direction == DMA_FROM_DEVICE) 401 priv->flags |= ID_P_NO_RXDMA; 402 403 priv->dma_direction = DMA_NONE; 404 405 /* Disable DMA Master Received/Transmitted, must be last! */ 406 rcar_i2c_write(priv, ICDMAER, 0); 407 } 408 409 static void rcar_i2c_dma_callback(void *data) 410 { 411 struct rcar_i2c_priv *priv = data; 412 413 priv->pos += sg_dma_len(&priv->sg); 414 415 rcar_i2c_cleanup_dma(priv, false); 416 } 417 418 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 419 { 420 struct device *dev = rcar_i2c_priv_to_dev(priv); 421 struct i2c_msg *msg = priv->msg; 422 bool read = msg->flags & I2C_M_RD; 423 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 424 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 425 struct dma_async_tx_descriptor *txdesc; 426 dma_addr_t dma_addr; 427 dma_cookie_t cookie; 428 unsigned char *buf; 429 int len; 430 431 /* Do various checks to see if DMA is feasible at all */ 432 if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 433 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 434 return false; 435 436 if (read) { 437 /* 438 * The last two bytes needs to be fetched using PIO in 439 * order for the STOP phase to work. 440 */ 441 buf = priv->msg->buf; 442 len = priv->msg->len - 2; 443 } else { 444 /* 445 * First byte in message was sent using PIO. 446 */ 447 buf = priv->msg->buf + 1; 448 len = priv->msg->len - 1; 449 } 450 451 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 452 if (dma_mapping_error(chan->device->dev, dma_addr)) { 453 dev_dbg(dev, "dma map failed, using PIO\n"); 454 return false; 455 } 456 457 sg_dma_len(&priv->sg) = len; 458 sg_dma_address(&priv->sg) = dma_addr; 459 460 priv->dma_direction = dir; 461 462 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 463 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 464 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 465 if (!txdesc) { 466 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 467 rcar_i2c_cleanup_dma(priv, false); 468 return false; 469 } 470 471 txdesc->callback = rcar_i2c_dma_callback; 472 txdesc->callback_param = priv; 473 474 cookie = dmaengine_submit(txdesc); 475 if (dma_submit_error(cookie)) { 476 dev_dbg(dev, "submitting dma failed, using PIO\n"); 477 rcar_i2c_cleanup_dma(priv, false); 478 return false; 479 } 480 481 /* Enable DMA Master Received/Transmitted */ 482 if (read) 483 rcar_i2c_write(priv, ICDMAER, RMDMAE); 484 else 485 rcar_i2c_write(priv, ICDMAER, TMDMAE); 486 487 dma_async_issue_pending(chan); 488 return true; 489 } 490 491 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 492 { 493 struct i2c_msg *msg = priv->msg; 494 u32 irqs_to_clear = MDE; 495 496 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 497 if (!(msr & MDE)) 498 return; 499 500 if (msr & MAT) 501 irqs_to_clear |= MAT; 502 503 /* Check if DMA can be enabled and take over */ 504 if (priv->pos == 1 && rcar_i2c_dma(priv)) 505 return; 506 507 if (priv->pos < msg->len) { 508 /* 509 * Prepare next data to ICRXTX register. 510 * This data will go to _SHIFT_ register. 511 * 512 * * 513 * [ICRXTX] -> [SHIFT] -> [I2C bus] 514 */ 515 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 516 priv->pos++; 517 } else { 518 /* 519 * The last data was pushed to ICRXTX on _PREV_ empty irq. 520 * It is on _SHIFT_ register, and will sent to I2C bus. 521 * 522 * * 523 * [ICRXTX] -> [SHIFT] -> [I2C bus] 524 */ 525 526 if (priv->flags & ID_LAST_MSG) 527 /* 528 * If current msg is the _LAST_ msg, 529 * prepare stop condition here. 530 * ID_DONE will be set on STOP irq. 531 */ 532 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 533 else 534 rcar_i2c_next_msg(priv); 535 } 536 537 rcar_i2c_clear_irq(priv, irqs_to_clear); 538 } 539 540 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 541 { 542 struct i2c_msg *msg = priv->msg; 543 bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN; 544 u32 irqs_to_clear = MDR; 545 546 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 547 if (!(msr & MDR)) 548 return; 549 550 if (msr & MAT) { 551 irqs_to_clear |= MAT; 552 /* 553 * Address transfer phase finished, but no data at this point. 554 * Try to use DMA to receive data. 555 */ 556 rcar_i2c_dma(priv); 557 } else if (priv->pos < msg->len) { 558 /* get received data */ 559 u8 data = rcar_i2c_read(priv, ICRXTX); 560 561 msg->buf[priv->pos] = data; 562 if (recv_len_init) { 563 if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) { 564 priv->flags |= ID_DONE | ID_EPROTO; 565 return; 566 } 567 msg->len += msg->buf[0]; 568 /* Enough data for DMA? */ 569 if (rcar_i2c_dma(priv)) 570 return; 571 /* new length after RECV_LEN now properly initialized */ 572 recv_len_init = false; 573 } 574 priv->pos++; 575 } 576 577 /* 578 * If next received data is the _LAST_ and we are not waiting for a new 579 * length because of RECV_LEN, then go to a new phase. 580 */ 581 if (priv->pos + 1 == msg->len && !recv_len_init) { 582 if (priv->flags & ID_LAST_MSG) { 583 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 584 } else { 585 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 586 priv->flags |= ID_REP_AFTER_RD; 587 } 588 } 589 590 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 591 rcar_i2c_next_msg(priv); 592 593 rcar_i2c_clear_irq(priv, irqs_to_clear); 594 } 595 596 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 597 { 598 u32 ssr_raw, ssr_filtered; 599 u8 value; 600 601 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 602 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 603 604 if (!ssr_filtered) 605 return false; 606 607 /* address detected */ 608 if (ssr_filtered & SAR) { 609 /* read or write request */ 610 if (ssr_raw & STM) { 611 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 612 rcar_i2c_write(priv, ICRXTX, value); 613 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 614 } else { 615 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 616 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 617 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 618 } 619 620 /* Clear SSR, too, because of old STOPs to other clients than us */ 621 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 622 } 623 624 /* master sent stop */ 625 if (ssr_filtered & SSR) { 626 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 627 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 628 rcar_i2c_write(priv, ICSIER, SAR); 629 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 630 } 631 632 /* master wants to write to us */ 633 if (ssr_filtered & SDR) { 634 int ret; 635 636 value = rcar_i2c_read(priv, ICRXTX); 637 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 638 /* Send NACK in case of error */ 639 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 640 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 641 } 642 643 /* master wants to read from us */ 644 if (ssr_filtered & SDE) { 645 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 646 rcar_i2c_write(priv, ICRXTX, value); 647 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 648 } 649 650 return true; 651 } 652 653 /* 654 * This driver has a lock-free design because there are IP cores (at least 655 * R-Car Gen2) which have an inherent race condition in their hardware design. 656 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after 657 * the interrupt was generated, otherwise an unwanted repeated message gets 658 * generated. It turned out that taking a spinlock at the beginning of the ISR 659 * was already causing repeated messages. Thus, this driver was converted to 660 * the now lockless behaviour. Please keep this in mind when hacking the driver. 661 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are 662 * likely affected. Therefore, we have different interrupt handler entries. 663 */ 664 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr) 665 { 666 if (!msr) { 667 if (rcar_i2c_slave_irq(priv)) 668 return IRQ_HANDLED; 669 670 return IRQ_NONE; 671 } 672 673 /* Arbitration lost */ 674 if (msr & MAL) { 675 priv->flags |= ID_DONE | ID_ARBLOST; 676 goto out; 677 } 678 679 /* Nack */ 680 if (msr & MNR) { 681 /* HW automatically sends STOP after received NACK */ 682 if (priv->flags & ID_P_NOT_ATOMIC) 683 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 684 priv->flags |= ID_NACK; 685 goto out; 686 } 687 688 /* Stop */ 689 if (msr & MST) { 690 priv->msgs_left--; /* The last message also made it */ 691 priv->flags |= ID_DONE; 692 goto out; 693 } 694 695 if (rcar_i2c_is_recv(priv)) 696 rcar_i2c_irq_recv(priv, msr); 697 else 698 rcar_i2c_irq_send(priv, msr); 699 700 out: 701 if (priv->flags & ID_DONE) { 702 rcar_i2c_write(priv, ICMIER, 0); 703 rcar_i2c_write(priv, ICMSR, 0); 704 if (priv->flags & ID_P_NOT_ATOMIC) 705 wake_up(&priv->wait); 706 } 707 708 return IRQ_HANDLED; 709 } 710 711 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr) 712 { 713 struct rcar_i2c_priv *priv = ptr; 714 u32 msr; 715 716 /* Clear START or STOP immediately, except for REPSTART after read */ 717 if (likely(!(priv->flags & ID_REP_AFTER_RD))) 718 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 719 720 /* Only handle interrupts that are currently enabled */ 721 msr = rcar_i2c_read(priv, ICMSR); 722 if (priv->flags & ID_P_NOT_ATOMIC) 723 msr &= rcar_i2c_read(priv, ICMIER); 724 725 return rcar_i2c_irq(irq, priv, msr); 726 } 727 728 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr) 729 { 730 struct rcar_i2c_priv *priv = ptr; 731 u32 msr; 732 733 /* Only handle interrupts that are currently enabled */ 734 msr = rcar_i2c_read(priv, ICMSR); 735 if (priv->flags & ID_P_NOT_ATOMIC) 736 msr &= rcar_i2c_read(priv, ICMIER); 737 738 /* 739 * Clear START or STOP immediately, except for REPSTART after read or 740 * if a spurious interrupt was detected. 741 */ 742 if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr)) 743 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 744 745 return rcar_i2c_irq(irq, priv, msr); 746 } 747 748 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 749 enum dma_transfer_direction dir, 750 dma_addr_t port_addr) 751 { 752 struct dma_chan *chan; 753 struct dma_slave_config cfg; 754 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 755 int ret; 756 757 chan = dma_request_chan(dev, chan_name); 758 if (IS_ERR(chan)) { 759 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 760 chan_name, PTR_ERR(chan)); 761 return chan; 762 } 763 764 memset(&cfg, 0, sizeof(cfg)); 765 cfg.direction = dir; 766 if (dir == DMA_MEM_TO_DEV) { 767 cfg.dst_addr = port_addr; 768 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 769 } else { 770 cfg.src_addr = port_addr; 771 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 772 } 773 774 ret = dmaengine_slave_config(chan, &cfg); 775 if (ret) { 776 dev_dbg(dev, "slave_config failed for %s (%d)\n", 777 chan_name, ret); 778 dma_release_channel(chan); 779 return ERR_PTR(ret); 780 } 781 782 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 783 return chan; 784 } 785 786 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 787 struct i2c_msg *msg) 788 { 789 struct device *dev = rcar_i2c_priv_to_dev(priv); 790 bool read; 791 struct dma_chan *chan; 792 enum dma_transfer_direction dir; 793 794 read = msg->flags & I2C_M_RD; 795 796 chan = read ? priv->dma_rx : priv->dma_tx; 797 if (PTR_ERR(chan) != -EPROBE_DEFER) 798 return; 799 800 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 801 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 802 803 if (read) 804 priv->dma_rx = chan; 805 else 806 priv->dma_tx = chan; 807 } 808 809 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 810 { 811 if (!IS_ERR(priv->dma_tx)) { 812 dma_release_channel(priv->dma_tx); 813 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 814 } 815 816 if (!IS_ERR(priv->dma_rx)) { 817 dma_release_channel(priv->dma_rx); 818 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 819 } 820 } 821 822 /* I2C is a special case, we need to poll the status of a reset */ 823 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 824 { 825 int ret; 826 827 /* Don't reset if a slave instance is currently running */ 828 if (priv->slave) 829 return -EISCONN; 830 831 ret = reset_control_reset(priv->rstc); 832 if (ret) 833 return ret; 834 835 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1, 836 100, false, priv->rstc); 837 } 838 839 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 840 struct i2c_msg *msgs, 841 int num) 842 { 843 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 844 struct device *dev = rcar_i2c_priv_to_dev(priv); 845 int i, ret; 846 long time_left; 847 848 priv->flags |= ID_P_NOT_ATOMIC; 849 850 pm_runtime_get_sync(dev); 851 852 /* Check bus state before init otherwise bus busy info will be lost */ 853 ret = rcar_i2c_bus_barrier(priv); 854 if (ret < 0) 855 goto out; 856 857 /* Gen3+ needs a reset. That also allows RXDMA once */ 858 if (priv->devtype >= I2C_RCAR_GEN3) { 859 ret = rcar_i2c_do_reset(priv); 860 if (ret) 861 goto out; 862 priv->flags &= ~ID_P_NO_RXDMA; 863 } 864 865 rcar_i2c_init(priv); 866 867 for (i = 0; i < num; i++) 868 rcar_i2c_request_dma(priv, msgs + i); 869 870 rcar_i2c_first_msg(priv, msgs, num); 871 872 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 873 num * adap->timeout); 874 875 /* cleanup DMA if it couldn't complete properly due to an error */ 876 if (priv->dma_direction != DMA_NONE) 877 rcar_i2c_cleanup_dma(priv, true); 878 879 if (!time_left) { 880 rcar_i2c_init(priv); 881 ret = -ETIMEDOUT; 882 } else if (priv->flags & ID_NACK) { 883 ret = -ENXIO; 884 } else if (priv->flags & ID_ARBLOST) { 885 ret = -EAGAIN; 886 } else if (priv->flags & ID_EPROTO) { 887 ret = -EPROTO; 888 } else { 889 ret = num - priv->msgs_left; /* The number of transfer */ 890 } 891 out: 892 pm_runtime_put(dev); 893 894 if (ret < 0 && ret != -ENXIO) 895 dev_err(dev, "error %d : %x\n", ret, priv->flags); 896 897 return ret; 898 } 899 900 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap, 901 struct i2c_msg *msgs, 902 int num) 903 { 904 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 905 struct device *dev = rcar_i2c_priv_to_dev(priv); 906 unsigned long j; 907 bool time_left; 908 int ret; 909 910 priv->flags &= ~ID_P_NOT_ATOMIC; 911 912 pm_runtime_get_sync(dev); 913 914 /* Check bus state before init otherwise bus busy info will be lost */ 915 ret = rcar_i2c_bus_barrier(priv); 916 if (ret < 0) 917 goto out; 918 919 rcar_i2c_init(priv); 920 rcar_i2c_first_msg(priv, msgs, num); 921 922 j = jiffies + num * adap->timeout; 923 do { 924 u32 msr = rcar_i2c_read(priv, ICMSR); 925 926 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP; 927 928 if (msr) { 929 if (priv->devtype < I2C_RCAR_GEN3) 930 rcar_i2c_gen2_irq(0, priv); 931 else 932 rcar_i2c_gen3_irq(0, priv); 933 } 934 935 time_left = time_before_eq(jiffies, j); 936 } while (!(priv->flags & ID_DONE) && time_left); 937 938 if (!time_left) { 939 rcar_i2c_init(priv); 940 ret = -ETIMEDOUT; 941 } else if (priv->flags & ID_NACK) { 942 ret = -ENXIO; 943 } else if (priv->flags & ID_ARBLOST) { 944 ret = -EAGAIN; 945 } else if (priv->flags & ID_EPROTO) { 946 ret = -EPROTO; 947 } else { 948 ret = num - priv->msgs_left; /* The number of transfer */ 949 } 950 out: 951 pm_runtime_put(dev); 952 953 if (ret < 0 && ret != -ENXIO) 954 dev_err(dev, "error %d : %x\n", ret, priv->flags); 955 956 return ret; 957 } 958 959 static int rcar_reg_slave(struct i2c_client *slave) 960 { 961 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 962 963 if (priv->slave) 964 return -EBUSY; 965 966 if (slave->flags & I2C_CLIENT_TEN) 967 return -EAFNOSUPPORT; 968 969 /* Keep device active for slave address detection logic */ 970 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 971 972 priv->slave = slave; 973 rcar_i2c_write(priv, ICSAR, slave->addr); 974 rcar_i2c_write(priv, ICSSR, 0); 975 rcar_i2c_write(priv, ICSIER, SAR); 976 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 977 978 return 0; 979 } 980 981 static int rcar_unreg_slave(struct i2c_client *slave) 982 { 983 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 984 985 WARN_ON(!priv->slave); 986 987 /* ensure no irq is running before clearing ptr */ 988 disable_irq(priv->irq); 989 rcar_i2c_reset_slave(priv); 990 enable_irq(priv->irq); 991 992 priv->slave = NULL; 993 994 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 995 996 return 0; 997 } 998 999 static u32 rcar_i2c_func(struct i2c_adapter *adap) 1000 { 1001 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 1002 1003 /* 1004 * This HW can't do: 1005 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 1006 * I2C_M_NOSTART (automatically sends address after START) 1007 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 1008 */ 1009 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 1010 (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK); 1011 1012 if (priv->flags & ID_P_HOST_NOTIFY) 1013 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 1014 1015 return func; 1016 } 1017 1018 static const struct i2c_algorithm rcar_i2c_algo = { 1019 .master_xfer = rcar_i2c_master_xfer, 1020 .master_xfer_atomic = rcar_i2c_master_xfer_atomic, 1021 .functionality = rcar_i2c_func, 1022 .reg_slave = rcar_reg_slave, 1023 .unreg_slave = rcar_unreg_slave, 1024 }; 1025 1026 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 1027 .flags = I2C_AQ_NO_ZERO_LEN, 1028 }; 1029 1030 static const struct of_device_id rcar_i2c_dt_ids[] = { 1031 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 1032 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 1033 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 1034 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 1035 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 1036 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 1037 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 1038 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 1039 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 1040 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 1041 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 1042 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 1043 { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN4 }, 1044 {}, 1045 }; 1046 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 1047 1048 static int rcar_i2c_probe(struct platform_device *pdev) 1049 { 1050 struct rcar_i2c_priv *priv; 1051 struct i2c_adapter *adap; 1052 struct device *dev = &pdev->dev; 1053 unsigned long irqflags = 0; 1054 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq; 1055 int ret; 1056 1057 /* Otherwise logic will break because some bytes must always use PIO */ 1058 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 1059 1060 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 1061 if (!priv) 1062 return -ENOMEM; 1063 1064 priv->clk = devm_clk_get(dev, NULL); 1065 if (IS_ERR(priv->clk)) { 1066 dev_err(dev, "cannot get clock\n"); 1067 return PTR_ERR(priv->clk); 1068 } 1069 1070 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 1071 if (IS_ERR(priv->io)) 1072 return PTR_ERR(priv->io); 1073 1074 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 1075 init_waitqueue_head(&priv->wait); 1076 1077 adap = &priv->adap; 1078 adap->nr = pdev->id; 1079 adap->algo = &rcar_i2c_algo; 1080 adap->class = I2C_CLASS_DEPRECATED; 1081 adap->retries = 3; 1082 adap->dev.parent = dev; 1083 adap->dev.of_node = dev->of_node; 1084 adap->bus_recovery_info = &rcar_i2c_bri; 1085 adap->quirks = &rcar_i2c_quirks; 1086 i2c_set_adapdata(adap, priv); 1087 strscpy(adap->name, pdev->name, sizeof(adap->name)); 1088 1089 /* Init DMA */ 1090 sg_init_table(&priv->sg, 1); 1091 priv->dma_direction = DMA_NONE; 1092 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 1093 1094 /* Activate device for clock calculation */ 1095 pm_runtime_enable(dev); 1096 pm_runtime_get_sync(dev); 1097 ret = rcar_i2c_clock_calculate(priv); 1098 if (ret < 0) { 1099 pm_runtime_put(dev); 1100 goto out_pm_disable; 1101 } 1102 1103 /* Bring hardware to known state */ 1104 rcar_i2c_init(priv); 1105 rcar_i2c_reset_slave(priv); 1106 1107 if (priv->devtype < I2C_RCAR_GEN3) { 1108 irqflags |= IRQF_NO_THREAD; 1109 irqhandler = rcar_i2c_gen2_irq; 1110 } 1111 1112 /* Stay always active when multi-master to keep arbitration working */ 1113 if (of_property_read_bool(dev->of_node, "multi-master")) 1114 priv->flags |= ID_P_PM_BLOCKED; 1115 else 1116 pm_runtime_put(dev); 1117 1118 if (of_property_read_bool(dev->of_node, "smbus")) 1119 priv->flags |= ID_P_HOST_NOTIFY; 1120 1121 /* R-Car Gen3+ needs a reset before every transfer */ 1122 if (priv->devtype >= I2C_RCAR_GEN3) { 1123 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1124 if (IS_ERR(priv->rstc)) { 1125 ret = PTR_ERR(priv->rstc); 1126 goto out_pm_put; 1127 } 1128 1129 ret = reset_control_status(priv->rstc); 1130 if (ret < 0) 1131 goto out_pm_put; 1132 1133 /* hard reset disturbs HostNotify local target, so disable it */ 1134 priv->flags &= ~ID_P_HOST_NOTIFY; 1135 } 1136 1137 ret = platform_get_irq(pdev, 0); 1138 if (ret < 0) 1139 goto out_pm_put; 1140 priv->irq = ret; 1141 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1142 if (ret < 0) { 1143 dev_err(dev, "cannot get irq %d\n", priv->irq); 1144 goto out_pm_put; 1145 } 1146 1147 platform_set_drvdata(pdev, priv); 1148 1149 ret = i2c_add_numbered_adapter(adap); 1150 if (ret < 0) 1151 goto out_pm_put; 1152 1153 if (priv->flags & ID_P_HOST_NOTIFY) { 1154 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1155 if (IS_ERR(priv->host_notify_client)) { 1156 ret = PTR_ERR(priv->host_notify_client); 1157 goto out_del_device; 1158 } 1159 } 1160 1161 dev_info(dev, "probed\n"); 1162 1163 return 0; 1164 1165 out_del_device: 1166 i2c_del_adapter(&priv->adap); 1167 out_pm_put: 1168 if (priv->flags & ID_P_PM_BLOCKED) 1169 pm_runtime_put(dev); 1170 out_pm_disable: 1171 pm_runtime_disable(dev); 1172 return ret; 1173 } 1174 1175 static void rcar_i2c_remove(struct platform_device *pdev) 1176 { 1177 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1178 struct device *dev = &pdev->dev; 1179 1180 if (priv->host_notify_client) 1181 i2c_free_slave_host_notify_device(priv->host_notify_client); 1182 i2c_del_adapter(&priv->adap); 1183 rcar_i2c_release_dma(priv); 1184 if (priv->flags & ID_P_PM_BLOCKED) 1185 pm_runtime_put(dev); 1186 pm_runtime_disable(dev); 1187 } 1188 1189 static int rcar_i2c_suspend(struct device *dev) 1190 { 1191 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1192 1193 i2c_mark_adapter_suspended(&priv->adap); 1194 return 0; 1195 } 1196 1197 static int rcar_i2c_resume(struct device *dev) 1198 { 1199 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1200 1201 i2c_mark_adapter_resumed(&priv->adap); 1202 return 0; 1203 } 1204 1205 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1206 NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1207 }; 1208 1209 static struct platform_driver rcar_i2c_driver = { 1210 .driver = { 1211 .name = "i2c-rcar", 1212 .of_match_table = rcar_i2c_dt_ids, 1213 .pm = pm_sleep_ptr(&rcar_i2c_pm_ops), 1214 }, 1215 .probe = rcar_i2c_probe, 1216 .remove_new = rcar_i2c_remove, 1217 }; 1218 1219 module_platform_driver(rcar_i2c_driver); 1220 1221 MODULE_LICENSE("GPL v2"); 1222 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1223 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1224