1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 45 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 46 47 /* ICSCR */ 48 #define SDBS (1 << 3) /* slave data buffer select */ 49 #define SIE (1 << 2) /* slave interface enable */ 50 #define GCAE (1 << 1) /* general call address enable */ 51 #define FNA (1 << 0) /* forced non acknowledgment */ 52 53 /* ICMCR */ 54 #define MDBS (1 << 7) /* non-fifo mode switch */ 55 #define FSCL (1 << 6) /* override SCL pin */ 56 #define FSDA (1 << 5) /* override SDA pin */ 57 #define OBPC (1 << 4) /* override pins */ 58 #define MIE (1 << 3) /* master if enable */ 59 #define TSBE (1 << 2) 60 #define FSB (1 << 1) /* force stop bit */ 61 #define ESG (1 << 0) /* enable start bit gen */ 62 63 /* ICSSR (also for ICSIER) */ 64 #define GCAR (1 << 6) /* general call received */ 65 #define STM (1 << 5) /* slave transmit mode */ 66 #define SSR (1 << 4) /* stop received */ 67 #define SDE (1 << 3) /* slave data empty */ 68 #define SDT (1 << 2) /* slave data transmitted */ 69 #define SDR (1 << 1) /* slave data received */ 70 #define SAR (1 << 0) /* slave addr received */ 71 72 /* ICMSR (also for ICMIE) */ 73 #define MNR (1 << 6) /* nack received */ 74 #define MAL (1 << 5) /* arbitration lost */ 75 #define MST (1 << 4) /* sent a stop */ 76 #define MDE (1 << 3) 77 #define MDT (1 << 2) 78 #define MDR (1 << 1) 79 #define MAT (1 << 0) /* slave addr xfer done */ 80 81 /* ICDMAER */ 82 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 83 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 84 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 85 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 86 87 /* ICFBSCR */ 88 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 89 90 #define RCAR_MIN_DMA_LEN 8 91 92 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 93 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 94 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 95 96 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 97 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 98 #define RCAR_IRQ_STOP (MST) 99 100 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 101 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 102 103 #define ID_LAST_MSG (1 << 0) 104 #define ID_FIRST_MSG (1 << 1) 105 #define ID_DONE (1 << 2) 106 #define ID_ARBLOST (1 << 3) 107 #define ID_NACK (1 << 4) 108 /* persistent flags */ 109 #define ID_P_HOST_NOTIFY BIT(28) 110 #define ID_P_REP_AFTER_RD BIT(29) 111 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 112 #define ID_P_PM_BLOCKED BIT(31) 113 #define ID_P_MASK GENMASK(31, 28) 114 115 enum rcar_i2c_type { 116 I2C_RCAR_GEN1, 117 I2C_RCAR_GEN2, 118 I2C_RCAR_GEN3, 119 }; 120 121 struct rcar_i2c_priv { 122 u32 flags; 123 void __iomem *io; 124 struct i2c_adapter adap; 125 struct i2c_msg *msg; 126 int msgs_left; 127 struct clk *clk; 128 129 wait_queue_head_t wait; 130 131 int pos; 132 u32 icccr; 133 u8 recovery_icmcr; /* protected by adapter lock */ 134 enum rcar_i2c_type devtype; 135 struct i2c_client *slave; 136 137 struct resource *res; 138 struct dma_chan *dma_tx; 139 struct dma_chan *dma_rx; 140 struct scatterlist sg; 141 enum dma_data_direction dma_direction; 142 143 struct reset_control *rstc; 144 bool atomic_xfer; 145 int irq; 146 147 struct i2c_client *host_notify_client; 148 }; 149 150 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 151 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 152 153 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 154 { 155 writel(val, priv->io + reg); 156 } 157 158 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 159 { 160 return readl(priv->io + reg); 161 } 162 163 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 164 { 165 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 166 167 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 168 169 }; 170 171 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 172 { 173 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 174 175 if (val) 176 priv->recovery_icmcr |= FSCL; 177 else 178 priv->recovery_icmcr &= ~FSCL; 179 180 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 181 }; 182 183 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 184 { 185 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 186 187 if (val) 188 priv->recovery_icmcr |= FSDA; 189 else 190 priv->recovery_icmcr &= ~FSDA; 191 192 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 193 }; 194 195 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 196 { 197 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 198 199 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 200 201 }; 202 203 static struct i2c_bus_recovery_info rcar_i2c_bri = { 204 .get_scl = rcar_i2c_get_scl, 205 .set_scl = rcar_i2c_set_scl, 206 .set_sda = rcar_i2c_set_sda, 207 .get_bus_free = rcar_i2c_get_bus_free, 208 .recover_bus = i2c_generic_scl_recovery, 209 }; 210 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 211 { 212 /* reset master mode */ 213 rcar_i2c_write(priv, ICMIER, 0); 214 rcar_i2c_write(priv, ICMCR, MDBS); 215 rcar_i2c_write(priv, ICMSR, 0); 216 /* start clock */ 217 rcar_i2c_write(priv, ICCCR, priv->icccr); 218 219 if (priv->devtype == I2C_RCAR_GEN3) 220 rcar_i2c_write(priv, ICFBSCR, TCYC17); 221 222 } 223 224 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 225 { 226 int ret; 227 u32 val; 228 229 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 230 priv->adap.timeout); 231 if (ret) { 232 /* Waiting did not help, try to recover */ 233 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 234 ret = i2c_recover_bus(&priv->adap); 235 } 236 237 return ret; 238 } 239 240 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 241 { 242 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 243 unsigned long rate; 244 struct device *dev = rcar_i2c_priv_to_dev(priv); 245 struct i2c_timings t = { 246 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 247 .scl_fall_ns = 35, 248 .scl_rise_ns = 200, 249 .scl_int_delay_ns = 50, 250 }; 251 252 /* Fall back to previously used values if not supplied */ 253 i2c_parse_fw_timings(dev, &t, false); 254 255 switch (priv->devtype) { 256 case I2C_RCAR_GEN1: 257 cdf_width = 2; 258 break; 259 case I2C_RCAR_GEN2: 260 case I2C_RCAR_GEN3: 261 cdf_width = 3; 262 break; 263 default: 264 dev_err(dev, "device type error\n"); 265 return -EIO; 266 } 267 268 /* 269 * calculate SCL clock 270 * see 271 * ICCCR 272 * 273 * ick = clkp / (1 + CDF) 274 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 275 * 276 * ick : I2C internal clock < 20 MHz 277 * ticf : I2C SCL falling time 278 * tr : I2C SCL rising time 279 * intd : LSI internal delay 280 * clkp : peripheral_clk 281 * F[] : integer up-valuation 282 */ 283 rate = clk_get_rate(priv->clk); 284 cdf = rate / 20000000; 285 if (cdf >= 1U << cdf_width) { 286 dev_err(dev, "Input clock %lu too high\n", rate); 287 return -EIO; 288 } 289 ick = rate / (cdf + 1); 290 291 /* 292 * it is impossible to calculate large scale 293 * number on u32. separate it 294 * 295 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 296 * = F[sum * ick / 1000000000] 297 * = F[(ick / 1000000) * sum / 1000] 298 */ 299 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 300 round = (ick + 500000) / 1000000 * sum; 301 round = (round + 500) / 1000; 302 303 /* 304 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 305 * 306 * Calculation result (= SCL) should be less than 307 * bus_speed for hardware safety 308 * 309 * We could use something along the lines of 310 * div = ick / (bus_speed + 1) + 1; 311 * scgd = (div - 20 - round + 7) / 8; 312 * scl = ick / (20 + (scgd * 8) + round); 313 * (not fully verified) but that would get pretty involved 314 */ 315 for (scgd = 0; scgd < 0x40; scgd++) { 316 scl = ick / (20 + (scgd * 8) + round); 317 if (scl <= t.bus_freq_hz) 318 goto scgd_find; 319 } 320 dev_err(dev, "it is impossible to calculate best SCL\n"); 321 return -EIO; 322 323 scgd_find: 324 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 325 scl, t.bus_freq_hz, rate, round, cdf, scgd); 326 327 /* keep icccr value */ 328 priv->icccr = scgd << cdf_width | cdf; 329 330 return 0; 331 } 332 333 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 334 { 335 int read = !!rcar_i2c_is_recv(priv); 336 337 priv->pos = 0; 338 if (priv->msgs_left == 1) 339 priv->flags |= ID_LAST_MSG; 340 341 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 342 /* 343 * We don't have a test case but the HW engineers say that the write order 344 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 345 * it didn't cause a drawback for me, let's rather be safe than sorry. 346 */ 347 if (priv->flags & ID_FIRST_MSG) { 348 rcar_i2c_write(priv, ICMSR, 0); 349 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 350 } else { 351 if (priv->flags & ID_P_REP_AFTER_RD) 352 priv->flags &= ~ID_P_REP_AFTER_RD; 353 else 354 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 355 rcar_i2c_write(priv, ICMSR, 0); 356 } 357 358 if (!priv->atomic_xfer) 359 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 360 } 361 362 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 363 { 364 priv->msg++; 365 priv->msgs_left--; 366 priv->flags &= ID_P_MASK; 367 rcar_i2c_prepare_msg(priv); 368 } 369 370 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 371 { 372 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 373 ? priv->dma_rx : priv->dma_tx; 374 375 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 376 sg_dma_len(&priv->sg), priv->dma_direction); 377 378 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 379 if (priv->devtype == I2C_RCAR_GEN3 && 380 priv->dma_direction == DMA_FROM_DEVICE) 381 priv->flags |= ID_P_NO_RXDMA; 382 383 priv->dma_direction = DMA_NONE; 384 385 /* Disable DMA Master Received/Transmitted, must be last! */ 386 rcar_i2c_write(priv, ICDMAER, 0); 387 } 388 389 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 390 { 391 if (priv->dma_direction == DMA_NONE) 392 return; 393 else if (priv->dma_direction == DMA_FROM_DEVICE) 394 dmaengine_terminate_all(priv->dma_rx); 395 else if (priv->dma_direction == DMA_TO_DEVICE) 396 dmaengine_terminate_all(priv->dma_tx); 397 398 rcar_i2c_dma_unmap(priv); 399 } 400 401 static void rcar_i2c_dma_callback(void *data) 402 { 403 struct rcar_i2c_priv *priv = data; 404 405 priv->pos += sg_dma_len(&priv->sg); 406 407 rcar_i2c_dma_unmap(priv); 408 } 409 410 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 411 { 412 struct device *dev = rcar_i2c_priv_to_dev(priv); 413 struct i2c_msg *msg = priv->msg; 414 bool read = msg->flags & I2C_M_RD; 415 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 416 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 417 struct dma_async_tx_descriptor *txdesc; 418 dma_addr_t dma_addr; 419 dma_cookie_t cookie; 420 unsigned char *buf; 421 int len; 422 423 /* Do various checks to see if DMA is feasible at all */ 424 if (priv->atomic_xfer || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 425 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 426 return false; 427 428 if (read) { 429 /* 430 * The last two bytes needs to be fetched using PIO in 431 * order for the STOP phase to work. 432 */ 433 buf = priv->msg->buf; 434 len = priv->msg->len - 2; 435 } else { 436 /* 437 * First byte in message was sent using PIO. 438 */ 439 buf = priv->msg->buf + 1; 440 len = priv->msg->len - 1; 441 } 442 443 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 444 if (dma_mapping_error(chan->device->dev, dma_addr)) { 445 dev_dbg(dev, "dma map failed, using PIO\n"); 446 return false; 447 } 448 449 sg_dma_len(&priv->sg) = len; 450 sg_dma_address(&priv->sg) = dma_addr; 451 452 priv->dma_direction = dir; 453 454 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 455 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 456 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 457 if (!txdesc) { 458 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 459 rcar_i2c_cleanup_dma(priv); 460 return false; 461 } 462 463 txdesc->callback = rcar_i2c_dma_callback; 464 txdesc->callback_param = priv; 465 466 cookie = dmaengine_submit(txdesc); 467 if (dma_submit_error(cookie)) { 468 dev_dbg(dev, "submitting dma failed, using PIO\n"); 469 rcar_i2c_cleanup_dma(priv); 470 return false; 471 } 472 473 /* Enable DMA Master Received/Transmitted */ 474 if (read) 475 rcar_i2c_write(priv, ICDMAER, RMDMAE); 476 else 477 rcar_i2c_write(priv, ICDMAER, TMDMAE); 478 479 dma_async_issue_pending(chan); 480 return true; 481 } 482 483 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 484 { 485 struct i2c_msg *msg = priv->msg; 486 487 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 488 if (!(msr & MDE)) 489 return; 490 491 /* Check if DMA can be enabled and take over */ 492 if (priv->pos == 1 && rcar_i2c_dma(priv)) 493 return; 494 495 if (priv->pos < msg->len) { 496 /* 497 * Prepare next data to ICRXTX register. 498 * This data will go to _SHIFT_ register. 499 * 500 * * 501 * [ICRXTX] -> [SHIFT] -> [I2C bus] 502 */ 503 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 504 priv->pos++; 505 } else { 506 /* 507 * The last data was pushed to ICRXTX on _PREV_ empty irq. 508 * It is on _SHIFT_ register, and will sent to I2C bus. 509 * 510 * * 511 * [ICRXTX] -> [SHIFT] -> [I2C bus] 512 */ 513 514 if (priv->flags & ID_LAST_MSG) { 515 /* 516 * If current msg is the _LAST_ msg, 517 * prepare stop condition here. 518 * ID_DONE will be set on STOP irq. 519 */ 520 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 521 } else { 522 rcar_i2c_next_msg(priv); 523 return; 524 } 525 } 526 527 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 528 } 529 530 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 531 { 532 struct i2c_msg *msg = priv->msg; 533 534 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 535 if (!(msr & MDR)) 536 return; 537 538 if (msr & MAT) { 539 /* 540 * Address transfer phase finished, but no data at this point. 541 * Try to use DMA to receive data. 542 */ 543 rcar_i2c_dma(priv); 544 } else if (priv->pos < msg->len) { 545 /* get received data */ 546 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 547 priv->pos++; 548 } 549 550 /* If next received data is the _LAST_, go to new phase. */ 551 if (priv->pos + 1 == msg->len) { 552 if (priv->flags & ID_LAST_MSG) { 553 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 554 } else { 555 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 556 priv->flags |= ID_P_REP_AFTER_RD; 557 } 558 } 559 560 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 561 rcar_i2c_next_msg(priv); 562 else 563 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 564 } 565 566 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 567 { 568 u32 ssr_raw, ssr_filtered; 569 u8 value; 570 571 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 572 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 573 574 if (!ssr_filtered) 575 return false; 576 577 /* address detected */ 578 if (ssr_filtered & SAR) { 579 /* read or write request */ 580 if (ssr_raw & STM) { 581 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 582 rcar_i2c_write(priv, ICRXTX, value); 583 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 584 } else { 585 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 586 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 587 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 588 } 589 590 /* Clear SSR, too, because of old STOPs to other clients than us */ 591 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 592 } 593 594 /* master sent stop */ 595 if (ssr_filtered & SSR) { 596 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 597 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 598 rcar_i2c_write(priv, ICSIER, SAR); 599 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 600 } 601 602 /* master wants to write to us */ 603 if (ssr_filtered & SDR) { 604 int ret; 605 606 value = rcar_i2c_read(priv, ICRXTX); 607 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 608 /* Send NACK in case of error */ 609 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 610 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 611 } 612 613 /* master wants to read from us */ 614 if (ssr_filtered & SDE) { 615 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 616 rcar_i2c_write(priv, ICRXTX, value); 617 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 618 } 619 620 return true; 621 } 622 623 /* 624 * This driver has a lock-free design because there are IP cores (at least 625 * R-Car Gen2) which have an inherent race condition in their hardware design. 626 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after 627 * the interrupt was generated, otherwise an unwanted repeated message gets 628 * generated. It turned out that taking a spinlock at the beginning of the ISR 629 * was already causing repeated messages. Thus, this driver was converted to 630 * the now lockless behaviour. Please keep this in mind when hacking the driver. 631 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are 632 * likely affected. Therefore, we have different interrupt handler entries. 633 */ 634 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr) 635 { 636 if (!msr) { 637 if (rcar_i2c_slave_irq(priv)) 638 return IRQ_HANDLED; 639 640 return IRQ_NONE; 641 } 642 643 /* Arbitration lost */ 644 if (msr & MAL) { 645 priv->flags |= ID_DONE | ID_ARBLOST; 646 goto out; 647 } 648 649 /* Nack */ 650 if (msr & MNR) { 651 /* HW automatically sends STOP after received NACK */ 652 if (!priv->atomic_xfer) 653 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 654 priv->flags |= ID_NACK; 655 goto out; 656 } 657 658 /* Stop */ 659 if (msr & MST) { 660 priv->msgs_left--; /* The last message also made it */ 661 priv->flags |= ID_DONE; 662 goto out; 663 } 664 665 if (rcar_i2c_is_recv(priv)) 666 rcar_i2c_irq_recv(priv, msr); 667 else 668 rcar_i2c_irq_send(priv, msr); 669 670 out: 671 if (priv->flags & ID_DONE) { 672 rcar_i2c_write(priv, ICMIER, 0); 673 rcar_i2c_write(priv, ICMSR, 0); 674 if (!priv->atomic_xfer) 675 wake_up(&priv->wait); 676 } 677 678 return IRQ_HANDLED; 679 } 680 681 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr) 682 { 683 struct rcar_i2c_priv *priv = ptr; 684 u32 msr; 685 686 /* Clear START or STOP immediately, except for REPSTART after read */ 687 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) 688 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 689 690 /* Only handle interrupts that are currently enabled */ 691 msr = rcar_i2c_read(priv, ICMSR); 692 if (!priv->atomic_xfer) 693 msr &= rcar_i2c_read(priv, ICMIER); 694 695 return rcar_i2c_irq(irq, priv, msr); 696 } 697 698 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr) 699 { 700 struct rcar_i2c_priv *priv = ptr; 701 u32 msr; 702 703 /* Only handle interrupts that are currently enabled */ 704 msr = rcar_i2c_read(priv, ICMSR); 705 if (!priv->atomic_xfer) 706 msr &= rcar_i2c_read(priv, ICMIER); 707 708 /* 709 * Clear START or STOP immediately, except for REPSTART after read or 710 * if a spurious interrupt was detected. 711 */ 712 if (likely(!(priv->flags & ID_P_REP_AFTER_RD) && msr)) 713 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 714 715 return rcar_i2c_irq(irq, priv, msr); 716 } 717 718 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 719 enum dma_transfer_direction dir, 720 dma_addr_t port_addr) 721 { 722 struct dma_chan *chan; 723 struct dma_slave_config cfg; 724 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 725 int ret; 726 727 chan = dma_request_chan(dev, chan_name); 728 if (IS_ERR(chan)) { 729 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 730 chan_name, PTR_ERR(chan)); 731 return chan; 732 } 733 734 memset(&cfg, 0, sizeof(cfg)); 735 cfg.direction = dir; 736 if (dir == DMA_MEM_TO_DEV) { 737 cfg.dst_addr = port_addr; 738 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 739 } else { 740 cfg.src_addr = port_addr; 741 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 742 } 743 744 ret = dmaengine_slave_config(chan, &cfg); 745 if (ret) { 746 dev_dbg(dev, "slave_config failed for %s (%d)\n", 747 chan_name, ret); 748 dma_release_channel(chan); 749 return ERR_PTR(ret); 750 } 751 752 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 753 return chan; 754 } 755 756 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 757 struct i2c_msg *msg) 758 { 759 struct device *dev = rcar_i2c_priv_to_dev(priv); 760 bool read; 761 struct dma_chan *chan; 762 enum dma_transfer_direction dir; 763 764 read = msg->flags & I2C_M_RD; 765 766 chan = read ? priv->dma_rx : priv->dma_tx; 767 if (PTR_ERR(chan) != -EPROBE_DEFER) 768 return; 769 770 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 771 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 772 773 if (read) 774 priv->dma_rx = chan; 775 else 776 priv->dma_tx = chan; 777 } 778 779 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 780 { 781 if (!IS_ERR(priv->dma_tx)) { 782 dma_release_channel(priv->dma_tx); 783 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 784 } 785 786 if (!IS_ERR(priv->dma_rx)) { 787 dma_release_channel(priv->dma_rx); 788 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 789 } 790 } 791 792 /* I2C is a special case, we need to poll the status of a reset */ 793 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 794 { 795 int ret; 796 797 ret = reset_control_reset(priv->rstc); 798 if (ret) 799 return ret; 800 801 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1, 802 100, false, priv->rstc); 803 } 804 805 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 806 struct i2c_msg *msgs, 807 int num) 808 { 809 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 810 struct device *dev = rcar_i2c_priv_to_dev(priv); 811 int i, ret; 812 long time_left; 813 814 priv->atomic_xfer = false; 815 816 pm_runtime_get_sync(dev); 817 818 /* Check bus state before init otherwise bus busy info will be lost */ 819 ret = rcar_i2c_bus_barrier(priv); 820 if (ret < 0) 821 goto out; 822 823 /* Gen3 needs a reset before allowing RXDMA once */ 824 if (priv->devtype == I2C_RCAR_GEN3) { 825 priv->flags |= ID_P_NO_RXDMA; 826 if (!IS_ERR(priv->rstc)) { 827 ret = rcar_i2c_do_reset(priv); 828 if (ret == 0) 829 priv->flags &= ~ID_P_NO_RXDMA; 830 } 831 } 832 833 rcar_i2c_init(priv); 834 835 for (i = 0; i < num; i++) 836 rcar_i2c_request_dma(priv, msgs + i); 837 838 /* init first message */ 839 priv->msg = msgs; 840 priv->msgs_left = num; 841 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 842 rcar_i2c_prepare_msg(priv); 843 844 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 845 num * adap->timeout); 846 847 /* cleanup DMA if it couldn't complete properly due to an error */ 848 if (priv->dma_direction != DMA_NONE) 849 rcar_i2c_cleanup_dma(priv); 850 851 if (!time_left) { 852 rcar_i2c_init(priv); 853 ret = -ETIMEDOUT; 854 } else if (priv->flags & ID_NACK) { 855 ret = -ENXIO; 856 } else if (priv->flags & ID_ARBLOST) { 857 ret = -EAGAIN; 858 } else { 859 ret = num - priv->msgs_left; /* The number of transfer */ 860 } 861 out: 862 pm_runtime_put(dev); 863 864 if (ret < 0 && ret != -ENXIO) 865 dev_err(dev, "error %d : %x\n", ret, priv->flags); 866 867 return ret; 868 } 869 870 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap, 871 struct i2c_msg *msgs, 872 int num) 873 { 874 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 875 struct device *dev = rcar_i2c_priv_to_dev(priv); 876 unsigned long j; 877 bool time_left; 878 int ret; 879 880 priv->atomic_xfer = true; 881 882 pm_runtime_get_sync(dev); 883 884 /* Check bus state before init otherwise bus busy info will be lost */ 885 ret = rcar_i2c_bus_barrier(priv); 886 if (ret < 0) 887 goto out; 888 889 rcar_i2c_init(priv); 890 891 /* init first message */ 892 priv->msg = msgs; 893 priv->msgs_left = num; 894 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 895 rcar_i2c_prepare_msg(priv); 896 897 j = jiffies + num * adap->timeout; 898 do { 899 u32 msr = rcar_i2c_read(priv, ICMSR); 900 901 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP; 902 903 if (msr) { 904 if (priv->devtype < I2C_RCAR_GEN3) 905 rcar_i2c_gen2_irq(0, priv); 906 else 907 rcar_i2c_gen3_irq(0, priv); 908 } 909 910 time_left = time_before_eq(jiffies, j); 911 } while (!(priv->flags & ID_DONE) && time_left); 912 913 if (!time_left) { 914 rcar_i2c_init(priv); 915 ret = -ETIMEDOUT; 916 } else if (priv->flags & ID_NACK) { 917 ret = -ENXIO; 918 } else if (priv->flags & ID_ARBLOST) { 919 ret = -EAGAIN; 920 } else { 921 ret = num - priv->msgs_left; /* The number of transfer */ 922 } 923 out: 924 pm_runtime_put(dev); 925 926 if (ret < 0 && ret != -ENXIO) 927 dev_err(dev, "error %d : %x\n", ret, priv->flags); 928 929 return ret; 930 } 931 932 static int rcar_reg_slave(struct i2c_client *slave) 933 { 934 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 935 936 if (priv->slave) 937 return -EBUSY; 938 939 if (slave->flags & I2C_CLIENT_TEN) 940 return -EAFNOSUPPORT; 941 942 /* Keep device active for slave address detection logic */ 943 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 944 945 priv->slave = slave; 946 rcar_i2c_write(priv, ICSAR, slave->addr); 947 rcar_i2c_write(priv, ICSSR, 0); 948 rcar_i2c_write(priv, ICSIER, SAR); 949 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 950 951 return 0; 952 } 953 954 static int rcar_unreg_slave(struct i2c_client *slave) 955 { 956 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 957 958 WARN_ON(!priv->slave); 959 960 /* ensure no irq is running before clearing ptr */ 961 disable_irq(priv->irq); 962 rcar_i2c_write(priv, ICSIER, 0); 963 rcar_i2c_write(priv, ICSSR, 0); 964 enable_irq(priv->irq); 965 rcar_i2c_write(priv, ICSCR, SDBS); 966 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 967 968 priv->slave = NULL; 969 970 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 971 972 return 0; 973 } 974 975 static u32 rcar_i2c_func(struct i2c_adapter *adap) 976 { 977 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 978 979 /* 980 * This HW can't do: 981 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 982 * I2C_M_NOSTART (automatically sends address after START) 983 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 984 */ 985 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 986 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 987 988 if (priv->flags & ID_P_HOST_NOTIFY) 989 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 990 991 return func; 992 } 993 994 static const struct i2c_algorithm rcar_i2c_algo = { 995 .master_xfer = rcar_i2c_master_xfer, 996 .master_xfer_atomic = rcar_i2c_master_xfer_atomic, 997 .functionality = rcar_i2c_func, 998 .reg_slave = rcar_reg_slave, 999 .unreg_slave = rcar_unreg_slave, 1000 }; 1001 1002 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 1003 .flags = I2C_AQ_NO_ZERO_LEN, 1004 }; 1005 1006 static const struct of_device_id rcar_i2c_dt_ids[] = { 1007 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 1008 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 1009 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 1010 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 1011 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 1012 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 1013 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 1014 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 1015 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 1016 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 1017 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 1018 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 1019 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 1020 {}, 1021 }; 1022 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 1023 1024 static int rcar_i2c_probe(struct platform_device *pdev) 1025 { 1026 struct rcar_i2c_priv *priv; 1027 struct i2c_adapter *adap; 1028 struct device *dev = &pdev->dev; 1029 unsigned long irqflags = 0; 1030 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq; 1031 int ret; 1032 1033 /* Otherwise logic will break because some bytes must always use PIO */ 1034 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 1035 1036 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 1037 if (!priv) 1038 return -ENOMEM; 1039 1040 priv->clk = devm_clk_get(dev, NULL); 1041 if (IS_ERR(priv->clk)) { 1042 dev_err(dev, "cannot get clock\n"); 1043 return PTR_ERR(priv->clk); 1044 } 1045 1046 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 1047 if (IS_ERR(priv->io)) 1048 return PTR_ERR(priv->io); 1049 1050 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 1051 init_waitqueue_head(&priv->wait); 1052 1053 adap = &priv->adap; 1054 adap->nr = pdev->id; 1055 adap->algo = &rcar_i2c_algo; 1056 adap->class = I2C_CLASS_DEPRECATED; 1057 adap->retries = 3; 1058 adap->dev.parent = dev; 1059 adap->dev.of_node = dev->of_node; 1060 adap->bus_recovery_info = &rcar_i2c_bri; 1061 adap->quirks = &rcar_i2c_quirks; 1062 i2c_set_adapdata(adap, priv); 1063 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 1064 1065 /* Init DMA */ 1066 sg_init_table(&priv->sg, 1); 1067 priv->dma_direction = DMA_NONE; 1068 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 1069 1070 /* Activate device for clock calculation */ 1071 pm_runtime_enable(dev); 1072 pm_runtime_get_sync(dev); 1073 ret = rcar_i2c_clock_calculate(priv); 1074 if (ret < 0) 1075 goto out_pm_put; 1076 1077 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 1078 1079 if (priv->devtype < I2C_RCAR_GEN3) { 1080 irqflags |= IRQF_NO_THREAD; 1081 irqhandler = rcar_i2c_gen2_irq; 1082 } 1083 1084 if (priv->devtype == I2C_RCAR_GEN3) { 1085 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1086 if (!IS_ERR(priv->rstc)) { 1087 ret = reset_control_status(priv->rstc); 1088 if (ret < 0) 1089 priv->rstc = ERR_PTR(-ENOTSUPP); 1090 } 1091 } 1092 1093 /* Stay always active when multi-master to keep arbitration working */ 1094 if (of_property_read_bool(dev->of_node, "multi-master")) 1095 priv->flags |= ID_P_PM_BLOCKED; 1096 else 1097 pm_runtime_put(dev); 1098 1099 if (of_property_read_bool(dev->of_node, "smbus")) 1100 priv->flags |= ID_P_HOST_NOTIFY; 1101 1102 ret = platform_get_irq(pdev, 0); 1103 if (ret < 0) 1104 goto out_pm_disable; 1105 priv->irq = ret; 1106 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1107 if (ret < 0) { 1108 dev_err(dev, "cannot get irq %d\n", priv->irq); 1109 goto out_pm_disable; 1110 } 1111 1112 platform_set_drvdata(pdev, priv); 1113 1114 ret = i2c_add_numbered_adapter(adap); 1115 if (ret < 0) 1116 goto out_pm_disable; 1117 1118 if (priv->flags & ID_P_HOST_NOTIFY) { 1119 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1120 if (IS_ERR(priv->host_notify_client)) { 1121 ret = PTR_ERR(priv->host_notify_client); 1122 goto out_del_device; 1123 } 1124 } 1125 1126 dev_info(dev, "probed\n"); 1127 1128 return 0; 1129 1130 out_del_device: 1131 i2c_del_adapter(&priv->adap); 1132 out_pm_put: 1133 pm_runtime_put(dev); 1134 out_pm_disable: 1135 pm_runtime_disable(dev); 1136 return ret; 1137 } 1138 1139 static int rcar_i2c_remove(struct platform_device *pdev) 1140 { 1141 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1142 struct device *dev = &pdev->dev; 1143 1144 if (priv->host_notify_client) 1145 i2c_free_slave_host_notify_device(priv->host_notify_client); 1146 i2c_del_adapter(&priv->adap); 1147 rcar_i2c_release_dma(priv); 1148 if (priv->flags & ID_P_PM_BLOCKED) 1149 pm_runtime_put(dev); 1150 pm_runtime_disable(dev); 1151 1152 return 0; 1153 } 1154 1155 #ifdef CONFIG_PM_SLEEP 1156 static int rcar_i2c_suspend(struct device *dev) 1157 { 1158 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1159 1160 i2c_mark_adapter_suspended(&priv->adap); 1161 return 0; 1162 } 1163 1164 static int rcar_i2c_resume(struct device *dev) 1165 { 1166 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1167 1168 i2c_mark_adapter_resumed(&priv->adap); 1169 return 0; 1170 } 1171 1172 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1173 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1174 }; 1175 1176 #define DEV_PM_OPS (&rcar_i2c_pm_ops) 1177 #else 1178 #define DEV_PM_OPS NULL 1179 #endif /* CONFIG_PM_SLEEP */ 1180 1181 static struct platform_driver rcar_i2c_driver = { 1182 .driver = { 1183 .name = "i2c-rcar", 1184 .of_match_table = rcar_i2c_dt_ids, 1185 .pm = DEV_PM_OPS, 1186 }, 1187 .probe = rcar_i2c_probe, 1188 .remove = rcar_i2c_remove, 1189 }; 1190 1191 module_platform_driver(rcar_i2c_driver); 1192 1193 MODULE_LICENSE("GPL v2"); 1194 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1195 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1196