1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/i2c.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 /* register offsets */ 32 #define ICSCR 0x00 /* slave ctrl */ 33 #define ICMCR 0x04 /* master ctrl */ 34 #define ICSSR 0x08 /* slave status */ 35 #define ICMSR 0x0C /* master status */ 36 #define ICSIER 0x10 /* slave irq enable */ 37 #define ICMIER 0x14 /* master irq enable */ 38 #define ICCCR 0x18 /* clock dividers */ 39 #define ICSAR 0x1C /* slave address */ 40 #define ICMAR 0x20 /* master address */ 41 #define ICRXTX 0x24 /* data port */ 42 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 43 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 44 45 /* ICSCR */ 46 #define SDBS (1 << 3) /* slave data buffer select */ 47 #define SIE (1 << 2) /* slave interface enable */ 48 #define GCAE (1 << 1) /* general call address enable */ 49 #define FNA (1 << 0) /* forced non acknowledgment */ 50 51 /* ICMCR */ 52 #define MDBS (1 << 7) /* non-fifo mode switch */ 53 #define FSCL (1 << 6) /* override SCL pin */ 54 #define FSDA (1 << 5) /* override SDA pin */ 55 #define OBPC (1 << 4) /* override pins */ 56 #define MIE (1 << 3) /* master if enable */ 57 #define TSBE (1 << 2) 58 #define FSB (1 << 1) /* force stop bit */ 59 #define ESG (1 << 0) /* enable start bit gen */ 60 61 /* ICSSR (also for ICSIER) */ 62 #define GCAR (1 << 6) /* general call received */ 63 #define STM (1 << 5) /* slave transmit mode */ 64 #define SSR (1 << 4) /* stop received */ 65 #define SDE (1 << 3) /* slave data empty */ 66 #define SDT (1 << 2) /* slave data transmitted */ 67 #define SDR (1 << 1) /* slave data received */ 68 #define SAR (1 << 0) /* slave addr received */ 69 70 /* ICMSR (also for ICMIE) */ 71 #define MNR (1 << 6) /* nack received */ 72 #define MAL (1 << 5) /* arbitration lost */ 73 #define MST (1 << 4) /* sent a stop */ 74 #define MDE (1 << 3) 75 #define MDT (1 << 2) 76 #define MDR (1 << 1) 77 #define MAT (1 << 0) /* slave addr xfer done */ 78 79 /* ICDMAER */ 80 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 81 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 82 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 83 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 84 85 /* ICFBSCR */ 86 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 87 88 89 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 90 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 91 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) 92 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 93 94 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 95 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 96 #define RCAR_IRQ_STOP (MST) 97 98 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 99 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 100 101 #define ID_LAST_MSG (1 << 0) 102 #define ID_FIRST_MSG (1 << 1) 103 #define ID_DONE (1 << 2) 104 #define ID_ARBLOST (1 << 3) 105 #define ID_NACK (1 << 4) 106 /* persistent flags */ 107 #define ID_P_REP_AFTER_RD BIT(29) 108 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 109 #define ID_P_PM_BLOCKED BIT(31) 110 #define ID_P_MASK GENMASK(31, 29) 111 112 enum rcar_i2c_type { 113 I2C_RCAR_GEN1, 114 I2C_RCAR_GEN2, 115 I2C_RCAR_GEN3, 116 }; 117 118 struct rcar_i2c_priv { 119 void __iomem *io; 120 struct i2c_adapter adap; 121 struct i2c_msg *msg; 122 int msgs_left; 123 struct clk *clk; 124 125 wait_queue_head_t wait; 126 127 int pos; 128 u32 icccr; 129 u32 flags; 130 u8 recovery_icmcr; /* protected by adapter lock */ 131 enum rcar_i2c_type devtype; 132 struct i2c_client *slave; 133 134 struct resource *res; 135 struct dma_chan *dma_tx; 136 struct dma_chan *dma_rx; 137 struct scatterlist sg; 138 enum dma_data_direction dma_direction; 139 140 struct reset_control *rstc; 141 }; 142 143 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 144 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 145 146 #define LOOP_TIMEOUT 1024 147 148 149 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 150 { 151 writel(val, priv->io + reg); 152 } 153 154 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 155 { 156 return readl(priv->io + reg); 157 } 158 159 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 160 { 161 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 162 163 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 164 165 }; 166 167 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 168 { 169 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 170 171 if (val) 172 priv->recovery_icmcr |= FSCL; 173 else 174 priv->recovery_icmcr &= ~FSCL; 175 176 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 177 }; 178 179 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 180 { 181 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 182 183 if (val) 184 priv->recovery_icmcr |= FSDA; 185 else 186 priv->recovery_icmcr &= ~FSDA; 187 188 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 189 }; 190 191 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 192 { 193 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 194 195 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 196 197 }; 198 199 static struct i2c_bus_recovery_info rcar_i2c_bri = { 200 .get_scl = rcar_i2c_get_scl, 201 .set_scl = rcar_i2c_set_scl, 202 .set_sda = rcar_i2c_set_sda, 203 .get_bus_free = rcar_i2c_get_bus_free, 204 .recover_bus = i2c_generic_scl_recovery, 205 }; 206 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 207 { 208 /* reset master mode */ 209 rcar_i2c_write(priv, ICMIER, 0); 210 rcar_i2c_write(priv, ICMCR, MDBS); 211 rcar_i2c_write(priv, ICMSR, 0); 212 /* start clock */ 213 rcar_i2c_write(priv, ICCCR, priv->icccr); 214 215 if (priv->devtype == I2C_RCAR_GEN3) 216 rcar_i2c_write(priv, ICFBSCR, TCYC17); 217 218 } 219 220 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 221 { 222 int i; 223 224 for (i = 0; i < LOOP_TIMEOUT; i++) { 225 /* make sure that bus is not busy */ 226 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 227 return 0; 228 udelay(1); 229 } 230 231 /* Waiting did not help, try to recover */ 232 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 233 return i2c_recover_bus(&priv->adap); 234 } 235 236 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) 237 { 238 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 239 unsigned long rate; 240 struct device *dev = rcar_i2c_priv_to_dev(priv); 241 242 /* Fall back to previously used values if not supplied */ 243 t->bus_freq_hz = t->bus_freq_hz ?: 100000; 244 t->scl_fall_ns = t->scl_fall_ns ?: 35; 245 t->scl_rise_ns = t->scl_rise_ns ?: 200; 246 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; 247 248 switch (priv->devtype) { 249 case I2C_RCAR_GEN1: 250 cdf_width = 2; 251 break; 252 case I2C_RCAR_GEN2: 253 case I2C_RCAR_GEN3: 254 cdf_width = 3; 255 break; 256 default: 257 dev_err(dev, "device type error\n"); 258 return -EIO; 259 } 260 261 /* 262 * calculate SCL clock 263 * see 264 * ICCCR 265 * 266 * ick = clkp / (1 + CDF) 267 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 268 * 269 * ick : I2C internal clock < 20 MHz 270 * ticf : I2C SCL falling time 271 * tr : I2C SCL rising time 272 * intd : LSI internal delay 273 * clkp : peripheral_clk 274 * F[] : integer up-valuation 275 */ 276 rate = clk_get_rate(priv->clk); 277 cdf = rate / 20000000; 278 if (cdf >= 1U << cdf_width) { 279 dev_err(dev, "Input clock %lu too high\n", rate); 280 return -EIO; 281 } 282 ick = rate / (cdf + 1); 283 284 /* 285 * it is impossible to calculate large scale 286 * number on u32. separate it 287 * 288 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 289 * = F[sum * ick / 1000000000] 290 * = F[(ick / 1000000) * sum / 1000] 291 */ 292 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; 293 round = (ick + 500000) / 1000000 * sum; 294 round = (round + 500) / 1000; 295 296 /* 297 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 298 * 299 * Calculation result (= SCL) should be less than 300 * bus_speed for hardware safety 301 * 302 * We could use something along the lines of 303 * div = ick / (bus_speed + 1) + 1; 304 * scgd = (div - 20 - round + 7) / 8; 305 * scl = ick / (20 + (scgd * 8) + round); 306 * (not fully verified) but that would get pretty involved 307 */ 308 for (scgd = 0; scgd < 0x40; scgd++) { 309 scl = ick / (20 + (scgd * 8) + round); 310 if (scl <= t->bus_freq_hz) 311 goto scgd_find; 312 } 313 dev_err(dev, "it is impossible to calculate best SCL\n"); 314 return -EIO; 315 316 scgd_find: 317 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 318 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); 319 320 /* keep icccr value */ 321 priv->icccr = scgd << cdf_width | cdf; 322 323 return 0; 324 } 325 326 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 327 { 328 int read = !!rcar_i2c_is_recv(priv); 329 330 priv->pos = 0; 331 if (priv->msgs_left == 1) 332 priv->flags |= ID_LAST_MSG; 333 334 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 335 /* 336 * We don't have a test case but the HW engineers say that the write order 337 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 338 * it didn't cause a drawback for me, let's rather be safe than sorry. 339 */ 340 if (priv->flags & ID_FIRST_MSG) { 341 rcar_i2c_write(priv, ICMSR, 0); 342 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 343 } else { 344 if (priv->flags & ID_P_REP_AFTER_RD) 345 priv->flags &= ~ID_P_REP_AFTER_RD; 346 else 347 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 348 rcar_i2c_write(priv, ICMSR, 0); 349 } 350 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 351 } 352 353 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 354 { 355 priv->msg++; 356 priv->msgs_left--; 357 priv->flags &= ID_P_MASK; 358 rcar_i2c_prepare_msg(priv); 359 } 360 361 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 362 { 363 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 364 ? priv->dma_rx : priv->dma_tx; 365 366 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 367 sg_dma_len(&priv->sg), priv->dma_direction); 368 369 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 370 if (priv->devtype == I2C_RCAR_GEN3 && 371 priv->dma_direction == DMA_FROM_DEVICE) 372 priv->flags |= ID_P_NO_RXDMA; 373 374 priv->dma_direction = DMA_NONE; 375 376 /* Disable DMA Master Received/Transmitted, must be last! */ 377 rcar_i2c_write(priv, ICDMAER, 0); 378 } 379 380 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 381 { 382 if (priv->dma_direction == DMA_NONE) 383 return; 384 else if (priv->dma_direction == DMA_FROM_DEVICE) 385 dmaengine_terminate_all(priv->dma_rx); 386 else if (priv->dma_direction == DMA_TO_DEVICE) 387 dmaengine_terminate_all(priv->dma_tx); 388 389 rcar_i2c_dma_unmap(priv); 390 } 391 392 static void rcar_i2c_dma_callback(void *data) 393 { 394 struct rcar_i2c_priv *priv = data; 395 396 priv->pos += sg_dma_len(&priv->sg); 397 398 rcar_i2c_dma_unmap(priv); 399 } 400 401 static void rcar_i2c_dma(struct rcar_i2c_priv *priv) 402 { 403 struct device *dev = rcar_i2c_priv_to_dev(priv); 404 struct i2c_msg *msg = priv->msg; 405 bool read = msg->flags & I2C_M_RD; 406 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 407 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 408 struct dma_async_tx_descriptor *txdesc; 409 dma_addr_t dma_addr; 410 dma_cookie_t cookie; 411 unsigned char *buf; 412 int len; 413 414 /* Do various checks to see if DMA is feasible at all */ 415 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) || 416 (read && priv->flags & ID_P_NO_RXDMA)) 417 return; 418 419 if (read) { 420 /* 421 * The last two bytes needs to be fetched using PIO in 422 * order for the STOP phase to work. 423 */ 424 buf = priv->msg->buf; 425 len = priv->msg->len - 2; 426 } else { 427 /* 428 * First byte in message was sent using PIO. 429 */ 430 buf = priv->msg->buf + 1; 431 len = priv->msg->len - 1; 432 } 433 434 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 435 if (dma_mapping_error(chan->device->dev, dma_addr)) { 436 dev_dbg(dev, "dma map failed, using PIO\n"); 437 return; 438 } 439 440 sg_dma_len(&priv->sg) = len; 441 sg_dma_address(&priv->sg) = dma_addr; 442 443 priv->dma_direction = dir; 444 445 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 446 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 447 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 448 if (!txdesc) { 449 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 450 rcar_i2c_cleanup_dma(priv); 451 return; 452 } 453 454 txdesc->callback = rcar_i2c_dma_callback; 455 txdesc->callback_param = priv; 456 457 cookie = dmaengine_submit(txdesc); 458 if (dma_submit_error(cookie)) { 459 dev_dbg(dev, "submitting dma failed, using PIO\n"); 460 rcar_i2c_cleanup_dma(priv); 461 return; 462 } 463 464 /* Enable DMA Master Received/Transmitted */ 465 if (read) 466 rcar_i2c_write(priv, ICDMAER, RMDMAE); 467 else 468 rcar_i2c_write(priv, ICDMAER, TMDMAE); 469 470 dma_async_issue_pending(chan); 471 } 472 473 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 474 { 475 struct i2c_msg *msg = priv->msg; 476 477 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 478 if (!(msr & MDE)) 479 return; 480 481 if (priv->pos < msg->len) { 482 /* 483 * Prepare next data to ICRXTX register. 484 * This data will go to _SHIFT_ register. 485 * 486 * * 487 * [ICRXTX] -> [SHIFT] -> [I2C bus] 488 */ 489 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 490 priv->pos++; 491 492 /* 493 * Try to use DMA to transmit the rest of the data if 494 * address transfer phase just finished. 495 */ 496 if (msr & MAT) 497 rcar_i2c_dma(priv); 498 } else { 499 /* 500 * The last data was pushed to ICRXTX on _PREV_ empty irq. 501 * It is on _SHIFT_ register, and will sent to I2C bus. 502 * 503 * * 504 * [ICRXTX] -> [SHIFT] -> [I2C bus] 505 */ 506 507 if (priv->flags & ID_LAST_MSG) { 508 /* 509 * If current msg is the _LAST_ msg, 510 * prepare stop condition here. 511 * ID_DONE will be set on STOP irq. 512 */ 513 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 514 } else { 515 rcar_i2c_next_msg(priv); 516 return; 517 } 518 } 519 520 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 521 } 522 523 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 524 { 525 struct i2c_msg *msg = priv->msg; 526 527 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 528 if (!(msr & MDR)) 529 return; 530 531 if (msr & MAT) { 532 /* 533 * Address transfer phase finished, but no data at this point. 534 * Try to use DMA to receive data. 535 */ 536 rcar_i2c_dma(priv); 537 } else if (priv->pos < msg->len) { 538 /* get received data */ 539 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 540 priv->pos++; 541 } 542 543 /* If next received data is the _LAST_, go to new phase. */ 544 if (priv->pos + 1 == msg->len) { 545 if (priv->flags & ID_LAST_MSG) { 546 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 547 } else { 548 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 549 priv->flags |= ID_P_REP_AFTER_RD; 550 } 551 } 552 553 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 554 rcar_i2c_next_msg(priv); 555 else 556 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 557 } 558 559 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 560 { 561 u32 ssr_raw, ssr_filtered; 562 u8 value; 563 564 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 565 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 566 567 if (!ssr_filtered) 568 return false; 569 570 /* address detected */ 571 if (ssr_filtered & SAR) { 572 /* read or write request */ 573 if (ssr_raw & STM) { 574 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 575 rcar_i2c_write(priv, ICRXTX, value); 576 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 577 } else { 578 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 579 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 580 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 581 } 582 583 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); 584 } 585 586 /* master sent stop */ 587 if (ssr_filtered & SSR) { 588 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 589 rcar_i2c_write(priv, ICSIER, SAR | SSR); 590 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 591 } 592 593 /* master wants to write to us */ 594 if (ssr_filtered & SDR) { 595 int ret; 596 597 value = rcar_i2c_read(priv, ICRXTX); 598 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 599 /* Send NACK in case of error */ 600 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 601 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 602 } 603 604 /* master wants to read from us */ 605 if (ssr_filtered & SDE) { 606 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 607 rcar_i2c_write(priv, ICRXTX, value); 608 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 609 } 610 611 return true; 612 } 613 614 /* 615 * This driver has a lock-free design because there are IP cores (at least 616 * R-Car Gen2) which have an inherent race condition in their hardware design. 617 * There, we need to clear RCAR_BUS_MASK_DATA bits as soon as possible after 618 * the interrupt was generated, otherwise an unwanted repeated message gets 619 * generated. It turned out that taking a spinlock at the beginning of the ISR 620 * was already causing repeated messages. Thus, this driver was converted to 621 * the now lockless behaviour. Please keep this in mind when hacking the driver. 622 */ 623 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 624 { 625 struct rcar_i2c_priv *priv = ptr; 626 u32 msr, val; 627 628 /* Clear START or STOP immediately, except for REPSTART after read */ 629 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) { 630 val = rcar_i2c_read(priv, ICMCR); 631 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); 632 } 633 634 msr = rcar_i2c_read(priv, ICMSR); 635 636 /* Only handle interrupts that are currently enabled */ 637 msr &= rcar_i2c_read(priv, ICMIER); 638 if (!msr) { 639 if (rcar_i2c_slave_irq(priv)) 640 return IRQ_HANDLED; 641 642 return IRQ_NONE; 643 } 644 645 /* Arbitration lost */ 646 if (msr & MAL) { 647 priv->flags |= ID_DONE | ID_ARBLOST; 648 goto out; 649 } 650 651 /* Nack */ 652 if (msr & MNR) { 653 /* HW automatically sends STOP after received NACK */ 654 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 655 priv->flags |= ID_NACK; 656 goto out; 657 } 658 659 /* Stop */ 660 if (msr & MST) { 661 priv->msgs_left--; /* The last message also made it */ 662 priv->flags |= ID_DONE; 663 goto out; 664 } 665 666 if (rcar_i2c_is_recv(priv)) 667 rcar_i2c_irq_recv(priv, msr); 668 else 669 rcar_i2c_irq_send(priv, msr); 670 671 out: 672 if (priv->flags & ID_DONE) { 673 rcar_i2c_write(priv, ICMIER, 0); 674 rcar_i2c_write(priv, ICMSR, 0); 675 wake_up(&priv->wait); 676 } 677 678 return IRQ_HANDLED; 679 } 680 681 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 682 enum dma_transfer_direction dir, 683 dma_addr_t port_addr) 684 { 685 struct dma_chan *chan; 686 struct dma_slave_config cfg; 687 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 688 int ret; 689 690 chan = dma_request_chan(dev, chan_name); 691 if (IS_ERR(chan)) { 692 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 693 chan_name, PTR_ERR(chan)); 694 return chan; 695 } 696 697 memset(&cfg, 0, sizeof(cfg)); 698 cfg.direction = dir; 699 if (dir == DMA_MEM_TO_DEV) { 700 cfg.dst_addr = port_addr; 701 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 702 } else { 703 cfg.src_addr = port_addr; 704 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 705 } 706 707 ret = dmaengine_slave_config(chan, &cfg); 708 if (ret) { 709 dev_dbg(dev, "slave_config failed for %s (%d)\n", 710 chan_name, ret); 711 dma_release_channel(chan); 712 return ERR_PTR(ret); 713 } 714 715 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 716 return chan; 717 } 718 719 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 720 struct i2c_msg *msg) 721 { 722 struct device *dev = rcar_i2c_priv_to_dev(priv); 723 bool read; 724 struct dma_chan *chan; 725 enum dma_transfer_direction dir; 726 727 read = msg->flags & I2C_M_RD; 728 729 chan = read ? priv->dma_rx : priv->dma_tx; 730 if (PTR_ERR(chan) != -EPROBE_DEFER) 731 return; 732 733 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 734 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 735 736 if (read) 737 priv->dma_rx = chan; 738 else 739 priv->dma_tx = chan; 740 } 741 742 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 743 { 744 if (!IS_ERR(priv->dma_tx)) { 745 dma_release_channel(priv->dma_tx); 746 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 747 } 748 749 if (!IS_ERR(priv->dma_rx)) { 750 dma_release_channel(priv->dma_rx); 751 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 752 } 753 } 754 755 /* I2C is a special case, we need to poll the status of a reset */ 756 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 757 { 758 int i, ret; 759 760 ret = reset_control_reset(priv->rstc); 761 if (ret) 762 return ret; 763 764 for (i = 0; i < LOOP_TIMEOUT; i++) { 765 ret = reset_control_status(priv->rstc); 766 if (ret == 0) 767 return 0; 768 udelay(1); 769 } 770 771 return -ETIMEDOUT; 772 } 773 774 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 775 struct i2c_msg *msgs, 776 int num) 777 { 778 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 779 struct device *dev = rcar_i2c_priv_to_dev(priv); 780 int i, ret; 781 long time_left; 782 783 pm_runtime_get_sync(dev); 784 785 /* Check bus state before init otherwise bus busy info will be lost */ 786 ret = rcar_i2c_bus_barrier(priv); 787 if (ret < 0) 788 goto out; 789 790 /* Gen3 needs a reset before allowing RXDMA once */ 791 if (priv->devtype == I2C_RCAR_GEN3) { 792 priv->flags |= ID_P_NO_RXDMA; 793 if (!IS_ERR(priv->rstc)) { 794 ret = rcar_i2c_do_reset(priv); 795 if (ret == 0) 796 priv->flags &= ~ID_P_NO_RXDMA; 797 } 798 } 799 800 rcar_i2c_init(priv); 801 802 for (i = 0; i < num; i++) 803 rcar_i2c_request_dma(priv, msgs + i); 804 805 /* init first message */ 806 priv->msg = msgs; 807 priv->msgs_left = num; 808 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 809 rcar_i2c_prepare_msg(priv); 810 811 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 812 num * adap->timeout); 813 814 /* cleanup DMA if it couldn't complete properly due to an error */ 815 if (priv->dma_direction != DMA_NONE) 816 rcar_i2c_cleanup_dma(priv); 817 818 if (!time_left) { 819 rcar_i2c_init(priv); 820 ret = -ETIMEDOUT; 821 } else if (priv->flags & ID_NACK) { 822 ret = -ENXIO; 823 } else if (priv->flags & ID_ARBLOST) { 824 ret = -EAGAIN; 825 } else { 826 ret = num - priv->msgs_left; /* The number of transfer */ 827 } 828 out: 829 pm_runtime_put(dev); 830 831 if (ret < 0 && ret != -ENXIO) 832 dev_err(dev, "error %d : %x\n", ret, priv->flags); 833 834 return ret; 835 } 836 837 static int rcar_reg_slave(struct i2c_client *slave) 838 { 839 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 840 841 if (priv->slave) 842 return -EBUSY; 843 844 if (slave->flags & I2C_CLIENT_TEN) 845 return -EAFNOSUPPORT; 846 847 /* Keep device active for slave address detection logic */ 848 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 849 850 priv->slave = slave; 851 rcar_i2c_write(priv, ICSAR, slave->addr); 852 rcar_i2c_write(priv, ICSSR, 0); 853 rcar_i2c_write(priv, ICSIER, SAR | SSR); 854 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 855 856 return 0; 857 } 858 859 static int rcar_unreg_slave(struct i2c_client *slave) 860 { 861 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 862 863 WARN_ON(!priv->slave); 864 865 rcar_i2c_write(priv, ICSIER, 0); 866 rcar_i2c_write(priv, ICSCR, 0); 867 868 priv->slave = NULL; 869 870 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 871 872 return 0; 873 } 874 875 static u32 rcar_i2c_func(struct i2c_adapter *adap) 876 { 877 /* 878 * This HW can't do: 879 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 880 * I2C_M_NOSTART (automatically sends address after START) 881 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 882 */ 883 return I2C_FUNC_I2C | I2C_FUNC_SLAVE | 884 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 885 } 886 887 static const struct i2c_algorithm rcar_i2c_algo = { 888 .master_xfer = rcar_i2c_master_xfer, 889 .functionality = rcar_i2c_func, 890 .reg_slave = rcar_reg_slave, 891 .unreg_slave = rcar_unreg_slave, 892 }; 893 894 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 895 .flags = I2C_AQ_NO_ZERO_LEN, 896 }; 897 898 static const struct of_device_id rcar_i2c_dt_ids[] = { 899 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 900 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 901 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 902 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 903 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 904 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 905 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 906 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 907 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 908 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 909 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 910 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 911 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 912 {}, 913 }; 914 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 915 916 static int rcar_i2c_probe(struct platform_device *pdev) 917 { 918 struct rcar_i2c_priv *priv; 919 struct i2c_adapter *adap; 920 struct device *dev = &pdev->dev; 921 struct i2c_timings i2c_t; 922 int irq, ret; 923 924 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 925 if (!priv) 926 return -ENOMEM; 927 928 priv->clk = devm_clk_get(dev, NULL); 929 if (IS_ERR(priv->clk)) { 930 dev_err(dev, "cannot get clock\n"); 931 return PTR_ERR(priv->clk); 932 } 933 934 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 935 936 priv->io = devm_ioremap_resource(dev, priv->res); 937 if (IS_ERR(priv->io)) 938 return PTR_ERR(priv->io); 939 940 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 941 init_waitqueue_head(&priv->wait); 942 943 adap = &priv->adap; 944 adap->nr = pdev->id; 945 adap->algo = &rcar_i2c_algo; 946 adap->class = I2C_CLASS_DEPRECATED; 947 adap->retries = 3; 948 adap->dev.parent = dev; 949 adap->dev.of_node = dev->of_node; 950 adap->bus_recovery_info = &rcar_i2c_bri; 951 adap->quirks = &rcar_i2c_quirks; 952 i2c_set_adapdata(adap, priv); 953 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 954 955 i2c_parse_fw_timings(dev, &i2c_t, false); 956 957 /* Init DMA */ 958 sg_init_table(&priv->sg, 1); 959 priv->dma_direction = DMA_NONE; 960 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 961 962 /* Activate device for clock calculation */ 963 pm_runtime_enable(dev); 964 pm_runtime_get_sync(dev); 965 ret = rcar_i2c_clock_calculate(priv, &i2c_t); 966 if (ret < 0) 967 goto out_pm_put; 968 969 if (priv->devtype == I2C_RCAR_GEN3) { 970 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 971 if (!IS_ERR(priv->rstc)) { 972 ret = reset_control_status(priv->rstc); 973 if (ret < 0) 974 priv->rstc = ERR_PTR(-ENOTSUPP); 975 } 976 } 977 978 /* Stay always active when multi-master to keep arbitration working */ 979 if (of_property_read_bool(dev->of_node, "multi-master")) 980 priv->flags |= ID_P_PM_BLOCKED; 981 else 982 pm_runtime_put(dev); 983 984 985 irq = platform_get_irq(pdev, 0); 986 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); 987 if (ret < 0) { 988 dev_err(dev, "cannot get irq %d\n", irq); 989 goto out_pm_disable; 990 } 991 992 platform_set_drvdata(pdev, priv); 993 994 ret = i2c_add_numbered_adapter(adap); 995 if (ret < 0) 996 goto out_pm_disable; 997 998 dev_info(dev, "probed\n"); 999 1000 return 0; 1001 1002 out_pm_put: 1003 pm_runtime_put(dev); 1004 out_pm_disable: 1005 pm_runtime_disable(dev); 1006 return ret; 1007 } 1008 1009 static int rcar_i2c_remove(struct platform_device *pdev) 1010 { 1011 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1012 struct device *dev = &pdev->dev; 1013 1014 i2c_del_adapter(&priv->adap); 1015 rcar_i2c_release_dma(priv); 1016 if (priv->flags & ID_P_PM_BLOCKED) 1017 pm_runtime_put(dev); 1018 pm_runtime_disable(dev); 1019 1020 return 0; 1021 } 1022 1023 #ifdef CONFIG_PM_SLEEP 1024 static int rcar_i2c_suspend(struct device *dev) 1025 { 1026 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1027 1028 i2c_mark_adapter_suspended(&priv->adap); 1029 return 0; 1030 } 1031 1032 static int rcar_i2c_resume(struct device *dev) 1033 { 1034 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1035 1036 i2c_mark_adapter_resumed(&priv->adap); 1037 return 0; 1038 } 1039 1040 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1041 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1042 }; 1043 1044 #define DEV_PM_OPS (&rcar_i2c_pm_ops) 1045 #else 1046 #define DEV_PM_OPS NULL 1047 #endif /* CONFIG_PM_SLEEP */ 1048 1049 static struct platform_driver rcar_i2c_driver = { 1050 .driver = { 1051 .name = "i2c-rcar", 1052 .of_match_table = rcar_i2c_dt_ids, 1053 .pm = DEV_PM_OPS, 1054 }, 1055 .probe = rcar_i2c_probe, 1056 .remove = rcar_i2c_remove, 1057 }; 1058 1059 module_platform_driver(rcar_i2c_driver); 1060 1061 MODULE_LICENSE("GPL v2"); 1062 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1063 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1064