1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 45 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 46 47 /* ICSCR */ 48 #define SDBS (1 << 3) /* slave data buffer select */ 49 #define SIE (1 << 2) /* slave interface enable */ 50 #define GCAE (1 << 1) /* general call address enable */ 51 #define FNA (1 << 0) /* forced non acknowledgment */ 52 53 /* ICMCR */ 54 #define MDBS (1 << 7) /* non-fifo mode switch */ 55 #define FSCL (1 << 6) /* override SCL pin */ 56 #define FSDA (1 << 5) /* override SDA pin */ 57 #define OBPC (1 << 4) /* override pins */ 58 #define MIE (1 << 3) /* master if enable */ 59 #define TSBE (1 << 2) 60 #define FSB (1 << 1) /* force stop bit */ 61 #define ESG (1 << 0) /* enable start bit gen */ 62 63 /* ICSSR (also for ICSIER) */ 64 #define GCAR (1 << 6) /* general call received */ 65 #define STM (1 << 5) /* slave transmit mode */ 66 #define SSR (1 << 4) /* stop received */ 67 #define SDE (1 << 3) /* slave data empty */ 68 #define SDT (1 << 2) /* slave data transmitted */ 69 #define SDR (1 << 1) /* slave data received */ 70 #define SAR (1 << 0) /* slave addr received */ 71 72 /* ICMSR (also for ICMIE) */ 73 #define MNR (1 << 6) /* nack received */ 74 #define MAL (1 << 5) /* arbitration lost */ 75 #define MST (1 << 4) /* sent a stop */ 76 #define MDE (1 << 3) 77 #define MDT (1 << 2) 78 #define MDR (1 << 1) 79 #define MAT (1 << 0) /* slave addr xfer done */ 80 81 /* ICDMAER */ 82 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 83 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 84 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 85 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 86 87 /* ICFBSCR */ 88 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 89 90 #define RCAR_MIN_DMA_LEN 8 91 92 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 93 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 94 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 95 96 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 97 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 98 #define RCAR_IRQ_STOP (MST) 99 100 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 101 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 102 103 #define ID_LAST_MSG (1 << 0) 104 #define ID_FIRST_MSG (1 << 1) 105 #define ID_DONE (1 << 2) 106 #define ID_ARBLOST (1 << 3) 107 #define ID_NACK (1 << 4) 108 /* persistent flags */ 109 #define ID_P_HOST_NOTIFY BIT(28) 110 #define ID_P_REP_AFTER_RD BIT(29) 111 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 112 #define ID_P_PM_BLOCKED BIT(31) 113 #define ID_P_MASK GENMASK(31, 28) 114 115 enum rcar_i2c_type { 116 I2C_RCAR_GEN1, 117 I2C_RCAR_GEN2, 118 I2C_RCAR_GEN3, 119 }; 120 121 struct rcar_i2c_priv { 122 u32 flags; 123 void __iomem *io; 124 struct i2c_adapter adap; 125 struct i2c_msg *msg; 126 int msgs_left; 127 struct clk *clk; 128 129 wait_queue_head_t wait; 130 131 int pos; 132 u32 icccr; 133 u8 recovery_icmcr; /* protected by adapter lock */ 134 enum rcar_i2c_type devtype; 135 struct i2c_client *slave; 136 137 struct resource *res; 138 struct dma_chan *dma_tx; 139 struct dma_chan *dma_rx; 140 struct scatterlist sg; 141 enum dma_data_direction dma_direction; 142 143 struct reset_control *rstc; 144 int irq; 145 146 struct i2c_client *host_notify_client; 147 }; 148 149 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 150 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 151 152 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 153 { 154 writel(val, priv->io + reg); 155 } 156 157 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 158 { 159 return readl(priv->io + reg); 160 } 161 162 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 163 { 164 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 165 166 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 167 168 }; 169 170 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 171 { 172 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 173 174 if (val) 175 priv->recovery_icmcr |= FSCL; 176 else 177 priv->recovery_icmcr &= ~FSCL; 178 179 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 180 }; 181 182 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 183 { 184 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 185 186 if (val) 187 priv->recovery_icmcr |= FSDA; 188 else 189 priv->recovery_icmcr &= ~FSDA; 190 191 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 192 }; 193 194 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 195 { 196 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 197 198 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 199 200 }; 201 202 static struct i2c_bus_recovery_info rcar_i2c_bri = { 203 .get_scl = rcar_i2c_get_scl, 204 .set_scl = rcar_i2c_set_scl, 205 .set_sda = rcar_i2c_set_sda, 206 .get_bus_free = rcar_i2c_get_bus_free, 207 .recover_bus = i2c_generic_scl_recovery, 208 }; 209 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 210 { 211 /* reset master mode */ 212 rcar_i2c_write(priv, ICMIER, 0); 213 rcar_i2c_write(priv, ICMCR, MDBS); 214 rcar_i2c_write(priv, ICMSR, 0); 215 /* start clock */ 216 rcar_i2c_write(priv, ICCCR, priv->icccr); 217 218 if (priv->devtype == I2C_RCAR_GEN3) 219 rcar_i2c_write(priv, ICFBSCR, TCYC17); 220 221 } 222 223 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 224 { 225 int ret; 226 u32 val; 227 228 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 229 priv->adap.timeout); 230 if (ret) { 231 /* Waiting did not help, try to recover */ 232 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 233 ret = i2c_recover_bus(&priv->adap); 234 } 235 236 return ret; 237 } 238 239 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 240 { 241 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 242 unsigned long rate; 243 struct device *dev = rcar_i2c_priv_to_dev(priv); 244 struct i2c_timings t = { 245 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 246 .scl_fall_ns = 35, 247 .scl_rise_ns = 200, 248 .scl_int_delay_ns = 50, 249 }; 250 251 /* Fall back to previously used values if not supplied */ 252 i2c_parse_fw_timings(dev, &t, false); 253 254 switch (priv->devtype) { 255 case I2C_RCAR_GEN1: 256 cdf_width = 2; 257 break; 258 case I2C_RCAR_GEN2: 259 case I2C_RCAR_GEN3: 260 cdf_width = 3; 261 break; 262 default: 263 dev_err(dev, "device type error\n"); 264 return -EIO; 265 } 266 267 /* 268 * calculate SCL clock 269 * see 270 * ICCCR 271 * 272 * ick = clkp / (1 + CDF) 273 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 274 * 275 * ick : I2C internal clock < 20 MHz 276 * ticf : I2C SCL falling time 277 * tr : I2C SCL rising time 278 * intd : LSI internal delay 279 * clkp : peripheral_clk 280 * F[] : integer up-valuation 281 */ 282 rate = clk_get_rate(priv->clk); 283 cdf = rate / 20000000; 284 if (cdf >= 1U << cdf_width) { 285 dev_err(dev, "Input clock %lu too high\n", rate); 286 return -EIO; 287 } 288 ick = rate / (cdf + 1); 289 290 /* 291 * it is impossible to calculate large scale 292 * number on u32. separate it 293 * 294 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 295 * = F[sum * ick / 1000000000] 296 * = F[(ick / 1000000) * sum / 1000] 297 */ 298 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 299 round = (ick + 500000) / 1000000 * sum; 300 round = (round + 500) / 1000; 301 302 /* 303 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 304 * 305 * Calculation result (= SCL) should be less than 306 * bus_speed for hardware safety 307 * 308 * We could use something along the lines of 309 * div = ick / (bus_speed + 1) + 1; 310 * scgd = (div - 20 - round + 7) / 8; 311 * scl = ick / (20 + (scgd * 8) + round); 312 * (not fully verified) but that would get pretty involved 313 */ 314 for (scgd = 0; scgd < 0x40; scgd++) { 315 scl = ick / (20 + (scgd * 8) + round); 316 if (scl <= t.bus_freq_hz) 317 goto scgd_find; 318 } 319 dev_err(dev, "it is impossible to calculate best SCL\n"); 320 return -EIO; 321 322 scgd_find: 323 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 324 scl, t.bus_freq_hz, rate, round, cdf, scgd); 325 326 /* keep icccr value */ 327 priv->icccr = scgd << cdf_width | cdf; 328 329 return 0; 330 } 331 332 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 333 { 334 int read = !!rcar_i2c_is_recv(priv); 335 336 priv->pos = 0; 337 if (priv->msgs_left == 1) 338 priv->flags |= ID_LAST_MSG; 339 340 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 341 /* 342 * We don't have a test case but the HW engineers say that the write order 343 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 344 * it didn't cause a drawback for me, let's rather be safe than sorry. 345 */ 346 if (priv->flags & ID_FIRST_MSG) { 347 rcar_i2c_write(priv, ICMSR, 0); 348 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 349 } else { 350 if (priv->flags & ID_P_REP_AFTER_RD) 351 priv->flags &= ~ID_P_REP_AFTER_RD; 352 else 353 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 354 rcar_i2c_write(priv, ICMSR, 0); 355 } 356 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 357 } 358 359 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 360 { 361 priv->msg++; 362 priv->msgs_left--; 363 priv->flags &= ID_P_MASK; 364 rcar_i2c_prepare_msg(priv); 365 } 366 367 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 368 { 369 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 370 ? priv->dma_rx : priv->dma_tx; 371 372 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 373 sg_dma_len(&priv->sg), priv->dma_direction); 374 375 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 376 if (priv->devtype == I2C_RCAR_GEN3 && 377 priv->dma_direction == DMA_FROM_DEVICE) 378 priv->flags |= ID_P_NO_RXDMA; 379 380 priv->dma_direction = DMA_NONE; 381 382 /* Disable DMA Master Received/Transmitted, must be last! */ 383 rcar_i2c_write(priv, ICDMAER, 0); 384 } 385 386 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 387 { 388 if (priv->dma_direction == DMA_NONE) 389 return; 390 else if (priv->dma_direction == DMA_FROM_DEVICE) 391 dmaengine_terminate_all(priv->dma_rx); 392 else if (priv->dma_direction == DMA_TO_DEVICE) 393 dmaengine_terminate_all(priv->dma_tx); 394 395 rcar_i2c_dma_unmap(priv); 396 } 397 398 static void rcar_i2c_dma_callback(void *data) 399 { 400 struct rcar_i2c_priv *priv = data; 401 402 priv->pos += sg_dma_len(&priv->sg); 403 404 rcar_i2c_dma_unmap(priv); 405 } 406 407 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 408 { 409 struct device *dev = rcar_i2c_priv_to_dev(priv); 410 struct i2c_msg *msg = priv->msg; 411 bool read = msg->flags & I2C_M_RD; 412 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 413 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 414 struct dma_async_tx_descriptor *txdesc; 415 dma_addr_t dma_addr; 416 dma_cookie_t cookie; 417 unsigned char *buf; 418 int len; 419 420 /* Do various checks to see if DMA is feasible at all */ 421 if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 422 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 423 return false; 424 425 if (read) { 426 /* 427 * The last two bytes needs to be fetched using PIO in 428 * order for the STOP phase to work. 429 */ 430 buf = priv->msg->buf; 431 len = priv->msg->len - 2; 432 } else { 433 /* 434 * First byte in message was sent using PIO. 435 */ 436 buf = priv->msg->buf + 1; 437 len = priv->msg->len - 1; 438 } 439 440 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 441 if (dma_mapping_error(chan->device->dev, dma_addr)) { 442 dev_dbg(dev, "dma map failed, using PIO\n"); 443 return false; 444 } 445 446 sg_dma_len(&priv->sg) = len; 447 sg_dma_address(&priv->sg) = dma_addr; 448 449 priv->dma_direction = dir; 450 451 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 452 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 454 if (!txdesc) { 455 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 456 rcar_i2c_cleanup_dma(priv); 457 return false; 458 } 459 460 txdesc->callback = rcar_i2c_dma_callback; 461 txdesc->callback_param = priv; 462 463 cookie = dmaengine_submit(txdesc); 464 if (dma_submit_error(cookie)) { 465 dev_dbg(dev, "submitting dma failed, using PIO\n"); 466 rcar_i2c_cleanup_dma(priv); 467 return false; 468 } 469 470 /* Enable DMA Master Received/Transmitted */ 471 if (read) 472 rcar_i2c_write(priv, ICDMAER, RMDMAE); 473 else 474 rcar_i2c_write(priv, ICDMAER, TMDMAE); 475 476 dma_async_issue_pending(chan); 477 return true; 478 } 479 480 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 481 { 482 struct i2c_msg *msg = priv->msg; 483 484 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 485 if (!(msr & MDE)) 486 return; 487 488 /* Check if DMA can be enabled and take over */ 489 if (priv->pos == 1 && rcar_i2c_dma(priv)) 490 return; 491 492 if (priv->pos < msg->len) { 493 /* 494 * Prepare next data to ICRXTX register. 495 * This data will go to _SHIFT_ register. 496 * 497 * * 498 * [ICRXTX] -> [SHIFT] -> [I2C bus] 499 */ 500 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 501 priv->pos++; 502 } else { 503 /* 504 * The last data was pushed to ICRXTX on _PREV_ empty irq. 505 * It is on _SHIFT_ register, and will sent to I2C bus. 506 * 507 * * 508 * [ICRXTX] -> [SHIFT] -> [I2C bus] 509 */ 510 511 if (priv->flags & ID_LAST_MSG) { 512 /* 513 * If current msg is the _LAST_ msg, 514 * prepare stop condition here. 515 * ID_DONE will be set on STOP irq. 516 */ 517 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 518 } else { 519 rcar_i2c_next_msg(priv); 520 return; 521 } 522 } 523 524 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 525 } 526 527 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 528 { 529 struct i2c_msg *msg = priv->msg; 530 531 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 532 if (!(msr & MDR)) 533 return; 534 535 if (msr & MAT) { 536 /* 537 * Address transfer phase finished, but no data at this point. 538 * Try to use DMA to receive data. 539 */ 540 rcar_i2c_dma(priv); 541 } else if (priv->pos < msg->len) { 542 /* get received data */ 543 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 544 priv->pos++; 545 } 546 547 /* If next received data is the _LAST_, go to new phase. */ 548 if (priv->pos + 1 == msg->len) { 549 if (priv->flags & ID_LAST_MSG) { 550 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 551 } else { 552 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 553 priv->flags |= ID_P_REP_AFTER_RD; 554 } 555 } 556 557 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 558 rcar_i2c_next_msg(priv); 559 else 560 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 561 } 562 563 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 564 { 565 u32 ssr_raw, ssr_filtered; 566 u8 value; 567 568 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 569 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 570 571 if (!ssr_filtered) 572 return false; 573 574 /* address detected */ 575 if (ssr_filtered & SAR) { 576 /* read or write request */ 577 if (ssr_raw & STM) { 578 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 579 rcar_i2c_write(priv, ICRXTX, value); 580 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 581 } else { 582 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 583 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 584 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 585 } 586 587 /* Clear SSR, too, because of old STOPs to other clients than us */ 588 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 589 } 590 591 /* master sent stop */ 592 if (ssr_filtered & SSR) { 593 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 594 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 595 rcar_i2c_write(priv, ICSIER, SAR); 596 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 597 } 598 599 /* master wants to write to us */ 600 if (ssr_filtered & SDR) { 601 int ret; 602 603 value = rcar_i2c_read(priv, ICRXTX); 604 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 605 /* Send NACK in case of error */ 606 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 607 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 608 } 609 610 /* master wants to read from us */ 611 if (ssr_filtered & SDE) { 612 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 613 rcar_i2c_write(priv, ICRXTX, value); 614 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 615 } 616 617 return true; 618 } 619 620 /* 621 * This driver has a lock-free design because there are IP cores (at least 622 * R-Car Gen2) which have an inherent race condition in their hardware design. 623 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after 624 * the interrupt was generated, otherwise an unwanted repeated message gets 625 * generated. It turned out that taking a spinlock at the beginning of the ISR 626 * was already causing repeated messages. Thus, this driver was converted to 627 * the now lockless behaviour. Please keep this in mind when hacking the driver. 628 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are 629 * likely affected. Therefore, we have different interrupt handler entries. 630 */ 631 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr) 632 { 633 if (!msr) { 634 if (rcar_i2c_slave_irq(priv)) 635 return IRQ_HANDLED; 636 637 return IRQ_NONE; 638 } 639 640 /* Arbitration lost */ 641 if (msr & MAL) { 642 priv->flags |= ID_DONE | ID_ARBLOST; 643 goto out; 644 } 645 646 /* Nack */ 647 if (msr & MNR) { 648 /* HW automatically sends STOP after received NACK */ 649 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 650 priv->flags |= ID_NACK; 651 goto out; 652 } 653 654 /* Stop */ 655 if (msr & MST) { 656 priv->msgs_left--; /* The last message also made it */ 657 priv->flags |= ID_DONE; 658 goto out; 659 } 660 661 if (rcar_i2c_is_recv(priv)) 662 rcar_i2c_irq_recv(priv, msr); 663 else 664 rcar_i2c_irq_send(priv, msr); 665 666 out: 667 if (priv->flags & ID_DONE) { 668 rcar_i2c_write(priv, ICMIER, 0); 669 rcar_i2c_write(priv, ICMSR, 0); 670 wake_up(&priv->wait); 671 } 672 673 return IRQ_HANDLED; 674 } 675 676 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr) 677 { 678 struct rcar_i2c_priv *priv = ptr; 679 u32 msr; 680 681 /* Clear START or STOP immediately, except for REPSTART after read */ 682 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) 683 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 684 685 /* Only handle interrupts that are currently enabled */ 686 msr = rcar_i2c_read(priv, ICMSR); 687 msr &= rcar_i2c_read(priv, ICMIER); 688 689 return rcar_i2c_irq(irq, priv, msr); 690 } 691 692 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr) 693 { 694 struct rcar_i2c_priv *priv = ptr; 695 u32 msr; 696 697 /* Only handle interrupts that are currently enabled */ 698 msr = rcar_i2c_read(priv, ICMSR); 699 msr &= rcar_i2c_read(priv, ICMIER); 700 701 /* 702 * Clear START or STOP immediately, except for REPSTART after read or 703 * if a spurious interrupt was detected. 704 */ 705 if (likely(!(priv->flags & ID_P_REP_AFTER_RD) && msr)) 706 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 707 708 return rcar_i2c_irq(irq, priv, msr); 709 } 710 711 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 712 enum dma_transfer_direction dir, 713 dma_addr_t port_addr) 714 { 715 struct dma_chan *chan; 716 struct dma_slave_config cfg; 717 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 718 int ret; 719 720 chan = dma_request_chan(dev, chan_name); 721 if (IS_ERR(chan)) { 722 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 723 chan_name, PTR_ERR(chan)); 724 return chan; 725 } 726 727 memset(&cfg, 0, sizeof(cfg)); 728 cfg.direction = dir; 729 if (dir == DMA_MEM_TO_DEV) { 730 cfg.dst_addr = port_addr; 731 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 732 } else { 733 cfg.src_addr = port_addr; 734 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 735 } 736 737 ret = dmaengine_slave_config(chan, &cfg); 738 if (ret) { 739 dev_dbg(dev, "slave_config failed for %s (%d)\n", 740 chan_name, ret); 741 dma_release_channel(chan); 742 return ERR_PTR(ret); 743 } 744 745 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 746 return chan; 747 } 748 749 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 750 struct i2c_msg *msg) 751 { 752 struct device *dev = rcar_i2c_priv_to_dev(priv); 753 bool read; 754 struct dma_chan *chan; 755 enum dma_transfer_direction dir; 756 757 read = msg->flags & I2C_M_RD; 758 759 chan = read ? priv->dma_rx : priv->dma_tx; 760 if (PTR_ERR(chan) != -EPROBE_DEFER) 761 return; 762 763 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 764 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 765 766 if (read) 767 priv->dma_rx = chan; 768 else 769 priv->dma_tx = chan; 770 } 771 772 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 773 { 774 if (!IS_ERR(priv->dma_tx)) { 775 dma_release_channel(priv->dma_tx); 776 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 777 } 778 779 if (!IS_ERR(priv->dma_rx)) { 780 dma_release_channel(priv->dma_rx); 781 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 782 } 783 } 784 785 /* I2C is a special case, we need to poll the status of a reset */ 786 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 787 { 788 int ret; 789 790 ret = reset_control_reset(priv->rstc); 791 if (ret) 792 return ret; 793 794 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1, 795 100, false, priv->rstc); 796 } 797 798 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 799 struct i2c_msg *msgs, 800 int num) 801 { 802 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 803 struct device *dev = rcar_i2c_priv_to_dev(priv); 804 int i, ret; 805 long time_left; 806 807 pm_runtime_get_sync(dev); 808 809 /* Check bus state before init otherwise bus busy info will be lost */ 810 ret = rcar_i2c_bus_barrier(priv); 811 if (ret < 0) 812 goto out; 813 814 /* Gen3 needs a reset before allowing RXDMA once */ 815 if (priv->devtype == I2C_RCAR_GEN3) { 816 priv->flags |= ID_P_NO_RXDMA; 817 if (!IS_ERR(priv->rstc)) { 818 ret = rcar_i2c_do_reset(priv); 819 if (ret == 0) 820 priv->flags &= ~ID_P_NO_RXDMA; 821 } 822 } 823 824 rcar_i2c_init(priv); 825 826 for (i = 0; i < num; i++) 827 rcar_i2c_request_dma(priv, msgs + i); 828 829 /* init first message */ 830 priv->msg = msgs; 831 priv->msgs_left = num; 832 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 833 rcar_i2c_prepare_msg(priv); 834 835 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 836 num * adap->timeout); 837 838 /* cleanup DMA if it couldn't complete properly due to an error */ 839 if (priv->dma_direction != DMA_NONE) 840 rcar_i2c_cleanup_dma(priv); 841 842 if (!time_left) { 843 rcar_i2c_init(priv); 844 ret = -ETIMEDOUT; 845 } else if (priv->flags & ID_NACK) { 846 ret = -ENXIO; 847 } else if (priv->flags & ID_ARBLOST) { 848 ret = -EAGAIN; 849 } else { 850 ret = num - priv->msgs_left; /* The number of transfer */ 851 } 852 out: 853 pm_runtime_put(dev); 854 855 if (ret < 0 && ret != -ENXIO) 856 dev_err(dev, "error %d : %x\n", ret, priv->flags); 857 858 return ret; 859 } 860 861 static int rcar_reg_slave(struct i2c_client *slave) 862 { 863 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 864 865 if (priv->slave) 866 return -EBUSY; 867 868 if (slave->flags & I2C_CLIENT_TEN) 869 return -EAFNOSUPPORT; 870 871 /* Keep device active for slave address detection logic */ 872 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 873 874 priv->slave = slave; 875 rcar_i2c_write(priv, ICSAR, slave->addr); 876 rcar_i2c_write(priv, ICSSR, 0); 877 rcar_i2c_write(priv, ICSIER, SAR); 878 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 879 880 return 0; 881 } 882 883 static int rcar_unreg_slave(struct i2c_client *slave) 884 { 885 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 886 887 WARN_ON(!priv->slave); 888 889 /* ensure no irq is running before clearing ptr */ 890 disable_irq(priv->irq); 891 rcar_i2c_write(priv, ICSIER, 0); 892 rcar_i2c_write(priv, ICSSR, 0); 893 enable_irq(priv->irq); 894 rcar_i2c_write(priv, ICSCR, SDBS); 895 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 896 897 priv->slave = NULL; 898 899 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 900 901 return 0; 902 } 903 904 static u32 rcar_i2c_func(struct i2c_adapter *adap) 905 { 906 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 907 908 /* 909 * This HW can't do: 910 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 911 * I2C_M_NOSTART (automatically sends address after START) 912 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 913 */ 914 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 915 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 916 917 if (priv->flags & ID_P_HOST_NOTIFY) 918 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 919 920 return func; 921 } 922 923 static const struct i2c_algorithm rcar_i2c_algo = { 924 .master_xfer = rcar_i2c_master_xfer, 925 .functionality = rcar_i2c_func, 926 .reg_slave = rcar_reg_slave, 927 .unreg_slave = rcar_unreg_slave, 928 }; 929 930 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 931 .flags = I2C_AQ_NO_ZERO_LEN, 932 }; 933 934 static const struct of_device_id rcar_i2c_dt_ids[] = { 935 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 936 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 937 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 938 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 939 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 940 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 941 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 942 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 943 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 944 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 945 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 946 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 947 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 948 {}, 949 }; 950 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 951 952 static int rcar_i2c_probe(struct platform_device *pdev) 953 { 954 struct rcar_i2c_priv *priv; 955 struct i2c_adapter *adap; 956 struct device *dev = &pdev->dev; 957 unsigned long irqflags = 0; 958 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq; 959 int ret; 960 961 /* Otherwise logic will break because some bytes must always use PIO */ 962 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 963 964 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 965 if (!priv) 966 return -ENOMEM; 967 968 priv->clk = devm_clk_get(dev, NULL); 969 if (IS_ERR(priv->clk)) { 970 dev_err(dev, "cannot get clock\n"); 971 return PTR_ERR(priv->clk); 972 } 973 974 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 975 if (IS_ERR(priv->io)) 976 return PTR_ERR(priv->io); 977 978 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 979 init_waitqueue_head(&priv->wait); 980 981 adap = &priv->adap; 982 adap->nr = pdev->id; 983 adap->algo = &rcar_i2c_algo; 984 adap->class = I2C_CLASS_DEPRECATED; 985 adap->retries = 3; 986 adap->dev.parent = dev; 987 adap->dev.of_node = dev->of_node; 988 adap->bus_recovery_info = &rcar_i2c_bri; 989 adap->quirks = &rcar_i2c_quirks; 990 i2c_set_adapdata(adap, priv); 991 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 992 993 /* Init DMA */ 994 sg_init_table(&priv->sg, 1); 995 priv->dma_direction = DMA_NONE; 996 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 997 998 /* Activate device for clock calculation */ 999 pm_runtime_enable(dev); 1000 pm_runtime_get_sync(dev); 1001 ret = rcar_i2c_clock_calculate(priv); 1002 if (ret < 0) 1003 goto out_pm_put; 1004 1005 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 1006 1007 if (priv->devtype < I2C_RCAR_GEN3) { 1008 irqflags |= IRQF_NO_THREAD; 1009 irqhandler = rcar_i2c_gen2_irq; 1010 } 1011 1012 if (priv->devtype == I2C_RCAR_GEN3) { 1013 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1014 if (!IS_ERR(priv->rstc)) { 1015 ret = reset_control_status(priv->rstc); 1016 if (ret < 0) 1017 priv->rstc = ERR_PTR(-ENOTSUPP); 1018 } 1019 } 1020 1021 /* Stay always active when multi-master to keep arbitration working */ 1022 if (of_property_read_bool(dev->of_node, "multi-master")) 1023 priv->flags |= ID_P_PM_BLOCKED; 1024 else 1025 pm_runtime_put(dev); 1026 1027 if (of_property_read_bool(dev->of_node, "smbus")) 1028 priv->flags |= ID_P_HOST_NOTIFY; 1029 1030 priv->irq = platform_get_irq(pdev, 0); 1031 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1032 if (ret < 0) { 1033 dev_err(dev, "cannot get irq %d\n", priv->irq); 1034 goto out_pm_disable; 1035 } 1036 1037 platform_set_drvdata(pdev, priv); 1038 1039 ret = i2c_add_numbered_adapter(adap); 1040 if (ret < 0) 1041 goto out_pm_disable; 1042 1043 if (priv->flags & ID_P_HOST_NOTIFY) { 1044 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1045 if (IS_ERR(priv->host_notify_client)) { 1046 ret = PTR_ERR(priv->host_notify_client); 1047 goto out_del_device; 1048 } 1049 } 1050 1051 dev_info(dev, "probed\n"); 1052 1053 return 0; 1054 1055 out_del_device: 1056 i2c_del_adapter(&priv->adap); 1057 out_pm_put: 1058 pm_runtime_put(dev); 1059 out_pm_disable: 1060 pm_runtime_disable(dev); 1061 return ret; 1062 } 1063 1064 static int rcar_i2c_remove(struct platform_device *pdev) 1065 { 1066 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1067 struct device *dev = &pdev->dev; 1068 1069 if (priv->host_notify_client) 1070 i2c_free_slave_host_notify_device(priv->host_notify_client); 1071 i2c_del_adapter(&priv->adap); 1072 rcar_i2c_release_dma(priv); 1073 if (priv->flags & ID_P_PM_BLOCKED) 1074 pm_runtime_put(dev); 1075 pm_runtime_disable(dev); 1076 1077 return 0; 1078 } 1079 1080 #ifdef CONFIG_PM_SLEEP 1081 static int rcar_i2c_suspend(struct device *dev) 1082 { 1083 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1084 1085 i2c_mark_adapter_suspended(&priv->adap); 1086 return 0; 1087 } 1088 1089 static int rcar_i2c_resume(struct device *dev) 1090 { 1091 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1092 1093 i2c_mark_adapter_resumed(&priv->adap); 1094 return 0; 1095 } 1096 1097 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1098 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1099 }; 1100 1101 #define DEV_PM_OPS (&rcar_i2c_pm_ops) 1102 #else 1103 #define DEV_PM_OPS NULL 1104 #endif /* CONFIG_PM_SLEEP */ 1105 1106 static struct platform_driver rcar_i2c_driver = { 1107 .driver = { 1108 .name = "i2c-rcar", 1109 .of_match_table = rcar_i2c_dt_ids, 1110 .pm = DEV_PM_OPS, 1111 }, 1112 .probe = rcar_i2c_probe, 1113 .remove = rcar_i2c_remove, 1114 }; 1115 1116 module_platform_driver(rcar_i2c_driver); 1117 1118 MODULE_LICENSE("GPL v2"); 1119 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1120 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1121