1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2015 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/i2c.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 /* register offsets */ 32 #define ICSCR 0x00 /* slave ctrl */ 33 #define ICMCR 0x04 /* master ctrl */ 34 #define ICSSR 0x08 /* slave status */ 35 #define ICMSR 0x0C /* master status */ 36 #define ICSIER 0x10 /* slave irq enable */ 37 #define ICMIER 0x14 /* master irq enable */ 38 #define ICCCR 0x18 /* clock dividers */ 39 #define ICSAR 0x1C /* slave address */ 40 #define ICMAR 0x20 /* master address */ 41 #define ICRXTX 0x24 /* data port */ 42 #define ICDMAER 0x3c /* DMA enable */ 43 #define ICFBSCR 0x38 /* first bit setup cycle */ 44 45 /* ICSCR */ 46 #define SDBS (1 << 3) /* slave data buffer select */ 47 #define SIE (1 << 2) /* slave interface enable */ 48 #define GCAE (1 << 1) /* general call address enable */ 49 #define FNA (1 << 0) /* forced non acknowledgment */ 50 51 /* ICMCR */ 52 #define MDBS (1 << 7) /* non-fifo mode switch */ 53 #define FSCL (1 << 6) /* override SCL pin */ 54 #define FSDA (1 << 5) /* override SDA pin */ 55 #define OBPC (1 << 4) /* override pins */ 56 #define MIE (1 << 3) /* master if enable */ 57 #define TSBE (1 << 2) 58 #define FSB (1 << 1) /* force stop bit */ 59 #define ESG (1 << 0) /* enable start bit gen */ 60 61 /* ICSSR (also for ICSIER) */ 62 #define GCAR (1 << 6) /* general call received */ 63 #define STM (1 << 5) /* slave transmit mode */ 64 #define SSR (1 << 4) /* stop received */ 65 #define SDE (1 << 3) /* slave data empty */ 66 #define SDT (1 << 2) /* slave data transmitted */ 67 #define SDR (1 << 1) /* slave data received */ 68 #define SAR (1 << 0) /* slave addr received */ 69 70 /* ICMSR (also for ICMIE) */ 71 #define MNR (1 << 6) /* nack received */ 72 #define MAL (1 << 5) /* arbitration lost */ 73 #define MST (1 << 4) /* sent a stop */ 74 #define MDE (1 << 3) 75 #define MDT (1 << 2) 76 #define MDR (1 << 1) 77 #define MAT (1 << 0) /* slave addr xfer done */ 78 79 /* ICDMAER */ 80 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 81 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 82 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 83 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 84 85 /* ICFBSCR */ 86 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */ 87 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 88 89 90 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 91 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 92 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) 93 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 94 95 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 96 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 97 #define RCAR_IRQ_STOP (MST) 98 99 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 100 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 101 102 #define ID_LAST_MSG (1 << 0) 103 #define ID_FIRST_MSG (1 << 1) 104 #define ID_DONE (1 << 2) 105 #define ID_ARBLOST (1 << 3) 106 #define ID_NACK (1 << 4) 107 /* persistent flags */ 108 #define ID_P_REP_AFTER_RD BIT(29) 109 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 110 #define ID_P_PM_BLOCKED BIT(31) 111 #define ID_P_MASK GENMASK(31, 29) 112 113 enum rcar_i2c_type { 114 I2C_RCAR_GEN1, 115 I2C_RCAR_GEN2, 116 I2C_RCAR_GEN3, 117 }; 118 119 struct rcar_i2c_priv { 120 void __iomem *io; 121 struct i2c_adapter adap; 122 struct i2c_msg *msg; 123 int msgs_left; 124 struct clk *clk; 125 126 wait_queue_head_t wait; 127 128 int pos; 129 u32 icccr; 130 u32 flags; 131 u8 recovery_icmcr; /* protected by adapter lock */ 132 enum rcar_i2c_type devtype; 133 struct i2c_client *slave; 134 135 struct resource *res; 136 struct dma_chan *dma_tx; 137 struct dma_chan *dma_rx; 138 struct scatterlist sg; 139 enum dma_data_direction dma_direction; 140 141 struct reset_control *rstc; 142 }; 143 144 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 145 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 146 147 #define LOOP_TIMEOUT 1024 148 149 150 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 151 { 152 writel(val, priv->io + reg); 153 } 154 155 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 156 { 157 return readl(priv->io + reg); 158 } 159 160 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 161 { 162 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 163 164 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 165 166 }; 167 168 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 169 { 170 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 171 172 if (val) 173 priv->recovery_icmcr |= FSCL; 174 else 175 priv->recovery_icmcr &= ~FSCL; 176 177 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 178 }; 179 180 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 181 { 182 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 183 184 if (val) 185 priv->recovery_icmcr |= FSDA; 186 else 187 priv->recovery_icmcr &= ~FSDA; 188 189 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 190 }; 191 192 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 193 { 194 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 195 196 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 197 198 }; 199 200 static struct i2c_bus_recovery_info rcar_i2c_bri = { 201 .get_scl = rcar_i2c_get_scl, 202 .set_scl = rcar_i2c_set_scl, 203 .set_sda = rcar_i2c_set_sda, 204 .get_bus_free = rcar_i2c_get_bus_free, 205 .recover_bus = i2c_generic_scl_recovery, 206 }; 207 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 208 { 209 /* reset master mode */ 210 rcar_i2c_write(priv, ICMIER, 0); 211 rcar_i2c_write(priv, ICMCR, MDBS); 212 rcar_i2c_write(priv, ICMSR, 0); 213 /* start clock */ 214 rcar_i2c_write(priv, ICCCR, priv->icccr); 215 } 216 217 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 218 { 219 int i; 220 221 for (i = 0; i < LOOP_TIMEOUT; i++) { 222 /* make sure that bus is not busy */ 223 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 224 return 0; 225 udelay(1); 226 } 227 228 /* Waiting did not help, try to recover */ 229 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 230 return i2c_recover_bus(&priv->adap); 231 } 232 233 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) 234 { 235 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 236 unsigned long rate; 237 struct device *dev = rcar_i2c_priv_to_dev(priv); 238 239 /* Fall back to previously used values if not supplied */ 240 t->bus_freq_hz = t->bus_freq_hz ?: 100000; 241 t->scl_fall_ns = t->scl_fall_ns ?: 35; 242 t->scl_rise_ns = t->scl_rise_ns ?: 200; 243 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; 244 245 switch (priv->devtype) { 246 case I2C_RCAR_GEN1: 247 cdf_width = 2; 248 break; 249 case I2C_RCAR_GEN2: 250 case I2C_RCAR_GEN3: 251 cdf_width = 3; 252 break; 253 default: 254 dev_err(dev, "device type error\n"); 255 return -EIO; 256 } 257 258 /* 259 * calculate SCL clock 260 * see 261 * ICCCR 262 * 263 * ick = clkp / (1 + CDF) 264 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 265 * 266 * ick : I2C internal clock < 20 MHz 267 * ticf : I2C SCL falling time 268 * tr : I2C SCL rising time 269 * intd : LSI internal delay 270 * clkp : peripheral_clk 271 * F[] : integer up-valuation 272 */ 273 rate = clk_get_rate(priv->clk); 274 cdf = rate / 20000000; 275 if (cdf >= 1U << cdf_width) { 276 dev_err(dev, "Input clock %lu too high\n", rate); 277 return -EIO; 278 } 279 ick = rate / (cdf + 1); 280 281 /* 282 * it is impossible to calculate large scale 283 * number on u32. separate it 284 * 285 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 286 * = F[sum * ick / 1000000000] 287 * = F[(ick / 1000000) * sum / 1000] 288 */ 289 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; 290 round = (ick + 500000) / 1000000 * sum; 291 round = (round + 500) / 1000; 292 293 /* 294 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 295 * 296 * Calculation result (= SCL) should be less than 297 * bus_speed for hardware safety 298 * 299 * We could use something along the lines of 300 * div = ick / (bus_speed + 1) + 1; 301 * scgd = (div - 20 - round + 7) / 8; 302 * scl = ick / (20 + (scgd * 8) + round); 303 * (not fully verified) but that would get pretty involved 304 */ 305 for (scgd = 0; scgd < 0x40; scgd++) { 306 scl = ick / (20 + (scgd * 8) + round); 307 if (scl <= t->bus_freq_hz) 308 goto scgd_find; 309 } 310 dev_err(dev, "it is impossible to calculate best SCL\n"); 311 return -EIO; 312 313 scgd_find: 314 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 315 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); 316 317 /* keep icccr value */ 318 priv->icccr = scgd << cdf_width | cdf; 319 320 return 0; 321 } 322 323 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 324 { 325 int read = !!rcar_i2c_is_recv(priv); 326 327 priv->pos = 0; 328 if (priv->msgs_left == 1) 329 priv->flags |= ID_LAST_MSG; 330 331 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 332 /* 333 * We don't have a test case but the HW engineers say that the write order 334 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 335 * it didn't cause a drawback for me, let's rather be safe than sorry. 336 */ 337 if (priv->flags & ID_FIRST_MSG) { 338 rcar_i2c_write(priv, ICMSR, 0); 339 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 340 } else { 341 if (priv->flags & ID_P_REP_AFTER_RD) 342 priv->flags &= ~ID_P_REP_AFTER_RD; 343 else 344 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 345 rcar_i2c_write(priv, ICMSR, 0); 346 } 347 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 348 } 349 350 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 351 { 352 priv->msg++; 353 priv->msgs_left--; 354 priv->flags &= ID_P_MASK; 355 rcar_i2c_prepare_msg(priv); 356 } 357 358 /* 359 * interrupt functions 360 */ 361 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 362 { 363 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 364 ? priv->dma_rx : priv->dma_tx; 365 366 /* Disable DMA Master Received/Transmitted */ 367 rcar_i2c_write(priv, ICDMAER, 0); 368 369 /* Reset default delay */ 370 rcar_i2c_write(priv, ICFBSCR, TCYC06); 371 372 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 373 sg_dma_len(&priv->sg), priv->dma_direction); 374 375 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 376 if (priv->devtype == I2C_RCAR_GEN3 && 377 priv->dma_direction == DMA_FROM_DEVICE) 378 priv->flags |= ID_P_NO_RXDMA; 379 380 priv->dma_direction = DMA_NONE; 381 } 382 383 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 384 { 385 if (priv->dma_direction == DMA_NONE) 386 return; 387 else if (priv->dma_direction == DMA_FROM_DEVICE) 388 dmaengine_terminate_all(priv->dma_rx); 389 else if (priv->dma_direction == DMA_TO_DEVICE) 390 dmaengine_terminate_all(priv->dma_tx); 391 392 rcar_i2c_dma_unmap(priv); 393 } 394 395 static void rcar_i2c_dma_callback(void *data) 396 { 397 struct rcar_i2c_priv *priv = data; 398 399 priv->pos += sg_dma_len(&priv->sg); 400 401 rcar_i2c_dma_unmap(priv); 402 } 403 404 static void rcar_i2c_dma(struct rcar_i2c_priv *priv) 405 { 406 struct device *dev = rcar_i2c_priv_to_dev(priv); 407 struct i2c_msg *msg = priv->msg; 408 bool read = msg->flags & I2C_M_RD; 409 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 410 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 411 struct dma_async_tx_descriptor *txdesc; 412 dma_addr_t dma_addr; 413 dma_cookie_t cookie; 414 unsigned char *buf; 415 int len; 416 417 /* Do various checks to see if DMA is feasible at all */ 418 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) || 419 (read && priv->flags & ID_P_NO_RXDMA)) 420 return; 421 422 if (read) { 423 /* 424 * The last two bytes needs to be fetched using PIO in 425 * order for the STOP phase to work. 426 */ 427 buf = priv->msg->buf; 428 len = priv->msg->len - 2; 429 } else { 430 /* 431 * First byte in message was sent using PIO. 432 */ 433 buf = priv->msg->buf + 1; 434 len = priv->msg->len - 1; 435 } 436 437 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 438 if (dma_mapping_error(chan->device->dev, dma_addr)) { 439 dev_dbg(dev, "dma map failed, using PIO\n"); 440 return; 441 } 442 443 sg_dma_len(&priv->sg) = len; 444 sg_dma_address(&priv->sg) = dma_addr; 445 446 priv->dma_direction = dir; 447 448 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 449 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 450 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 451 if (!txdesc) { 452 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 453 rcar_i2c_cleanup_dma(priv); 454 return; 455 } 456 457 txdesc->callback = rcar_i2c_dma_callback; 458 txdesc->callback_param = priv; 459 460 cookie = dmaengine_submit(txdesc); 461 if (dma_submit_error(cookie)) { 462 dev_dbg(dev, "submitting dma failed, using PIO\n"); 463 rcar_i2c_cleanup_dma(priv); 464 return; 465 } 466 467 /* Set delay for DMA operations */ 468 rcar_i2c_write(priv, ICFBSCR, TCYC17); 469 470 /* Enable DMA Master Received/Transmitted */ 471 if (read) 472 rcar_i2c_write(priv, ICDMAER, RMDMAE); 473 else 474 rcar_i2c_write(priv, ICDMAER, TMDMAE); 475 476 dma_async_issue_pending(chan); 477 } 478 479 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 480 { 481 struct i2c_msg *msg = priv->msg; 482 483 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 484 if (!(msr & MDE)) 485 return; 486 487 if (priv->pos < msg->len) { 488 /* 489 * Prepare next data to ICRXTX register. 490 * This data will go to _SHIFT_ register. 491 * 492 * * 493 * [ICRXTX] -> [SHIFT] -> [I2C bus] 494 */ 495 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 496 priv->pos++; 497 498 /* 499 * Try to use DMA to transmit the rest of the data if 500 * address transfer phase just finished. 501 */ 502 if (msr & MAT) 503 rcar_i2c_dma(priv); 504 } else { 505 /* 506 * The last data was pushed to ICRXTX on _PREV_ empty irq. 507 * It is on _SHIFT_ register, and will sent to I2C bus. 508 * 509 * * 510 * [ICRXTX] -> [SHIFT] -> [I2C bus] 511 */ 512 513 if (priv->flags & ID_LAST_MSG) { 514 /* 515 * If current msg is the _LAST_ msg, 516 * prepare stop condition here. 517 * ID_DONE will be set on STOP irq. 518 */ 519 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 520 } else { 521 rcar_i2c_next_msg(priv); 522 return; 523 } 524 } 525 526 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 527 } 528 529 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 530 { 531 struct i2c_msg *msg = priv->msg; 532 533 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 534 if (!(msr & MDR)) 535 return; 536 537 if (msr & MAT) { 538 /* 539 * Address transfer phase finished, but no data at this point. 540 * Try to use DMA to receive data. 541 */ 542 rcar_i2c_dma(priv); 543 } else if (priv->pos < msg->len) { 544 /* get received data */ 545 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 546 priv->pos++; 547 } 548 549 /* If next received data is the _LAST_, go to new phase. */ 550 if (priv->pos + 1 == msg->len) { 551 if (priv->flags & ID_LAST_MSG) { 552 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 553 } else { 554 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 555 priv->flags |= ID_P_REP_AFTER_RD; 556 } 557 } 558 559 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 560 rcar_i2c_next_msg(priv); 561 else 562 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 563 } 564 565 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 566 { 567 u32 ssr_raw, ssr_filtered; 568 u8 value; 569 570 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 571 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 572 573 if (!ssr_filtered) 574 return false; 575 576 /* address detected */ 577 if (ssr_filtered & SAR) { 578 /* read or write request */ 579 if (ssr_raw & STM) { 580 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 581 rcar_i2c_write(priv, ICRXTX, value); 582 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 583 } else { 584 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 585 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 586 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 587 } 588 589 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); 590 } 591 592 /* master sent stop */ 593 if (ssr_filtered & SSR) { 594 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 595 rcar_i2c_write(priv, ICSIER, SAR | SSR); 596 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 597 } 598 599 /* master wants to write to us */ 600 if (ssr_filtered & SDR) { 601 int ret; 602 603 value = rcar_i2c_read(priv, ICRXTX); 604 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 605 /* Send NACK in case of error */ 606 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 607 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 608 } 609 610 /* master wants to read from us */ 611 if (ssr_filtered & SDE) { 612 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 613 rcar_i2c_write(priv, ICRXTX, value); 614 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 615 } 616 617 return true; 618 } 619 620 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 621 { 622 struct rcar_i2c_priv *priv = ptr; 623 u32 msr, val; 624 625 /* Clear START or STOP immediately, except for REPSTART after read */ 626 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) { 627 val = rcar_i2c_read(priv, ICMCR); 628 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); 629 } 630 631 msr = rcar_i2c_read(priv, ICMSR); 632 633 /* Only handle interrupts that are currently enabled */ 634 msr &= rcar_i2c_read(priv, ICMIER); 635 if (!msr) { 636 if (rcar_i2c_slave_irq(priv)) 637 return IRQ_HANDLED; 638 639 return IRQ_NONE; 640 } 641 642 /* Arbitration lost */ 643 if (msr & MAL) { 644 priv->flags |= ID_DONE | ID_ARBLOST; 645 goto out; 646 } 647 648 /* Nack */ 649 if (msr & MNR) { 650 /* HW automatically sends STOP after received NACK */ 651 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 652 priv->flags |= ID_NACK; 653 goto out; 654 } 655 656 /* Stop */ 657 if (msr & MST) { 658 priv->msgs_left--; /* The last message also made it */ 659 priv->flags |= ID_DONE; 660 goto out; 661 } 662 663 if (rcar_i2c_is_recv(priv)) 664 rcar_i2c_irq_recv(priv, msr); 665 else 666 rcar_i2c_irq_send(priv, msr); 667 668 out: 669 if (priv->flags & ID_DONE) { 670 rcar_i2c_write(priv, ICMIER, 0); 671 rcar_i2c_write(priv, ICMSR, 0); 672 wake_up(&priv->wait); 673 } 674 675 return IRQ_HANDLED; 676 } 677 678 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 679 enum dma_transfer_direction dir, 680 dma_addr_t port_addr) 681 { 682 struct dma_chan *chan; 683 struct dma_slave_config cfg; 684 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 685 int ret; 686 687 chan = dma_request_chan(dev, chan_name); 688 if (IS_ERR(chan)) { 689 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 690 chan_name, PTR_ERR(chan)); 691 return chan; 692 } 693 694 memset(&cfg, 0, sizeof(cfg)); 695 cfg.direction = dir; 696 if (dir == DMA_MEM_TO_DEV) { 697 cfg.dst_addr = port_addr; 698 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 699 } else { 700 cfg.src_addr = port_addr; 701 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 702 } 703 704 ret = dmaengine_slave_config(chan, &cfg); 705 if (ret) { 706 dev_dbg(dev, "slave_config failed for %s (%d)\n", 707 chan_name, ret); 708 dma_release_channel(chan); 709 return ERR_PTR(ret); 710 } 711 712 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 713 return chan; 714 } 715 716 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 717 struct i2c_msg *msg) 718 { 719 struct device *dev = rcar_i2c_priv_to_dev(priv); 720 bool read; 721 struct dma_chan *chan; 722 enum dma_transfer_direction dir; 723 724 read = msg->flags & I2C_M_RD; 725 726 chan = read ? priv->dma_rx : priv->dma_tx; 727 if (PTR_ERR(chan) != -EPROBE_DEFER) 728 return; 729 730 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 731 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 732 733 if (read) 734 priv->dma_rx = chan; 735 else 736 priv->dma_tx = chan; 737 } 738 739 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 740 { 741 if (!IS_ERR(priv->dma_tx)) { 742 dma_release_channel(priv->dma_tx); 743 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 744 } 745 746 if (!IS_ERR(priv->dma_rx)) { 747 dma_release_channel(priv->dma_rx); 748 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 749 } 750 } 751 752 /* I2C is a special case, we need to poll the status of a reset */ 753 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 754 { 755 int i, ret; 756 757 ret = reset_control_reset(priv->rstc); 758 if (ret) 759 return ret; 760 761 for (i = 0; i < LOOP_TIMEOUT; i++) { 762 ret = reset_control_status(priv->rstc); 763 if (ret == 0) 764 return 0; 765 udelay(1); 766 } 767 768 return -ETIMEDOUT; 769 } 770 771 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 772 struct i2c_msg *msgs, 773 int num) 774 { 775 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 776 struct device *dev = rcar_i2c_priv_to_dev(priv); 777 int i, ret; 778 long time_left; 779 780 pm_runtime_get_sync(dev); 781 782 /* Gen3 needs a reset before allowing RXDMA once */ 783 if (priv->devtype == I2C_RCAR_GEN3) { 784 priv->flags |= ID_P_NO_RXDMA; 785 if (!IS_ERR(priv->rstc)) { 786 ret = rcar_i2c_do_reset(priv); 787 if (ret == 0) 788 priv->flags &= ~ID_P_NO_RXDMA; 789 } 790 } 791 792 rcar_i2c_init(priv); 793 794 ret = rcar_i2c_bus_barrier(priv); 795 if (ret < 0) 796 goto out; 797 798 for (i = 0; i < num; i++) 799 rcar_i2c_request_dma(priv, msgs + i); 800 801 /* init first message */ 802 priv->msg = msgs; 803 priv->msgs_left = num; 804 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 805 rcar_i2c_prepare_msg(priv); 806 807 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 808 num * adap->timeout); 809 810 /* cleanup DMA if it couldn't complete properly due to an error */ 811 if (priv->dma_direction != DMA_NONE) 812 rcar_i2c_cleanup_dma(priv); 813 814 if (!time_left) { 815 rcar_i2c_init(priv); 816 ret = -ETIMEDOUT; 817 } else if (priv->flags & ID_NACK) { 818 ret = -ENXIO; 819 } else if (priv->flags & ID_ARBLOST) { 820 ret = -EAGAIN; 821 } else { 822 ret = num - priv->msgs_left; /* The number of transfer */ 823 } 824 out: 825 pm_runtime_put(dev); 826 827 if (ret < 0 && ret != -ENXIO) 828 dev_err(dev, "error %d : %x\n", ret, priv->flags); 829 830 return ret; 831 } 832 833 static int rcar_reg_slave(struct i2c_client *slave) 834 { 835 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 836 837 if (priv->slave) 838 return -EBUSY; 839 840 if (slave->flags & I2C_CLIENT_TEN) 841 return -EAFNOSUPPORT; 842 843 /* Keep device active for slave address detection logic */ 844 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 845 846 priv->slave = slave; 847 rcar_i2c_write(priv, ICSAR, slave->addr); 848 rcar_i2c_write(priv, ICSSR, 0); 849 rcar_i2c_write(priv, ICSIER, SAR | SSR); 850 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 851 852 return 0; 853 } 854 855 static int rcar_unreg_slave(struct i2c_client *slave) 856 { 857 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 858 859 WARN_ON(!priv->slave); 860 861 rcar_i2c_write(priv, ICSIER, 0); 862 rcar_i2c_write(priv, ICSCR, 0); 863 864 priv->slave = NULL; 865 866 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 867 868 return 0; 869 } 870 871 static u32 rcar_i2c_func(struct i2c_adapter *adap) 872 { 873 /* 874 * This HW can't do: 875 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 876 * I2C_M_NOSTART (automatically sends address after START) 877 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 878 */ 879 return I2C_FUNC_I2C | I2C_FUNC_SLAVE | 880 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 881 } 882 883 static const struct i2c_algorithm rcar_i2c_algo = { 884 .master_xfer = rcar_i2c_master_xfer, 885 .functionality = rcar_i2c_func, 886 .reg_slave = rcar_reg_slave, 887 .unreg_slave = rcar_unreg_slave, 888 }; 889 890 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 891 .flags = I2C_AQ_NO_ZERO_LEN, 892 }; 893 894 static const struct of_device_id rcar_i2c_dt_ids[] = { 895 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 896 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 897 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 898 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 899 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 900 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 901 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 902 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 903 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 904 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 905 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 906 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 907 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 908 {}, 909 }; 910 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 911 912 static int rcar_i2c_probe(struct platform_device *pdev) 913 { 914 struct rcar_i2c_priv *priv; 915 struct i2c_adapter *adap; 916 struct device *dev = &pdev->dev; 917 struct i2c_timings i2c_t; 918 int irq, ret; 919 920 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 921 if (!priv) 922 return -ENOMEM; 923 924 priv->clk = devm_clk_get(dev, NULL); 925 if (IS_ERR(priv->clk)) { 926 dev_err(dev, "cannot get clock\n"); 927 return PTR_ERR(priv->clk); 928 } 929 930 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 931 932 priv->io = devm_ioremap_resource(dev, priv->res); 933 if (IS_ERR(priv->io)) 934 return PTR_ERR(priv->io); 935 936 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 937 init_waitqueue_head(&priv->wait); 938 939 adap = &priv->adap; 940 adap->nr = pdev->id; 941 adap->algo = &rcar_i2c_algo; 942 adap->class = I2C_CLASS_DEPRECATED; 943 adap->retries = 3; 944 adap->dev.parent = dev; 945 adap->dev.of_node = dev->of_node; 946 adap->bus_recovery_info = &rcar_i2c_bri; 947 adap->quirks = &rcar_i2c_quirks; 948 i2c_set_adapdata(adap, priv); 949 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 950 951 i2c_parse_fw_timings(dev, &i2c_t, false); 952 953 /* Init DMA */ 954 sg_init_table(&priv->sg, 1); 955 priv->dma_direction = DMA_NONE; 956 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 957 958 /* Activate device for clock calculation */ 959 pm_runtime_enable(dev); 960 pm_runtime_get_sync(dev); 961 ret = rcar_i2c_clock_calculate(priv, &i2c_t); 962 if (ret < 0) 963 goto out_pm_put; 964 965 if (priv->devtype == I2C_RCAR_GEN3) { 966 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 967 if (!IS_ERR(priv->rstc)) { 968 ret = reset_control_status(priv->rstc); 969 if (ret < 0) 970 priv->rstc = ERR_PTR(-ENOTSUPP); 971 } 972 } 973 974 /* Stay always active when multi-master to keep arbitration working */ 975 if (of_property_read_bool(dev->of_node, "multi-master")) 976 priv->flags |= ID_P_PM_BLOCKED; 977 else 978 pm_runtime_put(dev); 979 980 981 irq = platform_get_irq(pdev, 0); 982 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); 983 if (ret < 0) { 984 dev_err(dev, "cannot get irq %d\n", irq); 985 goto out_pm_disable; 986 } 987 988 platform_set_drvdata(pdev, priv); 989 990 ret = i2c_add_numbered_adapter(adap); 991 if (ret < 0) 992 goto out_pm_disable; 993 994 dev_info(dev, "probed\n"); 995 996 return 0; 997 998 out_pm_put: 999 pm_runtime_put(dev); 1000 out_pm_disable: 1001 pm_runtime_disable(dev); 1002 return ret; 1003 } 1004 1005 static int rcar_i2c_remove(struct platform_device *pdev) 1006 { 1007 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1008 struct device *dev = &pdev->dev; 1009 1010 i2c_del_adapter(&priv->adap); 1011 rcar_i2c_release_dma(priv); 1012 if (priv->flags & ID_P_PM_BLOCKED) 1013 pm_runtime_put(dev); 1014 pm_runtime_disable(dev); 1015 1016 return 0; 1017 } 1018 1019 static struct platform_driver rcar_i2c_driver = { 1020 .driver = { 1021 .name = "i2c-rcar", 1022 .of_match_table = rcar_i2c_dt_ids, 1023 }, 1024 .probe = rcar_i2c_probe, 1025 .remove = rcar_i2c_remove, 1026 }; 1027 1028 module_platform_driver(rcar_i2c_driver); 1029 1030 MODULE_LICENSE("GPL v2"); 1031 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1032 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1033