1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2014, Sony Mobile Communications AB. 5 * 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/atomic.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dmapool.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/scatterlist.h> 24 25 /* QUP Registers */ 26 #define QUP_CONFIG 0x000 27 #define QUP_STATE 0x004 28 #define QUP_IO_MODE 0x008 29 #define QUP_SW_RESET 0x00c 30 #define QUP_OPERATIONAL 0x018 31 #define QUP_ERROR_FLAGS 0x01c 32 #define QUP_ERROR_FLAGS_EN 0x020 33 #define QUP_OPERATIONAL_MASK 0x028 34 #define QUP_HW_VERSION 0x030 35 #define QUP_MX_OUTPUT_CNT 0x100 36 #define QUP_OUT_FIFO_BASE 0x110 37 #define QUP_MX_WRITE_CNT 0x150 38 #define QUP_MX_INPUT_CNT 0x200 39 #define QUP_MX_READ_CNT 0x208 40 #define QUP_IN_FIFO_BASE 0x218 41 #define QUP_I2C_CLK_CTL 0x400 42 #define QUP_I2C_STATUS 0x404 43 #define QUP_I2C_MASTER_GEN 0x408 44 45 /* QUP States and reset values */ 46 #define QUP_RESET_STATE 0 47 #define QUP_RUN_STATE 1 48 #define QUP_PAUSE_STATE 3 49 #define QUP_STATE_MASK 3 50 51 #define QUP_STATE_VALID BIT(2) 52 #define QUP_I2C_MAST_GEN BIT(4) 53 #define QUP_I2C_FLUSH BIT(6) 54 55 #define QUP_OPERATIONAL_RESET 0x000ff0 56 #define QUP_I2C_STATUS_RESET 0xfffffc 57 58 /* QUP OPERATIONAL FLAGS */ 59 #define QUP_I2C_NACK_FLAG BIT(3) 60 #define QUP_OUT_NOT_EMPTY BIT(4) 61 #define QUP_IN_NOT_EMPTY BIT(5) 62 #define QUP_OUT_FULL BIT(6) 63 #define QUP_OUT_SVC_FLAG BIT(8) 64 #define QUP_IN_SVC_FLAG BIT(9) 65 #define QUP_MX_OUTPUT_DONE BIT(10) 66 #define QUP_MX_INPUT_DONE BIT(11) 67 #define OUT_BLOCK_WRITE_REQ BIT(12) 68 #define IN_BLOCK_READ_REQ BIT(13) 69 70 /* I2C mini core related values */ 71 #define QUP_NO_INPUT BIT(7) 72 #define QUP_CLOCK_AUTO_GATE BIT(13) 73 #define I2C_MINI_CORE (2 << 8) 74 #define I2C_N_VAL 15 75 #define I2C_N_VAL_V2 7 76 77 /* Most significant word offset in FIFO port */ 78 #define QUP_MSW_SHIFT (I2C_N_VAL + 1) 79 80 /* Packing/Unpacking words in FIFOs, and IO modes */ 81 #define QUP_OUTPUT_BLK_MODE (1 << 10) 82 #define QUP_OUTPUT_BAM_MODE (3 << 10) 83 #define QUP_INPUT_BLK_MODE (1 << 12) 84 #define QUP_INPUT_BAM_MODE (3 << 12) 85 #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE) 86 #define QUP_UNPACK_EN BIT(14) 87 #define QUP_PACK_EN BIT(15) 88 89 #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN) 90 #define QUP_V2_TAGS_EN 1 91 92 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03) 93 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07) 94 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03) 95 #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07) 96 97 /* QUP tags */ 98 #define QUP_TAG_START (1 << 8) 99 #define QUP_TAG_DATA (2 << 8) 100 #define QUP_TAG_STOP (3 << 8) 101 #define QUP_TAG_REC (4 << 8) 102 #define QUP_BAM_INPUT_EOT 0x93 103 #define QUP_BAM_FLUSH_STOP 0x96 104 105 /* QUP v2 tags */ 106 #define QUP_TAG_V2_START 0x81 107 #define QUP_TAG_V2_DATAWR 0x82 108 #define QUP_TAG_V2_DATAWR_STOP 0x83 109 #define QUP_TAG_V2_DATARD 0x85 110 #define QUP_TAG_V2_DATARD_NACK 0x86 111 #define QUP_TAG_V2_DATARD_STOP 0x87 112 113 /* Status, Error flags */ 114 #define I2C_STATUS_WR_BUFFER_FULL BIT(0) 115 #define I2C_STATUS_BUS_ACTIVE BIT(8) 116 #define I2C_STATUS_ERROR_MASK 0x38000fc 117 #define QUP_STATUS_ERROR_FLAGS 0x7c 118 119 #define QUP_READ_LIMIT 256 120 #define SET_BIT 0x1 121 #define RESET_BIT 0x0 122 #define ONE_BYTE 0x1 123 #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31) 124 125 /* Maximum transfer length for single DMA descriptor */ 126 #define MX_TX_RX_LEN SZ_64K 127 #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT) 128 /* Maximum transfer length for all DMA descriptors */ 129 #define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN) 130 #define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT) 131 132 /* 133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on 134 * the top of maximum transfer time calculated from i2c bus speed to compensate 135 * the overheads. 136 */ 137 #define TOUT_MIN 2 138 139 /* I2C Frequency Modes */ 140 #define I2C_STANDARD_FREQ 100000 141 #define I2C_FAST_MODE_FREQ 400000 142 #define I2C_FAST_MODE_PLUS_FREQ 1000000 143 144 /* Default values. Use these if FW query fails */ 145 #define DEFAULT_CLK_FREQ I2C_STANDARD_FREQ 146 #define DEFAULT_SRC_CLK 20000000 147 148 /* 149 * Max tags length (start, stop and maximum 2 bytes address) for each QUP 150 * data transfer 151 */ 152 #define QUP_MAX_TAGS_LEN 4 153 /* Max data length for each DATARD tags */ 154 #define RECV_MAX_DATA_LEN 254 155 /* TAG length for DATA READ in RX FIFO */ 156 #define READ_RX_TAGS_LEN 2 157 158 /* 159 * count: no of blocks 160 * pos: current block number 161 * tx_tag_len: tx tag length for current block 162 * rx_tag_len: rx tag length for current block 163 * data_len: remaining data length for current message 164 * cur_blk_len: data length for current block 165 * total_tx_len: total tx length including tag bytes for current QUP transfer 166 * total_rx_len: total rx length including tag bytes for current QUP transfer 167 * tx_fifo_data_pos: current byte number in TX FIFO word 168 * tx_fifo_free: number of free bytes in current QUP block write. 169 * rx_fifo_data_pos: current byte number in RX FIFO word 170 * fifo_available: number of available bytes in RX FIFO for current 171 * QUP block read 172 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write 173 * to TX FIFO will be appended in this data and will be written to 174 * TX FIFO when all the 4 bytes are available. 175 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will 176 * contains the 4 bytes of RX data. 177 * cur_data: pointer to tell cur data position for current message 178 * cur_tx_tags: pointer to tell cur position in tags 179 * tx_tags_sent: all tx tag bytes have been written in FIFO word 180 * send_last_word: for tx FIFO, last word send is pending in current block 181 * rx_bytes_read: if all the bytes have been read from rx FIFO. 182 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word 183 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer. 184 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer. 185 * tags: contains tx tag bytes for current QUP transfer 186 */ 187 struct qup_i2c_block { 188 int count; 189 int pos; 190 int tx_tag_len; 191 int rx_tag_len; 192 int data_len; 193 int cur_blk_len; 194 int total_tx_len; 195 int total_rx_len; 196 int tx_fifo_data_pos; 197 int tx_fifo_free; 198 int rx_fifo_data_pos; 199 int fifo_available; 200 u32 tx_fifo_data; 201 u32 rx_fifo_data; 202 u8 *cur_data; 203 u8 *cur_tx_tags; 204 bool tx_tags_sent; 205 bool send_last_word; 206 bool rx_tags_fetched; 207 bool rx_bytes_read; 208 bool is_tx_blk_mode; 209 bool is_rx_blk_mode; 210 u8 tags[6]; 211 }; 212 213 struct qup_i2c_tag { 214 u8 *start; 215 dma_addr_t addr; 216 }; 217 218 struct qup_i2c_bam { 219 struct qup_i2c_tag tag; 220 struct dma_chan *dma; 221 struct scatterlist *sg; 222 unsigned int sg_cnt; 223 }; 224 225 struct qup_i2c_dev { 226 struct device *dev; 227 void __iomem *base; 228 int irq; 229 struct clk *clk; 230 struct clk *pclk; 231 struct i2c_adapter adap; 232 233 int clk_ctl; 234 int out_fifo_sz; 235 int in_fifo_sz; 236 int out_blk_sz; 237 int in_blk_sz; 238 239 int blk_xfer_limit; 240 unsigned long one_byte_t; 241 unsigned long xfer_timeout; 242 struct qup_i2c_block blk; 243 244 struct i2c_msg *msg; 245 /* Current posion in user message buffer */ 246 int pos; 247 /* I2C protocol errors */ 248 u32 bus_err; 249 /* QUP core errors */ 250 u32 qup_err; 251 252 /* To check if this is the last msg */ 253 bool is_last; 254 bool is_smbus_read; 255 256 /* To configure when bus is in run state */ 257 u32 config_run; 258 259 /* dma parameters */ 260 bool is_dma; 261 /* To check if the current transfer is using DMA */ 262 bool use_dma; 263 unsigned int max_xfer_sg_len; 264 unsigned int tag_buf_pos; 265 /* The threshold length above which block mode will be used */ 266 unsigned int blk_mode_threshold; 267 struct dma_pool *dpool; 268 struct qup_i2c_tag start_tag; 269 struct qup_i2c_bam brx; 270 struct qup_i2c_bam btx; 271 272 struct completion xfer; 273 /* function to write data in tx fifo */ 274 void (*write_tx_fifo)(struct qup_i2c_dev *qup); 275 /* function to read data from rx fifo */ 276 void (*read_rx_fifo)(struct qup_i2c_dev *qup); 277 /* function to write tags in tx fifo for i2c read transfer */ 278 void (*write_rx_tags)(struct qup_i2c_dev *qup); 279 }; 280 281 static irqreturn_t qup_i2c_interrupt(int irq, void *dev) 282 { 283 struct qup_i2c_dev *qup = dev; 284 struct qup_i2c_block *blk = &qup->blk; 285 u32 bus_err; 286 u32 qup_err; 287 u32 opflags; 288 289 bus_err = readl(qup->base + QUP_I2C_STATUS); 290 qup_err = readl(qup->base + QUP_ERROR_FLAGS); 291 opflags = readl(qup->base + QUP_OPERATIONAL); 292 293 if (!qup->msg) { 294 /* Clear Error interrupt */ 295 writel(QUP_RESET_STATE, qup->base + QUP_STATE); 296 return IRQ_HANDLED; 297 } 298 299 bus_err &= I2C_STATUS_ERROR_MASK; 300 qup_err &= QUP_STATUS_ERROR_FLAGS; 301 302 /* Clear the error bits in QUP_ERROR_FLAGS */ 303 if (qup_err) 304 writel(qup_err, qup->base + QUP_ERROR_FLAGS); 305 306 /* Clear the error bits in QUP_I2C_STATUS */ 307 if (bus_err) 308 writel(bus_err, qup->base + QUP_I2C_STATUS); 309 310 /* 311 * Check for BAM mode and returns if already error has come for current 312 * transfer. In Error case, sometimes, QUP generates more than one 313 * interrupt. 314 */ 315 if (qup->use_dma && (qup->qup_err || qup->bus_err)) 316 return IRQ_HANDLED; 317 318 /* Reset the QUP State in case of error */ 319 if (qup_err || bus_err) { 320 /* 321 * Don’t reset the QUP state in case of BAM mode. The BAM 322 * flush operation needs to be scheduled in transfer function 323 * which will clear the remaining schedule descriptors in BAM 324 * HW FIFO and generates the BAM interrupt. 325 */ 326 if (!qup->use_dma) 327 writel(QUP_RESET_STATE, qup->base + QUP_STATE); 328 goto done; 329 } 330 331 if (opflags & QUP_OUT_SVC_FLAG) { 332 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); 333 334 if (opflags & OUT_BLOCK_WRITE_REQ) { 335 blk->tx_fifo_free += qup->out_blk_sz; 336 if (qup->msg->flags & I2C_M_RD) 337 qup->write_rx_tags(qup); 338 else 339 qup->write_tx_fifo(qup); 340 } 341 } 342 343 if (opflags & QUP_IN_SVC_FLAG) { 344 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); 345 346 if (!blk->is_rx_blk_mode) { 347 blk->fifo_available += qup->in_fifo_sz; 348 qup->read_rx_fifo(qup); 349 } else if (opflags & IN_BLOCK_READ_REQ) { 350 blk->fifo_available += qup->in_blk_sz; 351 qup->read_rx_fifo(qup); 352 } 353 } 354 355 if (qup->msg->flags & I2C_M_RD) { 356 if (!blk->rx_bytes_read) 357 return IRQ_HANDLED; 358 } else { 359 /* 360 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked 361 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags 362 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason 363 * of interrupt for write message in FIFO mode is 364 * QUP_MAX_OUTPUT_DONE_FLAG condition. 365 */ 366 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE)) 367 return IRQ_HANDLED; 368 } 369 370 done: 371 qup->qup_err = qup_err; 372 qup->bus_err = bus_err; 373 complete(&qup->xfer); 374 return IRQ_HANDLED; 375 } 376 377 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup, 378 u32 req_state, u32 req_mask) 379 { 380 int retries = 1; 381 u32 state; 382 383 /* 384 * State transition takes 3 AHB clocks cycles + 3 I2C master clock 385 * cycles. So retry once after a 1uS delay. 386 */ 387 do { 388 state = readl(qup->base + QUP_STATE); 389 390 if (state & QUP_STATE_VALID && 391 (state & req_mask) == req_state) 392 return 0; 393 394 udelay(1); 395 } while (retries--); 396 397 return -ETIMEDOUT; 398 } 399 400 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state) 401 { 402 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK); 403 } 404 405 static void qup_i2c_flush(struct qup_i2c_dev *qup) 406 { 407 u32 val = readl(qup->base + QUP_STATE); 408 409 val |= QUP_I2C_FLUSH; 410 writel(val, qup->base + QUP_STATE); 411 } 412 413 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup) 414 { 415 return qup_i2c_poll_state_mask(qup, 0, 0); 416 } 417 418 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup) 419 { 420 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN); 421 } 422 423 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state) 424 { 425 if (qup_i2c_poll_state_valid(qup) != 0) 426 return -EIO; 427 428 writel(state, qup->base + QUP_STATE); 429 430 if (qup_i2c_poll_state(qup, state) != 0) 431 return -EIO; 432 return 0; 433 } 434 435 /* Check if I2C bus returns to IDLE state */ 436 static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len) 437 { 438 unsigned long timeout; 439 u32 status; 440 int ret = 0; 441 442 timeout = jiffies + len * 4; 443 for (;;) { 444 status = readl(qup->base + QUP_I2C_STATUS); 445 if (!(status & I2C_STATUS_BUS_ACTIVE)) 446 break; 447 448 if (time_after(jiffies, timeout)) 449 ret = -ETIMEDOUT; 450 451 usleep_range(len, len * 2); 452 } 453 454 return ret; 455 } 456 457 static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup) 458 { 459 struct qup_i2c_block *blk = &qup->blk; 460 struct i2c_msg *msg = qup->msg; 461 u32 addr = msg->addr << 1; 462 u32 qup_tag; 463 int idx; 464 u32 val; 465 466 if (qup->pos == 0) { 467 val = QUP_TAG_START | addr; 468 idx = 1; 469 blk->tx_fifo_free--; 470 } else { 471 val = 0; 472 idx = 0; 473 } 474 475 while (blk->tx_fifo_free && qup->pos < msg->len) { 476 if (qup->pos == msg->len - 1) 477 qup_tag = QUP_TAG_STOP; 478 else 479 qup_tag = QUP_TAG_DATA; 480 481 if (idx & 1) 482 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; 483 else 484 val = qup_tag | msg->buf[qup->pos]; 485 486 /* Write out the pair and the last odd value */ 487 if (idx & 1 || qup->pos == msg->len - 1) 488 writel(val, qup->base + QUP_OUT_FIFO_BASE); 489 490 qup->pos++; 491 idx++; 492 blk->tx_fifo_free--; 493 } 494 } 495 496 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup, 497 struct i2c_msg *msg) 498 { 499 qup->blk.pos = 0; 500 qup->blk.data_len = msg->len; 501 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); 502 } 503 504 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup) 505 { 506 int data_len; 507 508 if (qup->blk.data_len > qup->blk_xfer_limit) 509 data_len = qup->blk_xfer_limit; 510 else 511 data_len = qup->blk.data_len; 512 513 return data_len; 514 } 515 516 static bool qup_i2c_check_msg_len(struct i2c_msg *msg) 517 { 518 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN)); 519 } 520 521 static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup, 522 struct i2c_msg *msg) 523 { 524 int len = 0; 525 526 if (qup->is_smbus_read) { 527 tags[len++] = QUP_TAG_V2_DATARD_STOP; 528 tags[len++] = qup_i2c_get_data_len(qup); 529 } else { 530 tags[len++] = QUP_TAG_V2_START; 531 tags[len++] = addr & 0xff; 532 533 if (msg->flags & I2C_M_TEN) 534 tags[len++] = addr >> 8; 535 536 tags[len++] = QUP_TAG_V2_DATARD; 537 /* Read 1 byte indicating the length of the SMBus message */ 538 tags[len++] = 1; 539 } 540 return len; 541 } 542 543 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup, 544 struct i2c_msg *msg) 545 { 546 u16 addr = i2c_8bit_addr_from_msg(msg); 547 int len = 0; 548 int data_len; 549 550 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); 551 552 /* Handle tags for SMBus block read */ 553 if (qup_i2c_check_msg_len(msg)) 554 return qup_i2c_set_tags_smb(addr, tags, qup, msg); 555 556 if (qup->blk.pos == 0) { 557 tags[len++] = QUP_TAG_V2_START; 558 tags[len++] = addr & 0xff; 559 560 if (msg->flags & I2C_M_TEN) 561 tags[len++] = addr >> 8; 562 } 563 564 /* Send _STOP commands for the last block */ 565 if (last) { 566 if (msg->flags & I2C_M_RD) 567 tags[len++] = QUP_TAG_V2_DATARD_STOP; 568 else 569 tags[len++] = QUP_TAG_V2_DATAWR_STOP; 570 } else { 571 if (msg->flags & I2C_M_RD) 572 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? 573 QUP_TAG_V2_DATARD_NACK : 574 QUP_TAG_V2_DATARD; 575 else 576 tags[len++] = QUP_TAG_V2_DATAWR; 577 } 578 579 data_len = qup_i2c_get_data_len(qup); 580 581 /* 0 implies 256 bytes */ 582 if (data_len == QUP_READ_LIMIT) 583 tags[len++] = 0; 584 else 585 tags[len++] = data_len; 586 587 return len; 588 } 589 590 591 static void qup_i2c_bam_cb(void *data) 592 { 593 struct qup_i2c_dev *qup = data; 594 595 complete(&qup->xfer); 596 } 597 598 static int qup_sg_set_buf(struct scatterlist *sg, void *buf, 599 unsigned int buflen, struct qup_i2c_dev *qup, 600 int dir) 601 { 602 int ret; 603 604 sg_set_buf(sg, buf, buflen); 605 ret = dma_map_sg(qup->dev, sg, 1, dir); 606 if (!ret) 607 return -EINVAL; 608 609 return 0; 610 } 611 612 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup) 613 { 614 if (qup->btx.dma) 615 dma_release_channel(qup->btx.dma); 616 if (qup->brx.dma) 617 dma_release_channel(qup->brx.dma); 618 qup->btx.dma = NULL; 619 qup->brx.dma = NULL; 620 } 621 622 static int qup_i2c_req_dma(struct qup_i2c_dev *qup) 623 { 624 int err; 625 626 if (!qup->btx.dma) { 627 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx"); 628 if (IS_ERR(qup->btx.dma)) { 629 err = PTR_ERR(qup->btx.dma); 630 qup->btx.dma = NULL; 631 dev_err(qup->dev, "\n tx channel not available"); 632 return err; 633 } 634 } 635 636 if (!qup->brx.dma) { 637 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx"); 638 if (IS_ERR(qup->brx.dma)) { 639 dev_err(qup->dev, "\n rx channel not available"); 640 err = PTR_ERR(qup->brx.dma); 641 qup->brx.dma = NULL; 642 qup_i2c_rel_dma(qup); 643 return err; 644 } 645 } 646 return 0; 647 } 648 649 static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg) 650 { 651 int ret = 0, limit = QUP_READ_LIMIT; 652 u32 len = 0, blocks, rem; 653 u32 i = 0, tlen, tx_len = 0; 654 u8 *tags; 655 656 qup->blk_xfer_limit = QUP_READ_LIMIT; 657 qup_i2c_set_blk_data(qup, msg); 658 659 blocks = qup->blk.count; 660 rem = msg->len - (blocks - 1) * limit; 661 662 if (msg->flags & I2C_M_RD) { 663 while (qup->blk.pos < blocks) { 664 tlen = (i == (blocks - 1)) ? rem : limit; 665 tags = &qup->start_tag.start[qup->tag_buf_pos + len]; 666 len += qup_i2c_set_tags(tags, qup, msg); 667 qup->blk.data_len -= tlen; 668 669 /* scratch buf to read the start and len tags */ 670 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], 671 &qup->brx.tag.start[0], 672 2, qup, DMA_FROM_DEVICE); 673 674 if (ret) 675 return ret; 676 677 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], 678 &msg->buf[limit * i], 679 tlen, qup, 680 DMA_FROM_DEVICE); 681 if (ret) 682 return ret; 683 684 i++; 685 qup->blk.pos = i; 686 } 687 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], 688 &qup->start_tag.start[qup->tag_buf_pos], 689 len, qup, DMA_TO_DEVICE); 690 if (ret) 691 return ret; 692 693 qup->tag_buf_pos += len; 694 } else { 695 while (qup->blk.pos < blocks) { 696 tlen = (i == (blocks - 1)) ? rem : limit; 697 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; 698 len = qup_i2c_set_tags(tags, qup, msg); 699 qup->blk.data_len -= tlen; 700 701 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], 702 tags, len, 703 qup, DMA_TO_DEVICE); 704 if (ret) 705 return ret; 706 707 tx_len += len; 708 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], 709 &msg->buf[limit * i], 710 tlen, qup, DMA_TO_DEVICE); 711 if (ret) 712 return ret; 713 i++; 714 qup->blk.pos = i; 715 } 716 717 qup->tag_buf_pos += tx_len; 718 } 719 720 return 0; 721 } 722 723 static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup) 724 { 725 struct dma_async_tx_descriptor *txd, *rxd = NULL; 726 int ret = 0; 727 dma_cookie_t cookie_rx, cookie_tx; 728 u32 len = 0; 729 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; 730 731 /* schedule the EOT and FLUSH I2C tags */ 732 len = 1; 733 if (rx_cnt) { 734 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; 735 len++; 736 737 /* scratch buf to read the BAM EOT FLUSH tags */ 738 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], 739 &qup->brx.tag.start[0], 740 1, qup, DMA_FROM_DEVICE); 741 if (ret) 742 return ret; 743 } 744 745 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; 746 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], 747 len, qup, DMA_TO_DEVICE); 748 if (ret) 749 return ret; 750 751 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, 752 DMA_MEM_TO_DEV, 753 DMA_PREP_INTERRUPT | DMA_PREP_FENCE); 754 if (!txd) { 755 dev_err(qup->dev, "failed to get tx desc\n"); 756 ret = -EINVAL; 757 goto desc_err; 758 } 759 760 if (!rx_cnt) { 761 txd->callback = qup_i2c_bam_cb; 762 txd->callback_param = qup; 763 } 764 765 cookie_tx = dmaengine_submit(txd); 766 if (dma_submit_error(cookie_tx)) { 767 ret = -EINVAL; 768 goto desc_err; 769 } 770 771 dma_async_issue_pending(qup->btx.dma); 772 773 if (rx_cnt) { 774 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, 775 rx_cnt, DMA_DEV_TO_MEM, 776 DMA_PREP_INTERRUPT); 777 if (!rxd) { 778 dev_err(qup->dev, "failed to get rx desc\n"); 779 ret = -EINVAL; 780 781 /* abort TX descriptors */ 782 dmaengine_terminate_all(qup->btx.dma); 783 goto desc_err; 784 } 785 786 rxd->callback = qup_i2c_bam_cb; 787 rxd->callback_param = qup; 788 cookie_rx = dmaengine_submit(rxd); 789 if (dma_submit_error(cookie_rx)) { 790 ret = -EINVAL; 791 goto desc_err; 792 } 793 794 dma_async_issue_pending(qup->brx.dma); 795 } 796 797 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) { 798 dev_err(qup->dev, "normal trans timed out\n"); 799 ret = -ETIMEDOUT; 800 } 801 802 if (ret || qup->bus_err || qup->qup_err) { 803 reinit_completion(&qup->xfer); 804 805 if (qup_i2c_change_state(qup, QUP_RUN_STATE)) { 806 dev_err(qup->dev, "change to run state timed out"); 807 goto desc_err; 808 } 809 810 qup_i2c_flush(qup); 811 812 /* wait for remaining interrupts to occur */ 813 if (!wait_for_completion_timeout(&qup->xfer, HZ)) 814 dev_err(qup->dev, "flush timed out\n"); 815 816 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; 817 } 818 819 desc_err: 820 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); 821 822 if (rx_cnt) 823 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, 824 DMA_FROM_DEVICE); 825 826 return ret; 827 } 828 829 static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup) 830 { 831 qup->btx.sg_cnt = 0; 832 qup->brx.sg_cnt = 0; 833 qup->tag_buf_pos = 0; 834 } 835 836 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, 837 int num) 838 { 839 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); 840 int ret = 0; 841 int idx = 0; 842 843 enable_irq(qup->irq); 844 ret = qup_i2c_req_dma(qup); 845 846 if (ret) 847 goto out; 848 849 writel(0, qup->base + QUP_MX_INPUT_CNT); 850 writel(0, qup->base + QUP_MX_OUTPUT_CNT); 851 852 /* set BAM mode */ 853 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); 854 855 /* mask fifo irqs */ 856 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); 857 858 /* set RUN STATE */ 859 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 860 if (ret) 861 goto out; 862 863 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); 864 qup_i2c_bam_clear_tag_buffers(qup); 865 866 for (idx = 0; idx < num; idx++) { 867 qup->msg = msg + idx; 868 qup->is_last = idx == (num - 1); 869 870 ret = qup_i2c_bam_make_desc(qup, qup->msg); 871 if (ret) 872 break; 873 874 /* 875 * Make DMA descriptor and schedule the BAM transfer if its 876 * already crossed the maximum length. Since the memory for all 877 * tags buffers have been taken for 2 maximum possible 878 * transfers length so it will never cross the buffer actual 879 * length. 880 */ 881 if (qup->btx.sg_cnt > qup->max_xfer_sg_len || 882 qup->brx.sg_cnt > qup->max_xfer_sg_len || 883 qup->is_last) { 884 ret = qup_i2c_bam_schedule_desc(qup); 885 if (ret) 886 break; 887 888 qup_i2c_bam_clear_tag_buffers(qup); 889 } 890 } 891 892 out: 893 disable_irq(qup->irq); 894 895 qup->msg = NULL; 896 return ret; 897 } 898 899 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup, 900 struct i2c_msg *msg) 901 { 902 unsigned long left; 903 int ret = 0; 904 905 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); 906 if (!left) { 907 writel(1, qup->base + QUP_SW_RESET); 908 ret = -ETIMEDOUT; 909 } 910 911 if (qup->bus_err || qup->qup_err) 912 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; 913 914 return ret; 915 } 916 917 static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup) 918 { 919 struct qup_i2c_block *blk = &qup->blk; 920 struct i2c_msg *msg = qup->msg; 921 u32 val = 0; 922 int idx = 0; 923 924 while (blk->fifo_available && qup->pos < msg->len) { 925 if ((idx & 1) == 0) { 926 /* Reading 2 words at time */ 927 val = readl(qup->base + QUP_IN_FIFO_BASE); 928 msg->buf[qup->pos++] = val & 0xFF; 929 } else { 930 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; 931 } 932 idx++; 933 blk->fifo_available--; 934 } 935 936 if (qup->pos == msg->len) 937 blk->rx_bytes_read = true; 938 } 939 940 static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup) 941 { 942 struct i2c_msg *msg = qup->msg; 943 u32 addr, len, val; 944 945 addr = i2c_8bit_addr_from_msg(msg); 946 947 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */ 948 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; 949 950 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr; 951 writel(val, qup->base + QUP_OUT_FIFO_BASE); 952 } 953 954 static void qup_i2c_conf_v1(struct qup_i2c_dev *qup) 955 { 956 struct qup_i2c_block *blk = &qup->blk; 957 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL; 958 u32 io_mode = QUP_REPACK_EN; 959 960 blk->is_tx_blk_mode = 961 blk->total_tx_len > qup->out_fifo_sz ? true : false; 962 blk->is_rx_blk_mode = 963 blk->total_rx_len > qup->in_fifo_sz ? true : false; 964 965 if (blk->is_tx_blk_mode) { 966 io_mode |= QUP_OUTPUT_BLK_MODE; 967 writel(0, qup->base + QUP_MX_WRITE_CNT); 968 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); 969 } else { 970 writel(0, qup->base + QUP_MX_OUTPUT_CNT); 971 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); 972 } 973 974 if (blk->total_rx_len) { 975 if (blk->is_rx_blk_mode) { 976 io_mode |= QUP_INPUT_BLK_MODE; 977 writel(0, qup->base + QUP_MX_READ_CNT); 978 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); 979 } else { 980 writel(0, qup->base + QUP_MX_INPUT_CNT); 981 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); 982 } 983 } else { 984 qup_config |= QUP_NO_INPUT; 985 } 986 987 writel(qup_config, qup->base + QUP_CONFIG); 988 writel(io_mode, qup->base + QUP_IO_MODE); 989 } 990 991 static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk) 992 { 993 blk->tx_fifo_free = 0; 994 blk->fifo_available = 0; 995 blk->rx_bytes_read = false; 996 } 997 998 static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx) 999 { 1000 struct qup_i2c_block *blk = &qup->blk; 1001 int ret; 1002 1003 qup_i2c_clear_blk_v1(blk); 1004 qup_i2c_conf_v1(qup); 1005 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 1006 if (ret) 1007 return ret; 1008 1009 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); 1010 1011 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); 1012 if (ret) 1013 return ret; 1014 1015 reinit_completion(&qup->xfer); 1016 enable_irq(qup->irq); 1017 if (!blk->is_tx_blk_mode) { 1018 blk->tx_fifo_free = qup->out_fifo_sz; 1019 1020 if (is_rx) 1021 qup_i2c_write_rx_tags_v1(qup); 1022 else 1023 qup_i2c_write_tx_fifo_v1(qup); 1024 } 1025 1026 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 1027 if (ret) 1028 goto err; 1029 1030 ret = qup_i2c_wait_for_complete(qup, qup->msg); 1031 if (ret) 1032 goto err; 1033 1034 ret = qup_i2c_bus_active(qup, ONE_BYTE); 1035 1036 err: 1037 disable_irq(qup->irq); 1038 return ret; 1039 } 1040 1041 static int qup_i2c_write_one(struct qup_i2c_dev *qup) 1042 { 1043 struct i2c_msg *msg = qup->msg; 1044 struct qup_i2c_block *blk = &qup->blk; 1045 1046 qup->pos = 0; 1047 blk->total_tx_len = msg->len + 1; 1048 blk->total_rx_len = 0; 1049 1050 return qup_i2c_conf_xfer_v1(qup, false); 1051 } 1052 1053 static int qup_i2c_read_one(struct qup_i2c_dev *qup) 1054 { 1055 struct qup_i2c_block *blk = &qup->blk; 1056 1057 qup->pos = 0; 1058 blk->total_tx_len = 2; 1059 blk->total_rx_len = qup->msg->len; 1060 1061 return qup_i2c_conf_xfer_v1(qup, true); 1062 } 1063 1064 static int qup_i2c_xfer(struct i2c_adapter *adap, 1065 struct i2c_msg msgs[], 1066 int num) 1067 { 1068 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); 1069 int ret, idx; 1070 1071 ret = pm_runtime_get_sync(qup->dev); 1072 if (ret < 0) 1073 goto out; 1074 1075 qup->bus_err = 0; 1076 qup->qup_err = 0; 1077 1078 writel(1, qup->base + QUP_SW_RESET); 1079 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); 1080 if (ret) 1081 goto out; 1082 1083 /* Configure QUP as I2C mini core */ 1084 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); 1085 1086 for (idx = 0; idx < num; idx++) { 1087 if (msgs[idx].len == 0) { 1088 ret = -EINVAL; 1089 goto out; 1090 } 1091 1092 if (qup_i2c_poll_state_i2c_master(qup)) { 1093 ret = -EIO; 1094 goto out; 1095 } 1096 1097 if (qup_i2c_check_msg_len(&msgs[idx])) { 1098 ret = -EINVAL; 1099 goto out; 1100 } 1101 1102 qup->msg = &msgs[idx]; 1103 if (msgs[idx].flags & I2C_M_RD) 1104 ret = qup_i2c_read_one(qup); 1105 else 1106 ret = qup_i2c_write_one(qup); 1107 1108 if (ret) 1109 break; 1110 1111 ret = qup_i2c_change_state(qup, QUP_RESET_STATE); 1112 if (ret) 1113 break; 1114 } 1115 1116 if (ret == 0) 1117 ret = num; 1118 out: 1119 1120 pm_runtime_mark_last_busy(qup->dev); 1121 pm_runtime_put_autosuspend(qup->dev); 1122 1123 return ret; 1124 } 1125 1126 /* 1127 * Configure registers related with reconfiguration during run and call it 1128 * before each i2c sub transfer. 1129 */ 1130 static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup) 1131 { 1132 struct qup_i2c_block *blk = &qup->blk; 1133 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2; 1134 1135 if (blk->is_tx_blk_mode) 1136 writel(qup->config_run | blk->total_tx_len, 1137 qup->base + QUP_MX_OUTPUT_CNT); 1138 else 1139 writel(qup->config_run | blk->total_tx_len, 1140 qup->base + QUP_MX_WRITE_CNT); 1141 1142 if (blk->total_rx_len) { 1143 if (blk->is_rx_blk_mode) 1144 writel(qup->config_run | blk->total_rx_len, 1145 qup->base + QUP_MX_INPUT_CNT); 1146 else 1147 writel(qup->config_run | blk->total_rx_len, 1148 qup->base + QUP_MX_READ_CNT); 1149 } else { 1150 qup_config |= QUP_NO_INPUT; 1151 } 1152 1153 writel(qup_config, qup->base + QUP_CONFIG); 1154 } 1155 1156 /* 1157 * Configure registers related with transfer mode (FIFO/Block) 1158 * before starting of i2c transfer. It will be called only once in 1159 * QUP RESET state. 1160 */ 1161 static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup) 1162 { 1163 struct qup_i2c_block *blk = &qup->blk; 1164 u32 io_mode = QUP_REPACK_EN; 1165 1166 if (blk->is_tx_blk_mode) { 1167 io_mode |= QUP_OUTPUT_BLK_MODE; 1168 writel(0, qup->base + QUP_MX_WRITE_CNT); 1169 } else { 1170 writel(0, qup->base + QUP_MX_OUTPUT_CNT); 1171 } 1172 1173 if (blk->is_rx_blk_mode) { 1174 io_mode |= QUP_INPUT_BLK_MODE; 1175 writel(0, qup->base + QUP_MX_READ_CNT); 1176 } else { 1177 writel(0, qup->base + QUP_MX_INPUT_CNT); 1178 } 1179 1180 writel(io_mode, qup->base + QUP_IO_MODE); 1181 } 1182 1183 /* Clear required variables before starting of any QUP v2 sub transfer. */ 1184 static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk) 1185 { 1186 blk->send_last_word = false; 1187 blk->tx_tags_sent = false; 1188 blk->tx_fifo_data = 0; 1189 blk->tx_fifo_data_pos = 0; 1190 blk->tx_fifo_free = 0; 1191 1192 blk->rx_tags_fetched = false; 1193 blk->rx_bytes_read = false; 1194 blk->rx_fifo_data = 0; 1195 blk->rx_fifo_data_pos = 0; 1196 blk->fifo_available = 0; 1197 } 1198 1199 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */ 1200 static void qup_i2c_recv_data(struct qup_i2c_dev *qup) 1201 { 1202 struct qup_i2c_block *blk = &qup->blk; 1203 int j; 1204 1205 for (j = blk->rx_fifo_data_pos; 1206 blk->cur_blk_len && blk->fifo_available; 1207 blk->cur_blk_len--, blk->fifo_available--) { 1208 if (j == 0) 1209 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); 1210 1211 *(blk->cur_data++) = blk->rx_fifo_data; 1212 blk->rx_fifo_data >>= 8; 1213 1214 if (j == 3) 1215 j = 0; 1216 else 1217 j++; 1218 } 1219 1220 blk->rx_fifo_data_pos = j; 1221 } 1222 1223 /* Receive tags for read message in QUP v2 i2c transfer. */ 1224 static void qup_i2c_recv_tags(struct qup_i2c_dev *qup) 1225 { 1226 struct qup_i2c_block *blk = &qup->blk; 1227 1228 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); 1229 blk->rx_fifo_data >>= blk->rx_tag_len * 8; 1230 blk->rx_fifo_data_pos = blk->rx_tag_len; 1231 blk->fifo_available -= blk->rx_tag_len; 1232 } 1233 1234 /* 1235 * Read the data and tags from RX FIFO. Since in read case, the tags will be 1236 * preceded by received data bytes so 1237 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive 1238 * all tag bytes and discard that. 1239 * 2. Read the data from RX FIFO. When all the data bytes have been read then 1240 * set rx_bytes_read to true. 1241 */ 1242 static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup) 1243 { 1244 struct qup_i2c_block *blk = &qup->blk; 1245 1246 if (!blk->rx_tags_fetched) { 1247 qup_i2c_recv_tags(qup); 1248 blk->rx_tags_fetched = true; 1249 } 1250 1251 qup_i2c_recv_data(qup); 1252 if (!blk->cur_blk_len) 1253 blk->rx_bytes_read = true; 1254 } 1255 1256 /* 1257 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO 1258 * write works on word basis (4 bytes). Append new data byte write for TX FIFO 1259 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present. 1260 */ 1261 static void 1262 qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len) 1263 { 1264 struct qup_i2c_block *blk = &qup->blk; 1265 unsigned int j; 1266 1267 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free; 1268 (*len)--, blk->tx_fifo_free--) { 1269 blk->tx_fifo_data |= *(*data)++ << (j * 8); 1270 if (j == 3) { 1271 writel(blk->tx_fifo_data, 1272 qup->base + QUP_OUT_FIFO_BASE); 1273 blk->tx_fifo_data = 0x0; 1274 j = 0; 1275 } else { 1276 j++; 1277 } 1278 } 1279 1280 blk->tx_fifo_data_pos = j; 1281 } 1282 1283 /* Transfer tags for read message in QUP v2 i2c transfer. */ 1284 static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup) 1285 { 1286 struct qup_i2c_block *blk = &qup->blk; 1287 1288 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); 1289 if (blk->tx_fifo_data_pos) 1290 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); 1291 } 1292 1293 /* 1294 * Write the data and tags in TX FIFO. Since in write case, both tags and data 1295 * need to be written and QUP write tags can have maximum 256 data length, so 1296 * 1297 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the 1298 * tags to TX FIFO and set tx_tags_sent to true. 1299 * 2. Check if send_last_word is true. It will be set when last few data bytes 1300 * (less than 4 bytes) are reamining to be written in FIFO because of no FIFO 1301 * space. All this data bytes are available in tx_fifo_data so write this 1302 * in FIFO. 1303 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero 1304 * then more data is pending otherwise following 3 cases can be possible 1305 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block 1306 * have been written in TX FIFO so nothing else is required. 1307 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data 1308 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write 1309 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free 1310 * will be always greater than or equal to 4 bytes. 1311 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4 1312 * bytes) are copied to tx_fifo_data but couldn't be sent because of 1313 * FIFO full so make send_last_word true. 1314 */ 1315 static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup) 1316 { 1317 struct qup_i2c_block *blk = &qup->blk; 1318 1319 if (!blk->tx_tags_sent) { 1320 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, 1321 &blk->tx_tag_len); 1322 blk->tx_tags_sent = true; 1323 } 1324 1325 if (blk->send_last_word) 1326 goto send_last_word; 1327 1328 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); 1329 if (!blk->cur_blk_len) { 1330 if (!blk->tx_fifo_data_pos) 1331 return; 1332 1333 if (blk->tx_fifo_free) 1334 goto send_last_word; 1335 1336 blk->send_last_word = true; 1337 } 1338 1339 return; 1340 1341 send_last_word: 1342 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); 1343 } 1344 1345 /* 1346 * Main transfer function which read or write i2c data. 1347 * The QUP v2 supports reconfiguration during run in which multiple i2c sub 1348 * transfers can be scheduled. 1349 */ 1350 static int 1351 qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first, 1352 bool change_pause_state) 1353 { 1354 struct qup_i2c_block *blk = &qup->blk; 1355 struct i2c_msg *msg = qup->msg; 1356 int ret; 1357 1358 /* 1359 * Check if its SMBus Block read for which the top level read will be 1360 * done into 2 QUP reads. One with message length 1 while other one is 1361 * with actual length. 1362 */ 1363 if (qup_i2c_check_msg_len(msg)) { 1364 if (qup->is_smbus_read) { 1365 /* 1366 * If the message length is already read in 1367 * the first byte of the buffer, account for 1368 * that by setting the offset 1369 */ 1370 blk->cur_data += 1; 1371 is_first = false; 1372 } else { 1373 change_pause_state = false; 1374 } 1375 } 1376 1377 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; 1378 1379 qup_i2c_clear_blk_v2(blk); 1380 qup_i2c_conf_count_v2(qup); 1381 1382 /* If it is first sub transfer, then configure i2c bus clocks */ 1383 if (is_first) { 1384 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 1385 if (ret) 1386 return ret; 1387 1388 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); 1389 1390 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); 1391 if (ret) 1392 return ret; 1393 } 1394 1395 reinit_completion(&qup->xfer); 1396 enable_irq(qup->irq); 1397 /* 1398 * In FIFO mode, tx FIFO can be written directly while in block mode the 1399 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt 1400 */ 1401 if (!blk->is_tx_blk_mode) { 1402 blk->tx_fifo_free = qup->out_fifo_sz; 1403 1404 if (is_rx) 1405 qup_i2c_write_rx_tags_v2(qup); 1406 else 1407 qup_i2c_write_tx_fifo_v2(qup); 1408 } 1409 1410 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 1411 if (ret) 1412 goto err; 1413 1414 ret = qup_i2c_wait_for_complete(qup, msg); 1415 if (ret) 1416 goto err; 1417 1418 /* Move to pause state for all the transfers, except last one */ 1419 if (change_pause_state) { 1420 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); 1421 if (ret) 1422 goto err; 1423 } 1424 1425 err: 1426 disable_irq(qup->irq); 1427 return ret; 1428 } 1429 1430 /* 1431 * Transfer one read/write message in i2c transfer. It splits the message into 1432 * multiple of blk_xfer_limit data length blocks and schedule each 1433 * QUP block individually. 1434 */ 1435 static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx) 1436 { 1437 int ret = 0; 1438 unsigned int data_len, i; 1439 struct i2c_msg *msg = qup->msg; 1440 struct qup_i2c_block *blk = &qup->blk; 1441 u8 *msg_buf = msg->buf; 1442 1443 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; 1444 qup_i2c_set_blk_data(qup, msg); 1445 1446 for (i = 0; i < blk->count; i++) { 1447 data_len = qup_i2c_get_data_len(qup); 1448 blk->pos = i; 1449 blk->cur_tx_tags = blk->tags; 1450 blk->cur_blk_len = data_len; 1451 blk->tx_tag_len = 1452 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); 1453 1454 blk->cur_data = msg_buf; 1455 1456 if (is_rx) { 1457 blk->total_tx_len = blk->tx_tag_len; 1458 blk->rx_tag_len = 2; 1459 blk->total_rx_len = blk->rx_tag_len + data_len; 1460 } else { 1461 blk->total_tx_len = blk->tx_tag_len + data_len; 1462 blk->total_rx_len = 0; 1463 } 1464 1465 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i, 1466 !qup->is_last || i < blk->count - 1); 1467 if (ret) 1468 return ret; 1469 1470 /* Handle SMBus block read length */ 1471 if (qup_i2c_check_msg_len(msg) && msg->len == 1 && 1472 !qup->is_smbus_read) { 1473 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) 1474 return -EPROTO; 1475 1476 msg->len = msg->buf[0]; 1477 qup->is_smbus_read = true; 1478 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true); 1479 qup->is_smbus_read = false; 1480 if (ret) 1481 return ret; 1482 1483 msg->len += 1; 1484 } 1485 1486 msg_buf += data_len; 1487 blk->data_len -= qup->blk_xfer_limit; 1488 } 1489 1490 return ret; 1491 } 1492 1493 /* 1494 * QUP v2 supports 3 modes 1495 * Programmed IO using FIFO mode : Less than FIFO size 1496 * Programmed IO using Block mode : Greater than FIFO size 1497 * DMA using BAM : Appropriate for any transaction size but the address should 1498 * be DMA applicable 1499 * 1500 * This function determines the mode which will be used for this transfer. An 1501 * i2c transfer contains multiple message. Following are the rules to determine 1502 * the mode used. 1503 * 1. Determine complete length, maximum tx and rx length for complete transfer. 1504 * 2. If complete transfer length is greater than fifo size then use the DMA 1505 * mode. 1506 * 3. In FIFO or block mode, tx and rx can operate in different mode so check 1507 * for maximum tx and rx length to determine mode. 1508 */ 1509 static int 1510 qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup, 1511 struct i2c_msg msgs[], int num) 1512 { 1513 int idx; 1514 bool no_dma = false; 1515 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0; 1516 1517 /* All i2c_msgs should be transferred using either dma or cpu */ 1518 for (idx = 0; idx < num; idx++) { 1519 if (msgs[idx].len == 0) 1520 return -EINVAL; 1521 1522 if (msgs[idx].flags & I2C_M_RD) 1523 max_rx_len = max_t(unsigned int, max_rx_len, 1524 msgs[idx].len); 1525 else 1526 max_tx_len = max_t(unsigned int, max_tx_len, 1527 msgs[idx].len); 1528 1529 if (is_vmalloc_addr(msgs[idx].buf)) 1530 no_dma = true; 1531 1532 total_len += msgs[idx].len; 1533 } 1534 1535 if (!no_dma && qup->is_dma && 1536 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { 1537 qup->use_dma = true; 1538 } else { 1539 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - 1540 QUP_MAX_TAGS_LEN ? true : false; 1541 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - 1542 READ_RX_TAGS_LEN ? true : false; 1543 } 1544 1545 return 0; 1546 } 1547 1548 static int qup_i2c_xfer_v2(struct i2c_adapter *adap, 1549 struct i2c_msg msgs[], 1550 int num) 1551 { 1552 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); 1553 int ret, idx = 0; 1554 1555 qup->bus_err = 0; 1556 qup->qup_err = 0; 1557 1558 ret = pm_runtime_get_sync(qup->dev); 1559 if (ret < 0) 1560 goto out; 1561 1562 ret = qup_i2c_determine_mode_v2(qup, msgs, num); 1563 if (ret) 1564 goto out; 1565 1566 writel(1, qup->base + QUP_SW_RESET); 1567 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); 1568 if (ret) 1569 goto out; 1570 1571 /* Configure QUP as I2C mini core */ 1572 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); 1573 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); 1574 1575 if (qup_i2c_poll_state_i2c_master(qup)) { 1576 ret = -EIO; 1577 goto out; 1578 } 1579 1580 if (qup->use_dma) { 1581 reinit_completion(&qup->xfer); 1582 ret = qup_i2c_bam_xfer(adap, &msgs[0], num); 1583 qup->use_dma = false; 1584 } else { 1585 qup_i2c_conf_mode_v2(qup); 1586 1587 for (idx = 0; idx < num; idx++) { 1588 qup->msg = &msgs[idx]; 1589 qup->is_last = idx == (num - 1); 1590 1591 ret = qup_i2c_xfer_v2_msg(qup, idx, 1592 !!(msgs[idx].flags & I2C_M_RD)); 1593 if (ret) 1594 break; 1595 } 1596 qup->msg = NULL; 1597 } 1598 1599 if (!ret) 1600 ret = qup_i2c_bus_active(qup, ONE_BYTE); 1601 1602 if (!ret) 1603 qup_i2c_change_state(qup, QUP_RESET_STATE); 1604 1605 if (ret == 0) 1606 ret = num; 1607 out: 1608 pm_runtime_mark_last_busy(qup->dev); 1609 pm_runtime_put_autosuspend(qup->dev); 1610 1611 return ret; 1612 } 1613 1614 static u32 qup_i2c_func(struct i2c_adapter *adap) 1615 { 1616 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1617 } 1618 1619 static const struct i2c_algorithm qup_i2c_algo = { 1620 .master_xfer = qup_i2c_xfer, 1621 .functionality = qup_i2c_func, 1622 }; 1623 1624 static const struct i2c_algorithm qup_i2c_algo_v2 = { 1625 .master_xfer = qup_i2c_xfer_v2, 1626 .functionality = qup_i2c_func, 1627 }; 1628 1629 /* 1630 * The QUP block will issue a NACK and STOP on the bus when reaching 1631 * the end of the read, the length of the read is specified as one byte 1632 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes. 1633 */ 1634 static const struct i2c_adapter_quirks qup_i2c_quirks = { 1635 .max_read_len = QUP_READ_LIMIT, 1636 }; 1637 1638 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup) 1639 { 1640 clk_prepare_enable(qup->clk); 1641 clk_prepare_enable(qup->pclk); 1642 } 1643 1644 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup) 1645 { 1646 u32 config; 1647 1648 qup_i2c_change_state(qup, QUP_RESET_STATE); 1649 clk_disable_unprepare(qup->clk); 1650 config = readl(qup->base + QUP_CONFIG); 1651 config |= QUP_CLOCK_AUTO_GATE; 1652 writel(config, qup->base + QUP_CONFIG); 1653 clk_disable_unprepare(qup->pclk); 1654 } 1655 1656 #if IS_ENABLED(CONFIG_ACPI) 1657 static const struct acpi_device_id qup_i2c_acpi_match[] = { 1658 { "QCOM8010"}, 1659 { }, 1660 }; 1661 MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match); 1662 #endif 1663 1664 static int qup_i2c_probe(struct platform_device *pdev) 1665 { 1666 static const int blk_sizes[] = {4, 16, 32}; 1667 struct qup_i2c_dev *qup; 1668 unsigned long one_bit_t; 1669 struct resource *res; 1670 u32 io_mode, hw_ver, size; 1671 int ret, fs_div, hs_div; 1672 u32 src_clk_freq = DEFAULT_SRC_CLK; 1673 u32 clk_freq = DEFAULT_CLK_FREQ; 1674 int blocks; 1675 bool is_qup_v1; 1676 1677 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); 1678 if (!qup) 1679 return -ENOMEM; 1680 1681 qup->dev = &pdev->dev; 1682 init_completion(&qup->xfer); 1683 platform_set_drvdata(pdev, qup); 1684 1685 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); 1686 if (ret) { 1687 dev_notice(qup->dev, "using default clock-frequency %d", 1688 DEFAULT_CLK_FREQ); 1689 } 1690 1691 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) { 1692 qup->adap.algo = &qup_i2c_algo; 1693 qup->adap.quirks = &qup_i2c_quirks; 1694 is_qup_v1 = true; 1695 } else { 1696 qup->adap.algo = &qup_i2c_algo_v2; 1697 is_qup_v1 = false; 1698 if (acpi_match_device(qup_i2c_acpi_match, qup->dev)) 1699 goto nodma; 1700 else 1701 ret = qup_i2c_req_dma(qup); 1702 1703 if (ret == -EPROBE_DEFER) 1704 goto fail_dma; 1705 else if (ret != 0) 1706 goto nodma; 1707 1708 qup->max_xfer_sg_len = (MX_BLOCKS << 1); 1709 blocks = (MX_DMA_BLOCKS << 1) + 1; 1710 qup->btx.sg = devm_kzalloc(&pdev->dev, 1711 sizeof(*qup->btx.sg) * blocks, 1712 GFP_KERNEL); 1713 if (!qup->btx.sg) { 1714 ret = -ENOMEM; 1715 goto fail_dma; 1716 } 1717 sg_init_table(qup->btx.sg, blocks); 1718 1719 qup->brx.sg = devm_kzalloc(&pdev->dev, 1720 sizeof(*qup->brx.sg) * blocks, 1721 GFP_KERNEL); 1722 if (!qup->brx.sg) { 1723 ret = -ENOMEM; 1724 goto fail_dma; 1725 } 1726 sg_init_table(qup->brx.sg, blocks); 1727 1728 /* 2 tag bytes for each block + 5 for start, stop tags */ 1729 size = blocks * 2 + 5; 1730 1731 qup->start_tag.start = devm_kzalloc(&pdev->dev, 1732 size, GFP_KERNEL); 1733 if (!qup->start_tag.start) { 1734 ret = -ENOMEM; 1735 goto fail_dma; 1736 } 1737 1738 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); 1739 if (!qup->brx.tag.start) { 1740 ret = -ENOMEM; 1741 goto fail_dma; 1742 } 1743 1744 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); 1745 if (!qup->btx.tag.start) { 1746 ret = -ENOMEM; 1747 goto fail_dma; 1748 } 1749 qup->is_dma = true; 1750 } 1751 1752 nodma: 1753 /* We support frequencies up to FAST Mode Plus (1MHz) */ 1754 if (!clk_freq || clk_freq > I2C_FAST_MODE_PLUS_FREQ) { 1755 dev_err(qup->dev, "clock frequency not supported %d\n", 1756 clk_freq); 1757 return -EINVAL; 1758 } 1759 1760 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1761 qup->base = devm_ioremap_resource(qup->dev, res); 1762 if (IS_ERR(qup->base)) 1763 return PTR_ERR(qup->base); 1764 1765 qup->irq = platform_get_irq(pdev, 0); 1766 if (qup->irq < 0) { 1767 dev_err(qup->dev, "No IRQ defined\n"); 1768 return qup->irq; 1769 } 1770 1771 if (has_acpi_companion(qup->dev)) { 1772 ret = device_property_read_u32(qup->dev, 1773 "src-clock-hz", &src_clk_freq); 1774 if (ret) { 1775 dev_notice(qup->dev, "using default src-clock-hz %d", 1776 DEFAULT_SRC_CLK); 1777 } 1778 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); 1779 } else { 1780 qup->clk = devm_clk_get(qup->dev, "core"); 1781 if (IS_ERR(qup->clk)) { 1782 dev_err(qup->dev, "Could not get core clock\n"); 1783 return PTR_ERR(qup->clk); 1784 } 1785 1786 qup->pclk = devm_clk_get(qup->dev, "iface"); 1787 if (IS_ERR(qup->pclk)) { 1788 dev_err(qup->dev, "Could not get iface clock\n"); 1789 return PTR_ERR(qup->pclk); 1790 } 1791 qup_i2c_enable_clocks(qup); 1792 src_clk_freq = clk_get_rate(qup->clk); 1793 } 1794 1795 /* 1796 * Bootloaders might leave a pending interrupt on certain QUP's, 1797 * so we reset the core before registering for interrupts. 1798 */ 1799 writel(1, qup->base + QUP_SW_RESET); 1800 ret = qup_i2c_poll_state_valid(qup); 1801 if (ret) 1802 goto fail; 1803 1804 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, 1805 IRQF_TRIGGER_HIGH, "i2c_qup", qup); 1806 if (ret) { 1807 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); 1808 goto fail; 1809 } 1810 disable_irq(qup->irq); 1811 1812 hw_ver = readl(qup->base + QUP_HW_VERSION); 1813 dev_dbg(qup->dev, "Revision %x\n", hw_ver); 1814 1815 io_mode = readl(qup->base + QUP_IO_MODE); 1816 1817 /* 1818 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag' 1819 * associated with each byte written/received 1820 */ 1821 size = QUP_OUTPUT_BLOCK_SIZE(io_mode); 1822 if (size >= ARRAY_SIZE(blk_sizes)) { 1823 ret = -EIO; 1824 goto fail; 1825 } 1826 qup->out_blk_sz = blk_sizes[size]; 1827 1828 size = QUP_INPUT_BLOCK_SIZE(io_mode); 1829 if (size >= ARRAY_SIZE(blk_sizes)) { 1830 ret = -EIO; 1831 goto fail; 1832 } 1833 qup->in_blk_sz = blk_sizes[size]; 1834 1835 if (is_qup_v1) { 1836 /* 1837 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a 1838 * single transfer but the block size is in bytes so divide the 1839 * in_blk_sz and out_blk_sz by 2 1840 */ 1841 qup->in_blk_sz /= 2; 1842 qup->out_blk_sz /= 2; 1843 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; 1844 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; 1845 qup->write_rx_tags = qup_i2c_write_rx_tags_v1; 1846 } else { 1847 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; 1848 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; 1849 qup->write_rx_tags = qup_i2c_write_rx_tags_v2; 1850 } 1851 1852 size = QUP_OUTPUT_FIFO_SIZE(io_mode); 1853 qup->out_fifo_sz = qup->out_blk_sz * (2 << size); 1854 1855 size = QUP_INPUT_FIFO_SIZE(io_mode); 1856 qup->in_fifo_sz = qup->in_blk_sz * (2 << size); 1857 1858 hs_div = 3; 1859 if (clk_freq <= I2C_STANDARD_FREQ) { 1860 fs_div = ((src_clk_freq / clk_freq) / 2) - 3; 1861 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); 1862 } else { 1863 /* 33%/66% duty cycle */ 1864 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; 1865 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); 1866 } 1867 1868 /* 1869 * Time it takes for a byte to be clocked out on the bus. 1870 * Each byte takes 9 clock cycles (8 bits + 1 ack). 1871 */ 1872 one_bit_t = (USEC_PER_SEC / clk_freq) + 1; 1873 qup->one_byte_t = one_bit_t * 9; 1874 qup->xfer_timeout = TOUT_MIN * HZ + 1875 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); 1876 1877 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", 1878 qup->in_blk_sz, qup->in_fifo_sz, 1879 qup->out_blk_sz, qup->out_fifo_sz); 1880 1881 i2c_set_adapdata(&qup->adap, qup); 1882 qup->adap.dev.parent = qup->dev; 1883 qup->adap.dev.of_node = pdev->dev.of_node; 1884 qup->is_last = true; 1885 1886 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); 1887 1888 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); 1889 pm_runtime_use_autosuspend(qup->dev); 1890 pm_runtime_set_active(qup->dev); 1891 pm_runtime_enable(qup->dev); 1892 1893 ret = i2c_add_adapter(&qup->adap); 1894 if (ret) 1895 goto fail_runtime; 1896 1897 return 0; 1898 1899 fail_runtime: 1900 pm_runtime_disable(qup->dev); 1901 pm_runtime_set_suspended(qup->dev); 1902 fail: 1903 qup_i2c_disable_clocks(qup); 1904 fail_dma: 1905 if (qup->btx.dma) 1906 dma_release_channel(qup->btx.dma); 1907 if (qup->brx.dma) 1908 dma_release_channel(qup->brx.dma); 1909 return ret; 1910 } 1911 1912 static int qup_i2c_remove(struct platform_device *pdev) 1913 { 1914 struct qup_i2c_dev *qup = platform_get_drvdata(pdev); 1915 1916 if (qup->is_dma) { 1917 dma_release_channel(qup->btx.dma); 1918 dma_release_channel(qup->brx.dma); 1919 } 1920 1921 disable_irq(qup->irq); 1922 qup_i2c_disable_clocks(qup); 1923 i2c_del_adapter(&qup->adap); 1924 pm_runtime_disable(qup->dev); 1925 pm_runtime_set_suspended(qup->dev); 1926 return 0; 1927 } 1928 1929 #ifdef CONFIG_PM 1930 static int qup_i2c_pm_suspend_runtime(struct device *device) 1931 { 1932 struct qup_i2c_dev *qup = dev_get_drvdata(device); 1933 1934 dev_dbg(device, "pm_runtime: suspending...\n"); 1935 qup_i2c_disable_clocks(qup); 1936 return 0; 1937 } 1938 1939 static int qup_i2c_pm_resume_runtime(struct device *device) 1940 { 1941 struct qup_i2c_dev *qup = dev_get_drvdata(device); 1942 1943 dev_dbg(device, "pm_runtime: resuming...\n"); 1944 qup_i2c_enable_clocks(qup); 1945 return 0; 1946 } 1947 #endif 1948 1949 #ifdef CONFIG_PM_SLEEP 1950 static int qup_i2c_suspend(struct device *device) 1951 { 1952 if (!pm_runtime_suspended(device)) 1953 return qup_i2c_pm_suspend_runtime(device); 1954 return 0; 1955 } 1956 1957 static int qup_i2c_resume(struct device *device) 1958 { 1959 qup_i2c_pm_resume_runtime(device); 1960 pm_runtime_mark_last_busy(device); 1961 pm_request_autosuspend(device); 1962 return 0; 1963 } 1964 #endif 1965 1966 static const struct dev_pm_ops qup_i2c_qup_pm_ops = { 1967 SET_SYSTEM_SLEEP_PM_OPS( 1968 qup_i2c_suspend, 1969 qup_i2c_resume) 1970 SET_RUNTIME_PM_OPS( 1971 qup_i2c_pm_suspend_runtime, 1972 qup_i2c_pm_resume_runtime, 1973 NULL) 1974 }; 1975 1976 static const struct of_device_id qup_i2c_dt_match[] = { 1977 { .compatible = "qcom,i2c-qup-v1.1.1" }, 1978 { .compatible = "qcom,i2c-qup-v2.1.1" }, 1979 { .compatible = "qcom,i2c-qup-v2.2.1" }, 1980 {} 1981 }; 1982 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match); 1983 1984 static struct platform_driver qup_i2c_driver = { 1985 .probe = qup_i2c_probe, 1986 .remove = qup_i2c_remove, 1987 .driver = { 1988 .name = "i2c_qup", 1989 .pm = &qup_i2c_qup_pm_ops, 1990 .of_match_table = qup_i2c_dt_match, 1991 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match), 1992 }, 1993 }; 1994 1995 module_platform_driver(qup_i2c_driver); 1996 1997 MODULE_LICENSE("GPL v2"); 1998 MODULE_ALIAS("platform:i2c_qup"); 1999