1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/dmaengine.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/dma/qcom-gpi-dma.h> 9 #include <linux/err.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/qcom-geni-se.h> 18 #include <linux/spinlock.h> 19 20 #define SE_I2C_TX_TRANS_LEN 0x26c 21 #define SE_I2C_RX_TRANS_LEN 0x270 22 #define SE_I2C_SCL_COUNTERS 0x278 23 24 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ 25 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) 26 #define SE_I2C_ABORT BIT(1) 27 28 /* M_CMD OP codes for I2C */ 29 #define I2C_WRITE 0x1 30 #define I2C_READ 0x2 31 #define I2C_WRITE_READ 0x3 32 #define I2C_ADDR_ONLY 0x4 33 #define I2C_BUS_CLEAR 0x6 34 #define I2C_STOP_ON_BUS 0x7 35 /* M_CMD params for I2C */ 36 #define PRE_CMD_DELAY BIT(0) 37 #define TIMESTAMP_BEFORE BIT(1) 38 #define STOP_STRETCH BIT(2) 39 #define TIMESTAMP_AFTER BIT(3) 40 #define POST_COMMAND_DELAY BIT(4) 41 #define IGNORE_ADD_NACK BIT(6) 42 #define READ_FINISHED_WITH_ACK BIT(7) 43 #define BYPASS_ADDR_PHASE BIT(8) 44 #define SLV_ADDR_MSK GENMASK(15, 9) 45 #define SLV_ADDR_SHFT 9 46 /* I2C SCL COUNTER fields */ 47 #define HIGH_COUNTER_MSK GENMASK(29, 20) 48 #define HIGH_COUNTER_SHFT 20 49 #define LOW_COUNTER_MSK GENMASK(19, 10) 50 #define LOW_COUNTER_SHFT 10 51 #define CYCLE_COUNTER_MSK GENMASK(9, 0) 52 53 #define I2C_PACK_TX BIT(0) 54 #define I2C_PACK_RX BIT(1) 55 56 enum geni_i2c_err_code { 57 GP_IRQ0, 58 NACK, 59 GP_IRQ2, 60 BUS_PROTO, 61 ARB_LOST, 62 GP_IRQ5, 63 GENI_OVERRUN, 64 GENI_ILLEGAL_CMD, 65 GENI_ABORT_DONE, 66 GENI_TIMEOUT, 67 }; 68 69 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ 70 << 5) 71 72 #define I2C_AUTO_SUSPEND_DELAY 250 73 #define KHZ(freq) (1000 * freq) 74 #define PACKING_BYTES_PW 4 75 76 #define ABORT_TIMEOUT HZ 77 #define XFER_TIMEOUT HZ 78 #define RST_TIMEOUT HZ 79 80 struct geni_i2c_dev { 81 struct geni_se se; 82 u32 tx_wm; 83 int irq; 84 int err; 85 struct i2c_adapter adap; 86 struct completion done; 87 struct i2c_msg *cur; 88 int cur_wr; 89 int cur_rd; 90 spinlock_t lock; 91 u32 clk_freq_out; 92 const struct geni_i2c_clk_fld *clk_fld; 93 int suspended; 94 void *dma_buf; 95 size_t xfer_len; 96 dma_addr_t dma_addr; 97 struct dma_chan *tx_c; 98 struct dma_chan *rx_c; 99 bool gpi_mode; 100 }; 101 102 struct geni_i2c_err_log { 103 int err; 104 const char *msg; 105 }; 106 107 static const struct geni_i2c_err_log gi2c_log[] = { 108 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, 109 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"}, 110 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, 111 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"}, 112 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, 113 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, 114 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, 115 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, 116 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, 117 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, 118 }; 119 120 struct geni_i2c_clk_fld { 121 u32 clk_freq_out; 122 u8 clk_div; 123 u8 t_high_cnt; 124 u8 t_low_cnt; 125 u8 t_cycle_cnt; 126 }; 127 128 /* 129 * Hardware uses the underlying formula to calculate time periods of 130 * SCL clock cycle. Firmware uses some additional cycles excluded from the 131 * below formula and it is confirmed that the time periods are within 132 * specification limits. 133 * 134 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock 135 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock 136 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock 137 * clk_freq_out = t / t_cycle 138 * source_clock = 19.2 MHz 139 */ 140 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = { 141 {KHZ(100), 7, 10, 11, 26}, 142 {KHZ(400), 2, 5, 12, 24}, 143 {KHZ(1000), 1, 3, 9, 18}, 144 }; 145 146 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) 147 { 148 int i; 149 const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map; 150 151 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) { 152 if (itr->clk_freq_out == gi2c->clk_freq_out) { 153 gi2c->clk_fld = itr; 154 return 0; 155 } 156 } 157 return -EINVAL; 158 } 159 160 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) 161 { 162 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 163 u32 val; 164 165 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); 166 167 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; 168 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 169 170 val = itr->t_high_cnt << HIGH_COUNTER_SHFT; 171 val |= itr->t_low_cnt << LOW_COUNTER_SHFT; 172 val |= itr->t_cycle_cnt; 173 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 174 } 175 176 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) 177 { 178 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 179 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 180 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 181 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 182 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 183 u32 rx_st, tx_st; 184 185 if (dma) { 186 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 187 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 188 } else { 189 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); 190 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); 191 } 192 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", 193 dma, tx_st, rx_st, m_stat); 194 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", 195 m_cmd, geni_s, geni_ios); 196 } 197 198 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) 199 { 200 if (!gi2c->err) 201 gi2c->err = gi2c_log[err].err; 202 if (gi2c->cur) 203 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", 204 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); 205 206 if (err != NACK && err != GENI_ABORT_DONE) { 207 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 208 geni_i2c_err_misc(gi2c); 209 } 210 } 211 212 static irqreturn_t geni_i2c_irq(int irq, void *dev) 213 { 214 struct geni_i2c_dev *gi2c = dev; 215 void __iomem *base = gi2c->se.base; 216 int j, p; 217 u32 m_stat; 218 u32 rx_st; 219 u32 dm_tx_st; 220 u32 dm_rx_st; 221 u32 dma; 222 u32 val; 223 struct i2c_msg *cur; 224 225 spin_lock(&gi2c->lock); 226 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); 227 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); 228 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); 229 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); 230 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 231 cur = gi2c->cur; 232 233 if (!cur || 234 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || 235 dm_rx_st & (DM_I2C_CB_ERR)) { 236 if (m_stat & M_GP_IRQ_1_EN) 237 geni_i2c_err(gi2c, NACK); 238 if (m_stat & M_GP_IRQ_3_EN) 239 geni_i2c_err(gi2c, BUS_PROTO); 240 if (m_stat & M_GP_IRQ_4_EN) 241 geni_i2c_err(gi2c, ARB_LOST); 242 if (m_stat & M_CMD_OVERRUN_EN) 243 geni_i2c_err(gi2c, GENI_OVERRUN); 244 if (m_stat & M_ILLEGAL_CMD_EN) 245 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); 246 if (m_stat & M_CMD_ABORT_EN) 247 geni_i2c_err(gi2c, GENI_ABORT_DONE); 248 if (m_stat & M_GP_IRQ_0_EN) 249 geni_i2c_err(gi2c, GP_IRQ0); 250 251 /* Disable the TX Watermark interrupt to stop TX */ 252 if (!dma) 253 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 254 } else if (dma) { 255 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", 256 dm_tx_st, dm_rx_st); 257 } else if (cur->flags & I2C_M_RD && 258 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { 259 u32 rxcnt = rx_st & RX_FIFO_WC_MSK; 260 261 for (j = 0; j < rxcnt; j++) { 262 p = 0; 263 val = readl_relaxed(base + SE_GENI_RX_FIFOn); 264 while (gi2c->cur_rd < cur->len && p < sizeof(val)) { 265 cur->buf[gi2c->cur_rd++] = val & 0xff; 266 val >>= 8; 267 p++; 268 } 269 if (gi2c->cur_rd == cur->len) 270 break; 271 } 272 } else if (!(cur->flags & I2C_M_RD) && 273 m_stat & M_TX_FIFO_WATERMARK_EN) { 274 for (j = 0; j < gi2c->tx_wm; j++) { 275 u32 temp; 276 277 val = 0; 278 p = 0; 279 while (gi2c->cur_wr < cur->len && p < sizeof(val)) { 280 temp = cur->buf[gi2c->cur_wr++]; 281 val |= temp << (p * 8); 282 p++; 283 } 284 writel_relaxed(val, base + SE_GENI_TX_FIFOn); 285 /* TX Complete, Disable the TX Watermark interrupt */ 286 if (gi2c->cur_wr == cur->len) { 287 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 288 break; 289 } 290 } 291 } 292 293 if (m_stat) 294 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); 295 296 if (dma && dm_tx_st) 297 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); 298 if (dma && dm_rx_st) 299 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); 300 301 /* if this is err with done-bit not set, handle that through timeout. */ 302 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN || 303 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE || 304 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE) 305 complete(&gi2c->done); 306 307 spin_unlock(&gi2c->lock); 308 309 return IRQ_HANDLED; 310 } 311 312 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) 313 { 314 u32 val; 315 unsigned long time_left = ABORT_TIMEOUT; 316 unsigned long flags; 317 318 spin_lock_irqsave(&gi2c->lock, flags); 319 geni_i2c_err(gi2c, GENI_TIMEOUT); 320 gi2c->cur = NULL; 321 geni_se_abort_m_cmd(&gi2c->se); 322 spin_unlock_irqrestore(&gi2c->lock, flags); 323 do { 324 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 325 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 326 } while (!(val & M_CMD_ABORT_EN) && time_left); 327 328 if (!(val & M_CMD_ABORT_EN)) 329 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); 330 } 331 332 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) 333 { 334 u32 val; 335 unsigned long time_left = RST_TIMEOUT; 336 337 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); 338 do { 339 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 340 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 341 } while (!(val & RX_RESET_DONE) && time_left); 342 343 if (!(val & RX_RESET_DONE)) 344 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); 345 } 346 347 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) 348 { 349 u32 val; 350 unsigned long time_left = RST_TIMEOUT; 351 352 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); 353 do { 354 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 355 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 356 } while (!(val & TX_RESET_DONE) && time_left); 357 358 if (!(val & TX_RESET_DONE)) 359 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); 360 } 361 362 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c, 363 struct i2c_msg *cur) 364 { 365 gi2c->cur_rd = 0; 366 if (gi2c->dma_buf) { 367 if (gi2c->err) 368 geni_i2c_rx_fsm_rst(gi2c); 369 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 370 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 371 } 372 } 373 374 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c, 375 struct i2c_msg *cur) 376 { 377 gi2c->cur_wr = 0; 378 if (gi2c->dma_buf) { 379 if (gi2c->err) 380 geni_i2c_tx_fsm_rst(gi2c); 381 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 382 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 383 } 384 } 385 386 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 387 u32 m_param) 388 { 389 dma_addr_t rx_dma = 0; 390 unsigned long time_left; 391 void *dma_buf; 392 struct geni_se *se = &gi2c->se; 393 size_t len = msg->len; 394 struct i2c_msg *cur; 395 396 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 397 if (dma_buf) 398 geni_se_select_mode(se, GENI_SE_DMA); 399 else 400 geni_se_select_mode(se, GENI_SE_FIFO); 401 402 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 403 geni_se_setup_m_cmd(se, I2C_READ, m_param); 404 405 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 406 geni_se_select_mode(se, GENI_SE_FIFO); 407 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 408 dma_buf = NULL; 409 } else { 410 gi2c->xfer_len = len; 411 gi2c->dma_addr = rx_dma; 412 gi2c->dma_buf = dma_buf; 413 } 414 415 cur = gi2c->cur; 416 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 417 if (!time_left) 418 geni_i2c_abort_xfer(gi2c); 419 420 geni_i2c_rx_msg_cleanup(gi2c, cur); 421 422 return gi2c->err; 423 } 424 425 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 426 u32 m_param) 427 { 428 dma_addr_t tx_dma = 0; 429 unsigned long time_left; 430 void *dma_buf; 431 struct geni_se *se = &gi2c->se; 432 size_t len = msg->len; 433 struct i2c_msg *cur; 434 435 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 436 if (dma_buf) 437 geni_se_select_mode(se, GENI_SE_DMA); 438 else 439 geni_se_select_mode(se, GENI_SE_FIFO); 440 441 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 442 geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 443 444 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 445 geni_se_select_mode(se, GENI_SE_FIFO); 446 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 447 dma_buf = NULL; 448 } else { 449 gi2c->xfer_len = len; 450 gi2c->dma_addr = tx_dma; 451 gi2c->dma_buf = dma_buf; 452 } 453 454 if (!dma_buf) /* Get FIFO IRQ */ 455 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); 456 457 cur = gi2c->cur; 458 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 459 if (!time_left) 460 geni_i2c_abort_xfer(gi2c); 461 462 geni_i2c_tx_msg_cleanup(gi2c, cur); 463 464 return gi2c->err; 465 } 466 467 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result) 468 { 469 struct geni_i2c_dev *gi2c = cb; 470 471 if (result->result != DMA_TRANS_NOERROR) { 472 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); 473 gi2c->err = -EIO; 474 } else if (result->residue) { 475 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); 476 } 477 478 complete(&gi2c->done); 479 } 480 481 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 482 void *tx_buf, dma_addr_t tx_addr, 483 void *rx_buf, dma_addr_t rx_addr) 484 { 485 if (tx_buf) { 486 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); 487 i2c_put_dma_safe_msg_buf(tx_buf, msg, false); 488 } 489 490 if (rx_buf) { 491 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); 492 i2c_put_dma_safe_msg_buf(rx_buf, msg, false); 493 } 494 } 495 496 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 497 struct dma_slave_config *config, dma_addr_t *dma_addr_p, 498 void **buf, unsigned int op, struct dma_chan *dma_chan) 499 { 500 struct gpi_i2c_config *peripheral; 501 unsigned int flags; 502 void *dma_buf; 503 dma_addr_t addr; 504 enum dma_data_direction map_dirn; 505 enum dma_transfer_direction dma_dirn; 506 struct dma_async_tx_descriptor *desc; 507 int ret; 508 509 peripheral = config->peripheral_config; 510 511 dma_buf = i2c_get_dma_safe_msg_buf(msg, 1); 512 if (!dma_buf) 513 return -ENOMEM; 514 515 if (op == I2C_WRITE) 516 map_dirn = DMA_TO_DEVICE; 517 else 518 map_dirn = DMA_FROM_DEVICE; 519 520 addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn); 521 if (dma_mapping_error(gi2c->se.dev->parent, addr)) { 522 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 523 return -ENOMEM; 524 } 525 526 /* set the length as message for rx txn */ 527 peripheral->rx_len = msg->len; 528 peripheral->op = op; 529 530 ret = dmaengine_slave_config(dma_chan, config); 531 if (ret) { 532 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); 533 goto err_config; 534 } 535 536 peripheral->set_config = 0; 537 peripheral->multi_msg = true; 538 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 539 540 if (op == I2C_WRITE) 541 dma_dirn = DMA_MEM_TO_DEV; 542 else 543 dma_dirn = DMA_DEV_TO_MEM; 544 545 desc = dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, flags); 546 if (!desc) { 547 dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); 548 ret = -EIO; 549 goto err_config; 550 } 551 552 desc->callback_result = i2c_gpi_cb_result; 553 desc->callback_param = gi2c; 554 555 dmaengine_submit(desc); 556 *dma_addr_p = addr; 557 558 return 0; 559 560 err_config: 561 dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn); 562 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 563 return ret; 564 } 565 566 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num) 567 { 568 struct dma_slave_config config = {}; 569 struct gpi_i2c_config peripheral = {}; 570 int i, ret = 0, timeout; 571 dma_addr_t tx_addr, rx_addr; 572 void *tx_buf = NULL, *rx_buf = NULL; 573 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 574 575 config.peripheral_config = &peripheral; 576 config.peripheral_size = sizeof(peripheral); 577 578 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX; 579 peripheral.cycle_count = itr->t_cycle_cnt; 580 peripheral.high_count = itr->t_high_cnt; 581 peripheral.low_count = itr->t_low_cnt; 582 peripheral.clk_div = itr->clk_div; 583 peripheral.set_config = 1; 584 peripheral.multi_msg = false; 585 586 for (i = 0; i < num; i++) { 587 gi2c->cur = &msgs[i]; 588 gi2c->err = 0; 589 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len); 590 591 peripheral.stretch = 0; 592 if (i < num - 1) 593 peripheral.stretch = 1; 594 595 peripheral.addr = msgs[i].addr; 596 597 if (msgs[i].flags & I2C_M_RD) { 598 ret = geni_i2c_gpi(gi2c, &msgs[i], &config, 599 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); 600 if (ret) 601 goto err; 602 } 603 604 ret = geni_i2c_gpi(gi2c, &msgs[i], &config, 605 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); 606 if (ret) 607 goto err; 608 609 if (msgs[i].flags & I2C_M_RD) 610 dma_async_issue_pending(gi2c->rx_c); 611 dma_async_issue_pending(gi2c->tx_c); 612 613 timeout = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 614 if (!timeout) { 615 dev_err(gi2c->se.dev, "I2C timeout gpi flags:%d addr:0x%x\n", 616 gi2c->cur->flags, gi2c->cur->addr); 617 gi2c->err = -ETIMEDOUT; 618 goto err; 619 } 620 621 if (gi2c->err) { 622 ret = gi2c->err; 623 goto err; 624 } 625 626 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 627 } 628 629 return num; 630 631 err: 632 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret); 633 dmaengine_terminate_sync(gi2c->rx_c); 634 dmaengine_terminate_sync(gi2c->tx_c); 635 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 636 return ret; 637 } 638 639 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c, 640 struct i2c_msg msgs[], int num) 641 { 642 int i, ret = 0; 643 644 for (i = 0; i < num; i++) { 645 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; 646 647 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); 648 649 gi2c->cur = &msgs[i]; 650 if (msgs[i].flags & I2C_M_RD) 651 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); 652 else 653 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); 654 655 if (ret) 656 return ret; 657 } 658 659 return num; 660 } 661 662 static int geni_i2c_xfer(struct i2c_adapter *adap, 663 struct i2c_msg msgs[], 664 int num) 665 { 666 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); 667 int ret; 668 669 gi2c->err = 0; 670 reinit_completion(&gi2c->done); 671 ret = pm_runtime_get_sync(gi2c->se.dev); 672 if (ret < 0) { 673 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); 674 pm_runtime_put_noidle(gi2c->se.dev); 675 /* Set device in suspended since resume failed */ 676 pm_runtime_set_suspended(gi2c->se.dev); 677 return ret; 678 } 679 680 qcom_geni_i2c_conf(gi2c); 681 682 if (gi2c->gpi_mode) 683 ret = geni_i2c_gpi_xfer(gi2c, msgs, num); 684 else 685 ret = geni_i2c_fifo_xfer(gi2c, msgs, num); 686 687 pm_runtime_mark_last_busy(gi2c->se.dev); 688 pm_runtime_put_autosuspend(gi2c->se.dev); 689 gi2c->cur = NULL; 690 gi2c->err = 0; 691 return num; 692 } 693 694 static u32 geni_i2c_func(struct i2c_adapter *adap) 695 { 696 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 697 } 698 699 static const struct i2c_algorithm geni_i2c_algo = { 700 .master_xfer = geni_i2c_xfer, 701 .functionality = geni_i2c_func, 702 }; 703 704 #ifdef CONFIG_ACPI 705 static const struct acpi_device_id geni_i2c_acpi_match[] = { 706 { "QCOM0220"}, 707 { }, 708 }; 709 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); 710 #endif 711 712 static void release_gpi_dma(struct geni_i2c_dev *gi2c) 713 { 714 if (gi2c->rx_c) 715 dma_release_channel(gi2c->rx_c); 716 717 if (gi2c->tx_c) 718 dma_release_channel(gi2c->tx_c); 719 } 720 721 static int setup_gpi_dma(struct geni_i2c_dev *gi2c) 722 { 723 int ret; 724 725 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA); 726 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx"); 727 if (IS_ERR(gi2c->tx_c)) { 728 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c), 729 "Failed to get tx DMA ch\n"); 730 goto err_tx; 731 } 732 733 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx"); 734 if (IS_ERR(gi2c->rx_c)) { 735 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c), 736 "Failed to get rx DMA ch\n"); 737 goto err_rx; 738 } 739 740 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n"); 741 return 0; 742 743 err_rx: 744 dma_release_channel(gi2c->tx_c); 745 err_tx: 746 return ret; 747 } 748 749 static int geni_i2c_probe(struct platform_device *pdev) 750 { 751 struct geni_i2c_dev *gi2c; 752 struct resource *res; 753 u32 proto, tx_depth, fifo_disable; 754 int ret; 755 struct device *dev = &pdev->dev; 756 757 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); 758 if (!gi2c) 759 return -ENOMEM; 760 761 gi2c->se.dev = dev; 762 gi2c->se.wrapper = dev_get_drvdata(dev->parent); 763 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 764 gi2c->se.base = devm_ioremap_resource(dev, res); 765 if (IS_ERR(gi2c->se.base)) 766 return PTR_ERR(gi2c->se.base); 767 768 gi2c->se.clk = devm_clk_get(dev, "se"); 769 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) 770 return PTR_ERR(gi2c->se.clk); 771 772 ret = device_property_read_u32(dev, "clock-frequency", 773 &gi2c->clk_freq_out); 774 if (ret) { 775 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n"); 776 gi2c->clk_freq_out = KHZ(100); 777 } 778 779 if (has_acpi_companion(dev)) 780 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); 781 782 gi2c->irq = platform_get_irq(pdev, 0); 783 if (gi2c->irq < 0) 784 return gi2c->irq; 785 786 ret = geni_i2c_clk_map_idx(gi2c); 787 if (ret) { 788 dev_err(dev, "Invalid clk frequency %d Hz: %d\n", 789 gi2c->clk_freq_out, ret); 790 return ret; 791 } 792 793 gi2c->adap.algo = &geni_i2c_algo; 794 init_completion(&gi2c->done); 795 spin_lock_init(&gi2c->lock); 796 platform_set_drvdata(pdev, gi2c); 797 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0, 798 dev_name(dev), gi2c); 799 if (ret) { 800 dev_err(dev, "Request_irq failed:%d: err:%d\n", 801 gi2c->irq, ret); 802 return ret; 803 } 804 /* Disable the interrupt so that the system can enter low-power mode */ 805 disable_irq(gi2c->irq); 806 i2c_set_adapdata(&gi2c->adap, gi2c); 807 gi2c->adap.dev.parent = dev; 808 gi2c->adap.dev.of_node = dev->of_node; 809 strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); 810 811 ret = geni_icc_get(&gi2c->se, "qup-memory"); 812 if (ret) 813 return ret; 814 /* 815 * Set the bus quota for core and cpu to a reasonable value for 816 * register access. 817 * Set quota for DDR based on bus speed. 818 */ 819 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 820 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 821 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); 822 823 ret = geni_icc_set_bw(&gi2c->se); 824 if (ret) 825 return ret; 826 827 ret = geni_se_resources_on(&gi2c->se); 828 if (ret) { 829 dev_err(dev, "Error turning on resources %d\n", ret); 830 return ret; 831 } 832 proto = geni_se_read_proto(&gi2c->se); 833 if (proto != GENI_SE_I2C) { 834 dev_err(dev, "Invalid proto %d\n", proto); 835 geni_se_resources_off(&gi2c->se); 836 return -ENXIO; 837 } 838 839 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 840 if (fifo_disable) { 841 /* FIFO is disabled, so we can only use GPI DMA */ 842 gi2c->gpi_mode = true; 843 ret = setup_gpi_dma(gi2c); 844 if (ret) 845 return dev_err_probe(dev, ret, "Failed to setup GPI DMA mode\n"); 846 847 dev_dbg(dev, "Using GPI DMA mode for I2C\n"); 848 } else { 849 gi2c->gpi_mode = false; 850 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); 851 gi2c->tx_wm = tx_depth - 1; 852 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); 853 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, 854 PACKING_BYTES_PW, true, true, true); 855 856 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); 857 } 858 859 ret = geni_se_resources_off(&gi2c->se); 860 if (ret) { 861 dev_err(dev, "Error turning off resources %d\n", ret); 862 goto err_dma; 863 } 864 865 ret = geni_icc_disable(&gi2c->se); 866 if (ret) 867 goto err_dma; 868 869 gi2c->suspended = 1; 870 pm_runtime_set_suspended(gi2c->se.dev); 871 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); 872 pm_runtime_use_autosuspend(gi2c->se.dev); 873 pm_runtime_enable(gi2c->se.dev); 874 875 ret = i2c_add_adapter(&gi2c->adap); 876 if (ret) { 877 dev_err(dev, "Error adding i2c adapter %d\n", ret); 878 pm_runtime_disable(gi2c->se.dev); 879 goto err_dma; 880 } 881 882 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); 883 884 return 0; 885 886 err_dma: 887 release_gpi_dma(gi2c); 888 return ret; 889 } 890 891 static int geni_i2c_remove(struct platform_device *pdev) 892 { 893 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 894 895 i2c_del_adapter(&gi2c->adap); 896 release_gpi_dma(gi2c); 897 pm_runtime_disable(gi2c->se.dev); 898 return 0; 899 } 900 901 static void geni_i2c_shutdown(struct platform_device *pdev) 902 { 903 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 904 905 /* Make client i2c transfers start failing */ 906 i2c_mark_adapter_suspended(&gi2c->adap); 907 } 908 909 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) 910 { 911 int ret; 912 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 913 914 disable_irq(gi2c->irq); 915 ret = geni_se_resources_off(&gi2c->se); 916 if (ret) { 917 enable_irq(gi2c->irq); 918 return ret; 919 920 } else { 921 gi2c->suspended = 1; 922 } 923 924 return geni_icc_disable(&gi2c->se); 925 } 926 927 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) 928 { 929 int ret; 930 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 931 932 ret = geni_icc_enable(&gi2c->se); 933 if (ret) 934 return ret; 935 936 ret = geni_se_resources_on(&gi2c->se); 937 if (ret) 938 return ret; 939 940 enable_irq(gi2c->irq); 941 gi2c->suspended = 0; 942 return 0; 943 } 944 945 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) 946 { 947 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 948 949 i2c_mark_adapter_suspended(&gi2c->adap); 950 951 if (!gi2c->suspended) { 952 geni_i2c_runtime_suspend(dev); 953 pm_runtime_disable(dev); 954 pm_runtime_set_suspended(dev); 955 pm_runtime_enable(dev); 956 } 957 return 0; 958 } 959 960 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev) 961 { 962 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 963 964 i2c_mark_adapter_resumed(&gi2c->adap); 965 return 0; 966 } 967 968 static const struct dev_pm_ops geni_i2c_pm_ops = { 969 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq) 970 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, 971 NULL) 972 }; 973 974 static const struct of_device_id geni_i2c_dt_match[] = { 975 { .compatible = "qcom,geni-i2c" }, 976 {} 977 }; 978 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); 979 980 static struct platform_driver geni_i2c_driver = { 981 .probe = geni_i2c_probe, 982 .remove = geni_i2c_remove, 983 .shutdown = geni_i2c_shutdown, 984 .driver = { 985 .name = "geni_i2c", 986 .pm = &geni_i2c_pm_ops, 987 .of_match_table = geni_i2c_dt_match, 988 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match), 989 }, 990 }; 991 992 module_platform_driver(geni_i2c_driver); 993 994 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); 995 MODULE_LICENSE("GPL v2"); 996