1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/dma-mapping.h> 6 #include <linux/err.h> 7 #include <linux/i2c.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/qcom-geni-se.h> 16 #include <linux/spinlock.h> 17 18 #define SE_I2C_TX_TRANS_LEN 0x26c 19 #define SE_I2C_RX_TRANS_LEN 0x270 20 #define SE_I2C_SCL_COUNTERS 0x278 21 22 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ 23 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) 24 #define SE_I2C_ABORT BIT(1) 25 26 /* M_CMD OP codes for I2C */ 27 #define I2C_WRITE 0x1 28 #define I2C_READ 0x2 29 #define I2C_WRITE_READ 0x3 30 #define I2C_ADDR_ONLY 0x4 31 #define I2C_BUS_CLEAR 0x6 32 #define I2C_STOP_ON_BUS 0x7 33 /* M_CMD params for I2C */ 34 #define PRE_CMD_DELAY BIT(0) 35 #define TIMESTAMP_BEFORE BIT(1) 36 #define STOP_STRETCH BIT(2) 37 #define TIMESTAMP_AFTER BIT(3) 38 #define POST_COMMAND_DELAY BIT(4) 39 #define IGNORE_ADD_NACK BIT(6) 40 #define READ_FINISHED_WITH_ACK BIT(7) 41 #define BYPASS_ADDR_PHASE BIT(8) 42 #define SLV_ADDR_MSK GENMASK(15, 9) 43 #define SLV_ADDR_SHFT 9 44 /* I2C SCL COUNTER fields */ 45 #define HIGH_COUNTER_MSK GENMASK(29, 20) 46 #define HIGH_COUNTER_SHFT 20 47 #define LOW_COUNTER_MSK GENMASK(19, 10) 48 #define LOW_COUNTER_SHFT 10 49 #define CYCLE_COUNTER_MSK GENMASK(9, 0) 50 51 enum geni_i2c_err_code { 52 GP_IRQ0, 53 NACK, 54 GP_IRQ2, 55 BUS_PROTO, 56 ARB_LOST, 57 GP_IRQ5, 58 GENI_OVERRUN, 59 GENI_ILLEGAL_CMD, 60 GENI_ABORT_DONE, 61 GENI_TIMEOUT, 62 }; 63 64 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ 65 << 5) 66 67 #define I2C_AUTO_SUSPEND_DELAY 250 68 #define KHZ(freq) (1000 * freq) 69 #define PACKING_BYTES_PW 4 70 71 #define ABORT_TIMEOUT HZ 72 #define XFER_TIMEOUT HZ 73 #define RST_TIMEOUT HZ 74 75 struct geni_i2c_dev { 76 struct geni_se se; 77 u32 tx_wm; 78 int irq; 79 int err; 80 struct i2c_adapter adap; 81 struct completion done; 82 struct i2c_msg *cur; 83 int cur_wr; 84 int cur_rd; 85 spinlock_t lock; 86 u32 clk_freq_out; 87 const struct geni_i2c_clk_fld *clk_fld; 88 int suspended; 89 }; 90 91 struct geni_i2c_err_log { 92 int err; 93 const char *msg; 94 }; 95 96 static const struct geni_i2c_err_log gi2c_log[] = { 97 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, 98 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"}, 99 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, 100 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"}, 101 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, 102 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, 103 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, 104 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, 105 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, 106 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, 107 }; 108 109 struct geni_i2c_clk_fld { 110 u32 clk_freq_out; 111 u8 clk_div; 112 u8 t_high_cnt; 113 u8 t_low_cnt; 114 u8 t_cycle_cnt; 115 }; 116 117 /* 118 * Hardware uses the underlying formula to calculate time periods of 119 * SCL clock cycle. Firmware uses some additional cycles excluded from the 120 * below formula and it is confirmed that the time periods are within 121 * specification limits. 122 * 123 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock 124 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock 125 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock 126 * clk_freq_out = t / t_cycle 127 * source_clock = 19.2 MHz 128 */ 129 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = { 130 {KHZ(100), 7, 10, 11, 26}, 131 {KHZ(400), 2, 5, 12, 24}, 132 {KHZ(1000), 1, 3, 9, 18}, 133 }; 134 135 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) 136 { 137 int i; 138 const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map; 139 140 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) { 141 if (itr->clk_freq_out == gi2c->clk_freq_out) { 142 gi2c->clk_fld = itr; 143 return 0; 144 } 145 } 146 return -EINVAL; 147 } 148 149 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) 150 { 151 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 152 u32 val; 153 154 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); 155 156 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; 157 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 158 159 val = itr->t_high_cnt << HIGH_COUNTER_SHFT; 160 val |= itr->t_low_cnt << LOW_COUNTER_SHFT; 161 val |= itr->t_cycle_cnt; 162 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 163 } 164 165 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) 166 { 167 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 168 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 169 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 170 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 171 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 172 u32 rx_st, tx_st; 173 174 if (dma) { 175 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 176 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 177 } else { 178 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); 179 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); 180 } 181 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", 182 dma, tx_st, rx_st, m_stat); 183 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", 184 m_cmd, geni_s, geni_ios); 185 } 186 187 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) 188 { 189 if (!gi2c->err) 190 gi2c->err = gi2c_log[err].err; 191 if (gi2c->cur) 192 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", 193 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); 194 195 if (err != NACK && err != GENI_ABORT_DONE) { 196 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 197 geni_i2c_err_misc(gi2c); 198 } 199 } 200 201 static irqreturn_t geni_i2c_irq(int irq, void *dev) 202 { 203 struct geni_i2c_dev *gi2c = dev; 204 void __iomem *base = gi2c->se.base; 205 int j, p; 206 u32 m_stat; 207 u32 rx_st; 208 u32 dm_tx_st; 209 u32 dm_rx_st; 210 u32 dma; 211 u32 val; 212 struct i2c_msg *cur; 213 unsigned long flags; 214 215 spin_lock_irqsave(&gi2c->lock, flags); 216 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); 217 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); 218 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); 219 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); 220 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 221 cur = gi2c->cur; 222 223 if (!cur || 224 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || 225 dm_rx_st & (DM_I2C_CB_ERR)) { 226 if (m_stat & M_GP_IRQ_1_EN) 227 geni_i2c_err(gi2c, NACK); 228 if (m_stat & M_GP_IRQ_3_EN) 229 geni_i2c_err(gi2c, BUS_PROTO); 230 if (m_stat & M_GP_IRQ_4_EN) 231 geni_i2c_err(gi2c, ARB_LOST); 232 if (m_stat & M_CMD_OVERRUN_EN) 233 geni_i2c_err(gi2c, GENI_OVERRUN); 234 if (m_stat & M_ILLEGAL_CMD_EN) 235 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); 236 if (m_stat & M_CMD_ABORT_EN) 237 geni_i2c_err(gi2c, GENI_ABORT_DONE); 238 if (m_stat & M_GP_IRQ_0_EN) 239 geni_i2c_err(gi2c, GP_IRQ0); 240 241 /* Disable the TX Watermark interrupt to stop TX */ 242 if (!dma) 243 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 244 } else if (dma) { 245 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", 246 dm_tx_st, dm_rx_st); 247 } else if (cur->flags & I2C_M_RD && 248 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { 249 u32 rxcnt = rx_st & RX_FIFO_WC_MSK; 250 251 for (j = 0; j < rxcnt; j++) { 252 p = 0; 253 val = readl_relaxed(base + SE_GENI_RX_FIFOn); 254 while (gi2c->cur_rd < cur->len && p < sizeof(val)) { 255 cur->buf[gi2c->cur_rd++] = val & 0xff; 256 val >>= 8; 257 p++; 258 } 259 if (gi2c->cur_rd == cur->len) 260 break; 261 } 262 } else if (!(cur->flags & I2C_M_RD) && 263 m_stat & M_TX_FIFO_WATERMARK_EN) { 264 for (j = 0; j < gi2c->tx_wm; j++) { 265 u32 temp; 266 267 val = 0; 268 p = 0; 269 while (gi2c->cur_wr < cur->len && p < sizeof(val)) { 270 temp = cur->buf[gi2c->cur_wr++]; 271 val |= temp << (p * 8); 272 p++; 273 } 274 writel_relaxed(val, base + SE_GENI_TX_FIFOn); 275 /* TX Complete, Disable the TX Watermark interrupt */ 276 if (gi2c->cur_wr == cur->len) { 277 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 278 break; 279 } 280 } 281 } 282 283 if (m_stat) 284 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); 285 286 if (dma && dm_tx_st) 287 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); 288 if (dma && dm_rx_st) 289 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); 290 291 /* if this is err with done-bit not set, handle that through timeout. */ 292 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN || 293 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE || 294 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE) 295 complete(&gi2c->done); 296 297 spin_unlock_irqrestore(&gi2c->lock, flags); 298 299 return IRQ_HANDLED; 300 } 301 302 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) 303 { 304 u32 val; 305 unsigned long time_left = ABORT_TIMEOUT; 306 unsigned long flags; 307 308 spin_lock_irqsave(&gi2c->lock, flags); 309 geni_i2c_err(gi2c, GENI_TIMEOUT); 310 gi2c->cur = NULL; 311 geni_se_abort_m_cmd(&gi2c->se); 312 spin_unlock_irqrestore(&gi2c->lock, flags); 313 do { 314 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 315 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 316 } while (!(val & M_CMD_ABORT_EN) && time_left); 317 318 if (!(val & M_CMD_ABORT_EN)) 319 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); 320 } 321 322 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) 323 { 324 u32 val; 325 unsigned long time_left = RST_TIMEOUT; 326 327 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); 328 do { 329 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 330 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 331 } while (!(val & RX_RESET_DONE) && time_left); 332 333 if (!(val & RX_RESET_DONE)) 334 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); 335 } 336 337 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) 338 { 339 u32 val; 340 unsigned long time_left = RST_TIMEOUT; 341 342 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); 343 do { 344 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 345 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 346 } while (!(val & TX_RESET_DONE) && time_left); 347 348 if (!(val & TX_RESET_DONE)) 349 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); 350 } 351 352 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 353 u32 m_param) 354 { 355 dma_addr_t rx_dma; 356 unsigned long time_left; 357 void *dma_buf; 358 struct geni_se *se = &gi2c->se; 359 size_t len = msg->len; 360 361 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 362 if (dma_buf) 363 geni_se_select_mode(se, GENI_SE_DMA); 364 else 365 geni_se_select_mode(se, GENI_SE_FIFO); 366 367 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 368 geni_se_setup_m_cmd(se, I2C_READ, m_param); 369 370 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 371 geni_se_select_mode(se, GENI_SE_FIFO); 372 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 373 dma_buf = NULL; 374 } 375 376 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 377 if (!time_left) 378 geni_i2c_abort_xfer(gi2c); 379 380 gi2c->cur_rd = 0; 381 if (dma_buf) { 382 if (gi2c->err) 383 geni_i2c_rx_fsm_rst(gi2c); 384 geni_se_rx_dma_unprep(se, rx_dma, len); 385 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err); 386 } 387 388 return gi2c->err; 389 } 390 391 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 392 u32 m_param) 393 { 394 dma_addr_t tx_dma; 395 unsigned long time_left; 396 void *dma_buf; 397 struct geni_se *se = &gi2c->se; 398 size_t len = msg->len; 399 400 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 401 if (dma_buf) 402 geni_se_select_mode(se, GENI_SE_DMA); 403 else 404 geni_se_select_mode(se, GENI_SE_FIFO); 405 406 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 407 geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 408 409 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 410 geni_se_select_mode(se, GENI_SE_FIFO); 411 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 412 dma_buf = NULL; 413 } 414 415 if (!dma_buf) /* Get FIFO IRQ */ 416 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); 417 418 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 419 if (!time_left) 420 geni_i2c_abort_xfer(gi2c); 421 422 gi2c->cur_wr = 0; 423 if (dma_buf) { 424 if (gi2c->err) 425 geni_i2c_tx_fsm_rst(gi2c); 426 geni_se_tx_dma_unprep(se, tx_dma, len); 427 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err); 428 } 429 430 return gi2c->err; 431 } 432 433 static int geni_i2c_xfer(struct i2c_adapter *adap, 434 struct i2c_msg msgs[], 435 int num) 436 { 437 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); 438 int i, ret; 439 440 gi2c->err = 0; 441 reinit_completion(&gi2c->done); 442 ret = pm_runtime_get_sync(gi2c->se.dev); 443 if (ret < 0) { 444 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); 445 pm_runtime_put_noidle(gi2c->se.dev); 446 /* Set device in suspended since resume failed */ 447 pm_runtime_set_suspended(gi2c->se.dev); 448 return ret; 449 } 450 451 qcom_geni_i2c_conf(gi2c); 452 for (i = 0; i < num; i++) { 453 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; 454 455 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); 456 457 gi2c->cur = &msgs[i]; 458 if (msgs[i].flags & I2C_M_RD) 459 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); 460 else 461 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); 462 463 if (ret) 464 break; 465 } 466 if (ret == 0) 467 ret = num; 468 469 pm_runtime_mark_last_busy(gi2c->se.dev); 470 pm_runtime_put_autosuspend(gi2c->se.dev); 471 gi2c->cur = NULL; 472 gi2c->err = 0; 473 return ret; 474 } 475 476 static u32 geni_i2c_func(struct i2c_adapter *adap) 477 { 478 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 479 } 480 481 static const struct i2c_algorithm geni_i2c_algo = { 482 .master_xfer = geni_i2c_xfer, 483 .functionality = geni_i2c_func, 484 }; 485 486 static int geni_i2c_probe(struct platform_device *pdev) 487 { 488 struct geni_i2c_dev *gi2c; 489 struct resource *res; 490 u32 proto, tx_depth; 491 int ret; 492 493 gi2c = devm_kzalloc(&pdev->dev, sizeof(*gi2c), GFP_KERNEL); 494 if (!gi2c) 495 return -ENOMEM; 496 497 gi2c->se.dev = &pdev->dev; 498 gi2c->se.wrapper = dev_get_drvdata(pdev->dev.parent); 499 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 500 gi2c->se.base = devm_ioremap_resource(&pdev->dev, res); 501 if (IS_ERR(gi2c->se.base)) 502 return PTR_ERR(gi2c->se.base); 503 504 gi2c->se.clk = devm_clk_get(&pdev->dev, "se"); 505 if (IS_ERR(gi2c->se.clk)) { 506 ret = PTR_ERR(gi2c->se.clk); 507 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 508 return ret; 509 } 510 511 ret = device_property_read_u32(&pdev->dev, "clock-frequency", 512 &gi2c->clk_freq_out); 513 if (ret) { 514 dev_info(&pdev->dev, 515 "Bus frequency not specified, default to 100kHz.\n"); 516 gi2c->clk_freq_out = KHZ(100); 517 } 518 519 gi2c->irq = platform_get_irq(pdev, 0); 520 if (gi2c->irq < 0) { 521 dev_err(&pdev->dev, "IRQ error for i2c-geni\n"); 522 return gi2c->irq; 523 } 524 525 ret = geni_i2c_clk_map_idx(gi2c); 526 if (ret) { 527 dev_err(&pdev->dev, "Invalid clk frequency %d Hz: %d\n", 528 gi2c->clk_freq_out, ret); 529 return ret; 530 } 531 532 gi2c->adap.algo = &geni_i2c_algo; 533 init_completion(&gi2c->done); 534 spin_lock_init(&gi2c->lock); 535 platform_set_drvdata(pdev, gi2c); 536 ret = devm_request_irq(&pdev->dev, gi2c->irq, geni_i2c_irq, 537 IRQF_TRIGGER_HIGH, "i2c_geni", gi2c); 538 if (ret) { 539 dev_err(&pdev->dev, "Request_irq failed:%d: err:%d\n", 540 gi2c->irq, ret); 541 return ret; 542 } 543 /* Disable the interrupt so that the system can enter low-power mode */ 544 disable_irq(gi2c->irq); 545 i2c_set_adapdata(&gi2c->adap, gi2c); 546 gi2c->adap.dev.parent = &pdev->dev; 547 gi2c->adap.dev.of_node = pdev->dev.of_node; 548 strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); 549 550 ret = geni_se_resources_on(&gi2c->se); 551 if (ret) { 552 dev_err(&pdev->dev, "Error turning on resources %d\n", ret); 553 return ret; 554 } 555 proto = geni_se_read_proto(&gi2c->se); 556 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); 557 if (proto != GENI_SE_I2C) { 558 dev_err(&pdev->dev, "Invalid proto %d\n", proto); 559 geni_se_resources_off(&gi2c->se); 560 return -ENXIO; 561 } 562 gi2c->tx_wm = tx_depth - 1; 563 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); 564 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW, 565 true, true, true); 566 ret = geni_se_resources_off(&gi2c->se); 567 if (ret) { 568 dev_err(&pdev->dev, "Error turning off resources %d\n", ret); 569 return ret; 570 } 571 572 dev_dbg(&pdev->dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); 573 574 gi2c->suspended = 1; 575 pm_runtime_set_suspended(gi2c->se.dev); 576 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); 577 pm_runtime_use_autosuspend(gi2c->se.dev); 578 pm_runtime_enable(gi2c->se.dev); 579 580 ret = i2c_add_adapter(&gi2c->adap); 581 if (ret) { 582 dev_err(&pdev->dev, "Error adding i2c adapter %d\n", ret); 583 pm_runtime_disable(gi2c->se.dev); 584 return ret; 585 } 586 587 return 0; 588 } 589 590 static int geni_i2c_remove(struct platform_device *pdev) 591 { 592 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 593 594 i2c_del_adapter(&gi2c->adap); 595 pm_runtime_disable(gi2c->se.dev); 596 return 0; 597 } 598 599 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) 600 { 601 int ret; 602 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 603 604 disable_irq(gi2c->irq); 605 ret = geni_se_resources_off(&gi2c->se); 606 if (ret) { 607 enable_irq(gi2c->irq); 608 return ret; 609 610 } else { 611 gi2c->suspended = 1; 612 } 613 614 return 0; 615 } 616 617 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) 618 { 619 int ret; 620 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 621 622 ret = geni_se_resources_on(&gi2c->se); 623 if (ret) 624 return ret; 625 626 enable_irq(gi2c->irq); 627 gi2c->suspended = 0; 628 return 0; 629 } 630 631 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) 632 { 633 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 634 635 if (!gi2c->suspended) { 636 geni_i2c_runtime_suspend(dev); 637 pm_runtime_disable(dev); 638 pm_runtime_set_suspended(dev); 639 pm_runtime_enable(dev); 640 } 641 return 0; 642 } 643 644 static const struct dev_pm_ops geni_i2c_pm_ops = { 645 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, NULL) 646 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, 647 NULL) 648 }; 649 650 static const struct of_device_id geni_i2c_dt_match[] = { 651 { .compatible = "qcom,geni-i2c" }, 652 {} 653 }; 654 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); 655 656 static struct platform_driver geni_i2c_driver = { 657 .probe = geni_i2c_probe, 658 .remove = geni_i2c_remove, 659 .driver = { 660 .name = "geni_i2c", 661 .pm = &geni_i2c_pm_ops, 662 .of_match_table = geni_i2c_dt_match, 663 }, 664 }; 665 666 module_platform_driver(geni_i2c_driver); 667 668 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); 669 MODULE_LICENSE("GPL v2"); 670