1 /* 2 * i2c_adap_pxa.c 3 * 4 * I2C adapter for the PXA I2C bus access. 5 * 6 * Copyright (C) 2002 Intrinsyc Software Inc. 7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * History: 14 * Apr 2002: Initial version [CS] 15 * Jun 2002: Properly separated algo/adap [FB] 16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] 17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem] 18 * Sep 2004: Major rework to ensure efficient bus handling [RMK] 19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] 20 * Feb 2005: Rework slave mode handling [RMK] 21 */ 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/i2c.h> 25 #include <linux/init.h> 26 #include <linux/time.h> 27 #include <linux/sched.h> 28 #include <linux/delay.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/i2c-pxa.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/platform_device.h> 35 #include <linux/err.h> 36 #include <linux/clk.h> 37 #include <linux/slab.h> 38 #include <linux/io.h> 39 #include <linux/i2c/pxa-i2c.h> 40 41 #include <asm/irq.h> 42 43 struct pxa_reg_layout { 44 u32 ibmr; 45 u32 idbr; 46 u32 icr; 47 u32 isr; 48 u32 isar; 49 }; 50 51 enum pxa_i2c_types { 52 REGS_PXA2XX, 53 REGS_PXA3XX, 54 REGS_CE4100, 55 }; 56 57 /* 58 * I2C registers definitions 59 */ 60 static struct pxa_reg_layout pxa_reg_layout[] = { 61 [REGS_PXA2XX] = { 62 .ibmr = 0x00, 63 .idbr = 0x08, 64 .icr = 0x10, 65 .isr = 0x18, 66 .isar = 0x20, 67 }, 68 [REGS_PXA3XX] = { 69 .ibmr = 0x00, 70 .idbr = 0x04, 71 .icr = 0x08, 72 .isr = 0x0c, 73 .isar = 0x10, 74 }, 75 [REGS_CE4100] = { 76 .ibmr = 0x14, 77 .idbr = 0x0c, 78 .icr = 0x00, 79 .isr = 0x04, 80 /* no isar register */ 81 }, 82 }; 83 84 static const struct platform_device_id i2c_pxa_id_table[] = { 85 { "pxa2xx-i2c", REGS_PXA2XX }, 86 { "pxa3xx-pwri2c", REGS_PXA3XX }, 87 { "ce4100-i2c", REGS_CE4100 }, 88 { }, 89 }; 90 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); 91 92 /* 93 * I2C bit definitions 94 */ 95 96 #define ICR_START (1 << 0) /* start bit */ 97 #define ICR_STOP (1 << 1) /* stop bit */ 98 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ 99 #define ICR_TB (1 << 3) /* transfer byte bit */ 100 #define ICR_MA (1 << 4) /* master abort */ 101 #define ICR_SCLE (1 << 5) /* master clock enable */ 102 #define ICR_IUE (1 << 6) /* unit enable */ 103 #define ICR_GCD (1 << 7) /* general call disable */ 104 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ 105 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ 106 #define ICR_BEIE (1 << 10) /* enable bus error ints */ 107 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ 108 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ 109 #define ICR_SADIE (1 << 13) /* slave address detected int enable */ 110 #define ICR_UR (1 << 14) /* unit reset */ 111 #define ICR_FM (1 << 15) /* fast mode */ 112 #define ICR_HS (1 << 16) /* High Speed mode */ 113 #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */ 114 115 #define ISR_RWM (1 << 0) /* read/write mode */ 116 #define ISR_ACKNAK (1 << 1) /* ack/nak status */ 117 #define ISR_UB (1 << 2) /* unit busy */ 118 #define ISR_IBB (1 << 3) /* bus busy */ 119 #define ISR_SSD (1 << 4) /* slave stop detected */ 120 #define ISR_ALD (1 << 5) /* arbitration loss detected */ 121 #define ISR_ITE (1 << 6) /* tx buffer empty */ 122 #define ISR_IRF (1 << 7) /* rx buffer full */ 123 #define ISR_GCAD (1 << 8) /* general call address detected */ 124 #define ISR_SAD (1 << 9) /* slave address detected */ 125 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ 126 127 struct pxa_i2c { 128 spinlock_t lock; 129 wait_queue_head_t wait; 130 struct i2c_msg *msg; 131 unsigned int msg_num; 132 unsigned int msg_idx; 133 unsigned int msg_ptr; 134 unsigned int slave_addr; 135 136 struct i2c_adapter adap; 137 struct clk *clk; 138 #ifdef CONFIG_I2C_PXA_SLAVE 139 struct i2c_slave_client *slave; 140 #endif 141 142 unsigned int irqlogidx; 143 u32 isrlog[32]; 144 u32 icrlog[32]; 145 146 void __iomem *reg_base; 147 void __iomem *reg_ibmr; 148 void __iomem *reg_idbr; 149 void __iomem *reg_icr; 150 void __iomem *reg_isr; 151 void __iomem *reg_isar; 152 153 unsigned long iobase; 154 unsigned long iosize; 155 156 int irq; 157 unsigned int use_pio :1; 158 unsigned int fast_mode :1; 159 unsigned int high_mode:1; 160 unsigned char master_code; 161 unsigned long rate; 162 bool highmode_enter; 163 }; 164 165 #define _IBMR(i2c) ((i2c)->reg_ibmr) 166 #define _IDBR(i2c) ((i2c)->reg_idbr) 167 #define _ICR(i2c) ((i2c)->reg_icr) 168 #define _ISR(i2c) ((i2c)->reg_isr) 169 #define _ISAR(i2c) ((i2c)->reg_isar) 170 171 /* 172 * I2C Slave mode address 173 */ 174 #define I2C_PXA_SLAVE_ADDR 0x1 175 176 #ifdef DEBUG 177 178 struct bits { 179 u32 mask; 180 const char *set; 181 const char *unset; 182 }; 183 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } 184 185 static inline void 186 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) 187 { 188 printk("%s %08x: ", prefix, val); 189 while (num--) { 190 const char *str = val & bits->mask ? bits->set : bits->unset; 191 if (str) 192 printk("%s ", str); 193 bits++; 194 } 195 } 196 197 static const struct bits isr_bits[] = { 198 PXA_BIT(ISR_RWM, "RX", "TX"), 199 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), 200 PXA_BIT(ISR_UB, "Bsy", "Rdy"), 201 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), 202 PXA_BIT(ISR_SSD, "SlaveStop", NULL), 203 PXA_BIT(ISR_ALD, "ALD", NULL), 204 PXA_BIT(ISR_ITE, "TxEmpty", NULL), 205 PXA_BIT(ISR_IRF, "RxFull", NULL), 206 PXA_BIT(ISR_GCAD, "GenCall", NULL), 207 PXA_BIT(ISR_SAD, "SlaveAddr", NULL), 208 PXA_BIT(ISR_BED, "BusErr", NULL), 209 }; 210 211 static void decode_ISR(unsigned int val) 212 { 213 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); 214 printk("\n"); 215 } 216 217 static const struct bits icr_bits[] = { 218 PXA_BIT(ICR_START, "START", NULL), 219 PXA_BIT(ICR_STOP, "STOP", NULL), 220 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), 221 PXA_BIT(ICR_TB, "TB", NULL), 222 PXA_BIT(ICR_MA, "MA", NULL), 223 PXA_BIT(ICR_SCLE, "SCLE", "scle"), 224 PXA_BIT(ICR_IUE, "IUE", "iue"), 225 PXA_BIT(ICR_GCD, "GCD", NULL), 226 PXA_BIT(ICR_ITEIE, "ITEIE", NULL), 227 PXA_BIT(ICR_IRFIE, "IRFIE", NULL), 228 PXA_BIT(ICR_BEIE, "BEIE", NULL), 229 PXA_BIT(ICR_SSDIE, "SSDIE", NULL), 230 PXA_BIT(ICR_ALDIE, "ALDIE", NULL), 231 PXA_BIT(ICR_SADIE, "SADIE", NULL), 232 PXA_BIT(ICR_UR, "UR", "ur"), 233 }; 234 235 #ifdef CONFIG_I2C_PXA_SLAVE 236 static void decode_ICR(unsigned int val) 237 { 238 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); 239 printk("\n"); 240 } 241 #endif 242 243 static unsigned int i2c_debug = DEBUG; 244 245 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) 246 { 247 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, 248 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 249 } 250 251 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) 252 253 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) 254 { 255 unsigned int i; 256 printk(KERN_ERR "i2c: error: %s\n", why); 257 printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", 258 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); 259 printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n", 260 readl(_ICR(i2c)), readl(_ISR(i2c))); 261 printk(KERN_DEBUG "i2c: log: "); 262 for (i = 0; i < i2c->irqlogidx; i++) 263 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); 264 printk("\n"); 265 } 266 267 #else /* ifdef DEBUG */ 268 269 #define i2c_debug 0 270 271 #define show_state(i2c) do { } while (0) 272 #define decode_ISR(val) do { } while (0) 273 #define decode_ICR(val) do { } while (0) 274 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0) 275 276 #endif /* ifdef DEBUG / else */ 277 278 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); 279 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); 280 281 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) 282 { 283 return !(readl(_ICR(i2c)) & ICR_SCLE); 284 } 285 286 static void i2c_pxa_abort(struct pxa_i2c *i2c) 287 { 288 int i = 250; 289 290 if (i2c_pxa_is_slavemode(i2c)) { 291 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); 292 return; 293 } 294 295 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { 296 unsigned long icr = readl(_ICR(i2c)); 297 298 icr &= ~ICR_START; 299 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; 300 301 writel(icr, _ICR(i2c)); 302 303 show_state(i2c); 304 305 mdelay(1); 306 i --; 307 } 308 309 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), 310 _ICR(i2c)); 311 } 312 313 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) 314 { 315 int timeout = DEF_TIMEOUT; 316 317 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { 318 if ((readl(_ISR(i2c)) & ISR_SAD) != 0) 319 timeout += 4; 320 321 msleep(2); 322 show_state(i2c); 323 } 324 325 if (timeout < 0) 326 show_state(i2c); 327 328 return timeout < 0 ? I2C_RETRY : 0; 329 } 330 331 static int i2c_pxa_wait_master(struct pxa_i2c *i2c) 332 { 333 unsigned long timeout = jiffies + HZ*4; 334 335 while (time_before(jiffies, timeout)) { 336 if (i2c_debug > 1) 337 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 338 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 339 340 if (readl(_ISR(i2c)) & ISR_SAD) { 341 if (i2c_debug > 0) 342 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); 343 goto out; 344 } 345 346 /* wait for unit and bus being not busy, and we also do a 347 * quick check of the i2c lines themselves to ensure they've 348 * gone high... 349 */ 350 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { 351 if (i2c_debug > 0) 352 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 353 return 1; 354 } 355 356 msleep(1); 357 } 358 359 if (i2c_debug > 0) 360 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 361 out: 362 return 0; 363 } 364 365 static int i2c_pxa_set_master(struct pxa_i2c *i2c) 366 { 367 if (i2c_debug) 368 dev_dbg(&i2c->adap.dev, "setting to bus master\n"); 369 370 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { 371 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); 372 if (!i2c_pxa_wait_master(i2c)) { 373 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); 374 return I2C_RETRY; 375 } 376 } 377 378 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); 379 return 0; 380 } 381 382 #ifdef CONFIG_I2C_PXA_SLAVE 383 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) 384 { 385 unsigned long timeout = jiffies + HZ*1; 386 387 /* wait for stop */ 388 389 show_state(i2c); 390 391 while (time_before(jiffies, timeout)) { 392 if (i2c_debug > 1) 393 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 394 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 395 396 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || 397 (readl(_ISR(i2c)) & ISR_SAD) != 0 || 398 (readl(_ICR(i2c)) & ICR_SCLE) == 0) { 399 if (i2c_debug > 1) 400 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 401 return 1; 402 } 403 404 msleep(1); 405 } 406 407 if (i2c_debug > 0) 408 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 409 return 0; 410 } 411 412 /* 413 * clear the hold on the bus, and take of anything else 414 * that has been configured 415 */ 416 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) 417 { 418 show_state(i2c); 419 420 if (errcode < 0) { 421 udelay(100); /* simple delay */ 422 } else { 423 /* we need to wait for the stop condition to end */ 424 425 /* if we where in stop, then clear... */ 426 if (readl(_ICR(i2c)) & ICR_STOP) { 427 udelay(100); 428 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); 429 } 430 431 if (!i2c_pxa_wait_slave(i2c)) { 432 dev_err(&i2c->adap.dev, "%s: wait timedout\n", 433 __func__); 434 return; 435 } 436 } 437 438 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); 439 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 440 441 if (i2c_debug) { 442 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); 443 decode_ICR(readl(_ICR(i2c))); 444 } 445 } 446 #else 447 #define i2c_pxa_set_slave(i2c, err) do { } while (0) 448 #endif 449 450 static void i2c_pxa_reset(struct pxa_i2c *i2c) 451 { 452 pr_debug("Resetting I2C Controller Unit\n"); 453 454 /* abort any transfer currently under way */ 455 i2c_pxa_abort(i2c); 456 457 /* reset according to 9.8 */ 458 writel(ICR_UR, _ICR(i2c)); 459 writel(I2C_ISR_INIT, _ISR(i2c)); 460 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); 461 462 if (i2c->reg_isar) 463 writel(i2c->slave_addr, _ISAR(i2c)); 464 465 /* set control register values */ 466 writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c)); 467 writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c)); 468 469 #ifdef CONFIG_I2C_PXA_SLAVE 470 dev_info(&i2c->adap.dev, "Enabling slave mode\n"); 471 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); 472 #endif 473 474 i2c_pxa_set_slave(i2c, 0); 475 476 /* enable unit */ 477 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); 478 udelay(100); 479 } 480 481 482 #ifdef CONFIG_I2C_PXA_SLAVE 483 /* 484 * PXA I2C Slave mode 485 */ 486 487 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 488 { 489 if (isr & ISR_BED) { 490 /* what should we do here? */ 491 } else { 492 int ret = 0; 493 494 if (i2c->slave != NULL) 495 ret = i2c->slave->read(i2c->slave->data); 496 497 writel(ret, _IDBR(i2c)); 498 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ 499 } 500 } 501 502 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 503 { 504 unsigned int byte = readl(_IDBR(i2c)); 505 506 if (i2c->slave != NULL) 507 i2c->slave->write(i2c->slave->data, byte); 508 509 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 510 } 511 512 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 513 { 514 int timeout; 515 516 if (i2c_debug > 0) 517 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", 518 (isr & ISR_RWM) ? 'r' : 't'); 519 520 if (i2c->slave != NULL) 521 i2c->slave->event(i2c->slave->data, 522 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); 523 524 /* 525 * slave could interrupt in the middle of us generating a 526 * start condition... if this happens, we'd better back off 527 * and stop holding the poor thing up 528 */ 529 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); 530 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 531 532 timeout = 0x10000; 533 534 while (1) { 535 if ((readl(_IBMR(i2c)) & 2) == 2) 536 break; 537 538 timeout--; 539 540 if (timeout <= 0) { 541 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 542 break; 543 } 544 } 545 546 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 547 } 548 549 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 550 { 551 if (i2c_debug > 2) 552 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); 553 554 if (i2c->slave != NULL) 555 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); 556 557 if (i2c_debug > 2) 558 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); 559 560 /* 561 * If we have a master-mode message waiting, 562 * kick it off now that the slave has completed. 563 */ 564 if (i2c->msg) 565 i2c_pxa_master_complete(i2c, I2C_RETRY); 566 } 567 #else 568 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 569 { 570 if (isr & ISR_BED) { 571 /* what should we do here? */ 572 } else { 573 writel(0, _IDBR(i2c)); 574 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 575 } 576 } 577 578 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 579 { 580 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); 581 } 582 583 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 584 { 585 int timeout; 586 587 /* 588 * slave could interrupt in the middle of us generating a 589 * start condition... if this happens, we'd better back off 590 * and stop holding the poor thing up 591 */ 592 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); 593 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); 594 595 timeout = 0x10000; 596 597 while (1) { 598 if ((readl(_IBMR(i2c)) & 2) == 2) 599 break; 600 601 timeout--; 602 603 if (timeout <= 0) { 604 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 605 break; 606 } 607 } 608 609 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 610 } 611 612 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 613 { 614 if (i2c->msg) 615 i2c_pxa_master_complete(i2c, I2C_RETRY); 616 } 617 #endif 618 619 /* 620 * PXA I2C Master mode 621 */ 622 623 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) 624 { 625 unsigned int addr = (msg->addr & 0x7f) << 1; 626 627 if (msg->flags & I2C_M_RD) 628 addr |= 1; 629 630 return addr; 631 } 632 633 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) 634 { 635 u32 icr; 636 637 /* 638 * Step 1: target slave address into IDBR 639 */ 640 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); 641 642 /* 643 * Step 2: initiate the write. 644 */ 645 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); 646 writel(icr | ICR_START | ICR_TB, _ICR(i2c)); 647 } 648 649 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) 650 { 651 u32 icr; 652 653 /* 654 * Clear the STOP and ACK flags 655 */ 656 icr = readl(_ICR(i2c)); 657 icr &= ~(ICR_STOP | ICR_ACKNAK); 658 writel(icr, _ICR(i2c)); 659 } 660 661 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) 662 { 663 /* make timeout the same as for interrupt based functions */ 664 long timeout = 2 * DEF_TIMEOUT; 665 666 /* 667 * Wait for the bus to become free. 668 */ 669 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { 670 udelay(1000); 671 show_state(i2c); 672 } 673 674 if (timeout < 0) { 675 show_state(i2c); 676 dev_err(&i2c->adap.dev, 677 "i2c_pxa: timeout waiting for bus free\n"); 678 return I2C_RETRY; 679 } 680 681 /* 682 * Set master mode. 683 */ 684 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); 685 686 return 0; 687 } 688 689 /* 690 * PXA I2C send master code 691 * 1. Load master code to IDBR and send it. 692 * Note for HS mode, set ICR [GPIOEN]. 693 * 2. Wait until win arbitration. 694 */ 695 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c) 696 { 697 u32 icr; 698 long timeout; 699 700 spin_lock_irq(&i2c->lock); 701 i2c->highmode_enter = true; 702 writel(i2c->master_code, _IDBR(i2c)); 703 704 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); 705 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE; 706 writel(icr, _ICR(i2c)); 707 708 spin_unlock_irq(&i2c->lock); 709 timeout = wait_event_timeout(i2c->wait, 710 i2c->highmode_enter == false, HZ * 1); 711 712 i2c->highmode_enter = false; 713 714 return (timeout == 0) ? I2C_RETRY : 0; 715 } 716 717 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, 718 struct i2c_msg *msg, int num) 719 { 720 unsigned long timeout = 500000; /* 5 seconds */ 721 int ret = 0; 722 723 ret = i2c_pxa_pio_set_master(i2c); 724 if (ret) 725 goto out; 726 727 i2c->msg = msg; 728 i2c->msg_num = num; 729 i2c->msg_idx = 0; 730 i2c->msg_ptr = 0; 731 i2c->irqlogidx = 0; 732 733 i2c_pxa_start_message(i2c); 734 735 while (i2c->msg_num > 0 && --timeout) { 736 i2c_pxa_handler(0, i2c); 737 udelay(10); 738 } 739 740 i2c_pxa_stop_message(i2c); 741 742 /* 743 * We place the return code in i2c->msg_idx. 744 */ 745 ret = i2c->msg_idx; 746 747 out: 748 if (timeout == 0) 749 i2c_pxa_scream_blue_murder(i2c, "timeout"); 750 751 return ret; 752 } 753 754 /* 755 * We are protected by the adapter bus mutex. 756 */ 757 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) 758 { 759 long timeout; 760 int ret; 761 762 /* 763 * Wait for the bus to become free. 764 */ 765 ret = i2c_pxa_wait_bus_not_busy(i2c); 766 if (ret) { 767 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); 768 goto out; 769 } 770 771 /* 772 * Set master mode. 773 */ 774 ret = i2c_pxa_set_master(i2c); 775 if (ret) { 776 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); 777 goto out; 778 } 779 780 if (i2c->high_mode) { 781 ret = i2c_pxa_send_mastercode(i2c); 782 if (ret) { 783 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n"); 784 goto out; 785 } 786 } 787 788 spin_lock_irq(&i2c->lock); 789 790 i2c->msg = msg; 791 i2c->msg_num = num; 792 i2c->msg_idx = 0; 793 i2c->msg_ptr = 0; 794 i2c->irqlogidx = 0; 795 796 i2c_pxa_start_message(i2c); 797 798 spin_unlock_irq(&i2c->lock); 799 800 /* 801 * The rest of the processing occurs in the interrupt handler. 802 */ 803 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 804 i2c_pxa_stop_message(i2c); 805 806 /* 807 * We place the return code in i2c->msg_idx. 808 */ 809 ret = i2c->msg_idx; 810 811 if (!timeout && i2c->msg_num) { 812 i2c_pxa_scream_blue_murder(i2c, "timeout"); 813 ret = I2C_RETRY; 814 } 815 816 out: 817 return ret; 818 } 819 820 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, 821 struct i2c_msg msgs[], int num) 822 { 823 struct pxa_i2c *i2c = adap->algo_data; 824 int ret, i; 825 826 /* If the I2C controller is disabled we need to reset it 827 (probably due to a suspend/resume destroying state). We do 828 this here as we can then avoid worrying about resuming the 829 controller before its users. */ 830 if (!(readl(_ICR(i2c)) & ICR_IUE)) 831 i2c_pxa_reset(i2c); 832 833 for (i = adap->retries; i >= 0; i--) { 834 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); 835 if (ret != I2C_RETRY) 836 goto out; 837 838 if (i2c_debug) 839 dev_dbg(&adap->dev, "Retrying transmission\n"); 840 udelay(100); 841 } 842 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 843 ret = -EREMOTEIO; 844 out: 845 i2c_pxa_set_slave(i2c, ret); 846 return ret; 847 } 848 849 /* 850 * i2c_pxa_master_complete - complete the message and wake up. 851 */ 852 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) 853 { 854 i2c->msg_ptr = 0; 855 i2c->msg = NULL; 856 i2c->msg_idx ++; 857 i2c->msg_num = 0; 858 if (ret) 859 i2c->msg_idx = ret; 860 if (!i2c->use_pio) 861 wake_up(&i2c->wait); 862 } 863 864 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) 865 { 866 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 867 868 again: 869 /* 870 * If ISR_ALD is set, we lost arbitration. 871 */ 872 if (isr & ISR_ALD) { 873 /* 874 * Do we need to do anything here? The PXA docs 875 * are vague about what happens. 876 */ 877 i2c_pxa_scream_blue_murder(i2c, "ALD set"); 878 879 /* 880 * We ignore this error. We seem to see spurious ALDs 881 * for seemingly no reason. If we handle them as I think 882 * they should, we end up causing an I2C error, which 883 * is painful for some systems. 884 */ 885 return; /* ignore */ 886 } 887 888 if (isr & ISR_BED) { 889 int ret = BUS_ERROR; 890 891 /* 892 * I2C bus error - either the device NAK'd us, or 893 * something more serious happened. If we were NAK'd 894 * on the initial address phase, we can retry. 895 */ 896 if (isr & ISR_ACKNAK) { 897 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) 898 ret = I2C_RETRY; 899 else 900 ret = XFER_NAKED; 901 } 902 i2c_pxa_master_complete(i2c, ret); 903 } else if (isr & ISR_RWM) { 904 /* 905 * Read mode. We have just sent the address byte, and 906 * now we must initiate the transfer. 907 */ 908 if (i2c->msg_ptr == i2c->msg->len - 1 && 909 i2c->msg_idx == i2c->msg_num - 1) 910 icr |= ICR_STOP | ICR_ACKNAK; 911 912 icr |= ICR_ALDIE | ICR_TB; 913 } else if (i2c->msg_ptr < i2c->msg->len) { 914 /* 915 * Write mode. Write the next data byte. 916 */ 917 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); 918 919 icr |= ICR_ALDIE | ICR_TB; 920 921 /* 922 * If this is the last byte of the last message, send 923 * a STOP. 924 */ 925 if (i2c->msg_ptr == i2c->msg->len && 926 i2c->msg_idx == i2c->msg_num - 1) 927 icr |= ICR_STOP; 928 } else if (i2c->msg_idx < i2c->msg_num - 1) { 929 /* 930 * Next segment of the message. 931 */ 932 i2c->msg_ptr = 0; 933 i2c->msg_idx ++; 934 i2c->msg++; 935 936 /* 937 * If we aren't doing a repeated start and address, 938 * go back and try to send the next byte. Note that 939 * we do not support switching the R/W direction here. 940 */ 941 if (i2c->msg->flags & I2C_M_NOSTART) 942 goto again; 943 944 /* 945 * Write the next address. 946 */ 947 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); 948 949 /* 950 * And trigger a repeated start, and send the byte. 951 */ 952 icr &= ~ICR_ALDIE; 953 icr |= ICR_START | ICR_TB; 954 } else { 955 if (i2c->msg->len == 0) { 956 /* 957 * Device probes have a message length of zero 958 * and need the bus to be reset before it can 959 * be used again. 960 */ 961 i2c_pxa_reset(i2c); 962 } 963 i2c_pxa_master_complete(i2c, 0); 964 } 965 966 i2c->icrlog[i2c->irqlogidx-1] = icr; 967 968 writel(icr, _ICR(i2c)); 969 show_state(i2c); 970 } 971 972 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) 973 { 974 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 975 976 /* 977 * Read the byte. 978 */ 979 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); 980 981 if (i2c->msg_ptr < i2c->msg->len) { 982 /* 983 * If this is the last byte of the last 984 * message, send a STOP. 985 */ 986 if (i2c->msg_ptr == i2c->msg->len - 1) 987 icr |= ICR_STOP | ICR_ACKNAK; 988 989 icr |= ICR_ALDIE | ICR_TB; 990 } else { 991 i2c_pxa_master_complete(i2c, 0); 992 } 993 994 i2c->icrlog[i2c->irqlogidx-1] = icr; 995 996 writel(icr, _ICR(i2c)); 997 } 998 999 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \ 1000 ISR_SAD | ISR_BED) 1001 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) 1002 { 1003 struct pxa_i2c *i2c = dev_id; 1004 u32 isr = readl(_ISR(i2c)); 1005 1006 if (!(isr & VALID_INT_SOURCE)) 1007 return IRQ_NONE; 1008 1009 if (i2c_debug > 2 && 0) { 1010 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", 1011 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); 1012 decode_ISR(isr); 1013 } 1014 1015 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) 1016 i2c->isrlog[i2c->irqlogidx++] = isr; 1017 1018 show_state(i2c); 1019 1020 /* 1021 * Always clear all pending IRQs. 1022 */ 1023 writel(isr & VALID_INT_SOURCE, _ISR(i2c)); 1024 1025 if (isr & ISR_SAD) 1026 i2c_pxa_slave_start(i2c, isr); 1027 if (isr & ISR_SSD) 1028 i2c_pxa_slave_stop(i2c); 1029 1030 if (i2c_pxa_is_slavemode(i2c)) { 1031 if (isr & ISR_ITE) 1032 i2c_pxa_slave_txempty(i2c, isr); 1033 if (isr & ISR_IRF) 1034 i2c_pxa_slave_rxfull(i2c, isr); 1035 } else if (i2c->msg && (!i2c->highmode_enter)) { 1036 if (isr & ISR_ITE) 1037 i2c_pxa_irq_txempty(i2c, isr); 1038 if (isr & ISR_IRF) 1039 i2c_pxa_irq_rxfull(i2c, isr); 1040 } else if ((isr & ISR_ITE) && i2c->highmode_enter) { 1041 i2c->highmode_enter = false; 1042 wake_up(&i2c->wait); 1043 } else { 1044 i2c_pxa_scream_blue_murder(i2c, "spurious irq"); 1045 } 1046 1047 return IRQ_HANDLED; 1048 } 1049 1050 1051 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 1052 { 1053 struct pxa_i2c *i2c = adap->algo_data; 1054 int ret, i; 1055 1056 for (i = adap->retries; i >= 0; i--) { 1057 ret = i2c_pxa_do_xfer(i2c, msgs, num); 1058 if (ret != I2C_RETRY) 1059 goto out; 1060 1061 if (i2c_debug) 1062 dev_dbg(&adap->dev, "Retrying transmission\n"); 1063 udelay(100); 1064 } 1065 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 1066 ret = -EREMOTEIO; 1067 out: 1068 i2c_pxa_set_slave(i2c, ret); 1069 return ret; 1070 } 1071 1072 static u32 i2c_pxa_functionality(struct i2c_adapter *adap) 1073 { 1074 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1075 } 1076 1077 static const struct i2c_algorithm i2c_pxa_algorithm = { 1078 .master_xfer = i2c_pxa_xfer, 1079 .functionality = i2c_pxa_functionality, 1080 }; 1081 1082 static const struct i2c_algorithm i2c_pxa_pio_algorithm = { 1083 .master_xfer = i2c_pxa_pio_xfer, 1084 .functionality = i2c_pxa_functionality, 1085 }; 1086 1087 static struct of_device_id i2c_pxa_dt_ids[] = { 1088 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX }, 1089 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX }, 1090 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA2XX }, 1091 {} 1092 }; 1093 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); 1094 1095 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c, 1096 enum pxa_i2c_types *i2c_types) 1097 { 1098 struct device_node *np = pdev->dev.of_node; 1099 const struct of_device_id *of_id = 1100 of_match_device(i2c_pxa_dt_ids, &pdev->dev); 1101 1102 if (!of_id) 1103 return 1; 1104 1105 /* For device tree we always use the dynamic or alias-assigned ID */ 1106 i2c->adap.nr = -1; 1107 1108 if (of_get_property(np, "mrvl,i2c-polling", NULL)) 1109 i2c->use_pio = 1; 1110 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL)) 1111 i2c->fast_mode = 1; 1112 *i2c_types = (u32)(of_id->data); 1113 return 0; 1114 } 1115 1116 static int i2c_pxa_probe_pdata(struct platform_device *pdev, 1117 struct pxa_i2c *i2c, 1118 enum pxa_i2c_types *i2c_types) 1119 { 1120 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev); 1121 const struct platform_device_id *id = platform_get_device_id(pdev); 1122 1123 *i2c_types = id->driver_data; 1124 if (plat) { 1125 i2c->use_pio = plat->use_pio; 1126 i2c->fast_mode = plat->fast_mode; 1127 i2c->high_mode = plat->high_mode; 1128 i2c->master_code = plat->master_code; 1129 if (!i2c->master_code) 1130 i2c->master_code = 0xe; 1131 i2c->rate = plat->rate; 1132 } 1133 return 0; 1134 } 1135 1136 static int i2c_pxa_probe(struct platform_device *dev) 1137 { 1138 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev); 1139 enum pxa_i2c_types i2c_type; 1140 struct pxa_i2c *i2c; 1141 struct resource *res = NULL; 1142 int ret, irq; 1143 1144 i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); 1145 if (!i2c) { 1146 ret = -ENOMEM; 1147 goto emalloc; 1148 } 1149 1150 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */ 1151 i2c->adap.nr = dev->id; 1152 1153 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type); 1154 if (ret > 0) 1155 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type); 1156 if (ret < 0) 1157 goto eclk; 1158 1159 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1160 irq = platform_get_irq(dev, 0); 1161 if (res == NULL || irq < 0) { 1162 ret = -ENODEV; 1163 goto eclk; 1164 } 1165 1166 if (!request_mem_region(res->start, resource_size(res), res->name)) { 1167 ret = -ENOMEM; 1168 goto eclk; 1169 } 1170 1171 i2c->adap.owner = THIS_MODULE; 1172 i2c->adap.retries = 5; 1173 1174 spin_lock_init(&i2c->lock); 1175 init_waitqueue_head(&i2c->wait); 1176 1177 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); 1178 1179 i2c->clk = clk_get(&dev->dev, NULL); 1180 if (IS_ERR(i2c->clk)) { 1181 ret = PTR_ERR(i2c->clk); 1182 goto eclk; 1183 } 1184 1185 i2c->reg_base = ioremap(res->start, resource_size(res)); 1186 if (!i2c->reg_base) { 1187 ret = -EIO; 1188 goto eremap; 1189 } 1190 1191 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; 1192 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; 1193 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; 1194 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; 1195 if (i2c_type != REGS_CE4100) 1196 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; 1197 1198 i2c->iobase = res->start; 1199 i2c->iosize = resource_size(res); 1200 1201 i2c->irq = irq; 1202 1203 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 1204 i2c->highmode_enter = false; 1205 1206 if (plat) { 1207 #ifdef CONFIG_I2C_PXA_SLAVE 1208 i2c->slave_addr = plat->slave_addr; 1209 i2c->slave = plat->slave; 1210 #endif 1211 i2c->adap.class = plat->class; 1212 } 1213 1214 if (i2c->high_mode) { 1215 if (i2c->rate) { 1216 clk_set_rate(i2c->clk, i2c->rate); 1217 pr_info("i2c: <%s> set rate to %ld\n", 1218 i2c->adap.name, clk_get_rate(i2c->clk)); 1219 } else 1220 pr_warn("i2c: <%s> clock rate not set\n", 1221 i2c->adap.name); 1222 } 1223 1224 clk_prepare_enable(i2c->clk); 1225 1226 if (i2c->use_pio) { 1227 i2c->adap.algo = &i2c_pxa_pio_algorithm; 1228 } else { 1229 i2c->adap.algo = &i2c_pxa_algorithm; 1230 ret = request_irq(irq, i2c_pxa_handler, IRQF_SHARED, 1231 dev_name(&dev->dev), i2c); 1232 if (ret) 1233 goto ereqirq; 1234 } 1235 1236 i2c_pxa_reset(i2c); 1237 1238 i2c->adap.algo_data = i2c; 1239 i2c->adap.dev.parent = &dev->dev; 1240 #ifdef CONFIG_OF 1241 i2c->adap.dev.of_node = dev->dev.of_node; 1242 #endif 1243 1244 ret = i2c_add_numbered_adapter(&i2c->adap); 1245 if (ret < 0) { 1246 printk(KERN_INFO "I2C: Failed to add bus\n"); 1247 goto eadapt; 1248 } 1249 1250 platform_set_drvdata(dev, i2c); 1251 1252 #ifdef CONFIG_I2C_PXA_SLAVE 1253 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", 1254 dev_name(&i2c->adap.dev), i2c->slave_addr); 1255 #else 1256 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", 1257 dev_name(&i2c->adap.dev)); 1258 #endif 1259 return 0; 1260 1261 eadapt: 1262 if (!i2c->use_pio) 1263 free_irq(irq, i2c); 1264 ereqirq: 1265 clk_disable_unprepare(i2c->clk); 1266 iounmap(i2c->reg_base); 1267 eremap: 1268 clk_put(i2c->clk); 1269 eclk: 1270 kfree(i2c); 1271 emalloc: 1272 release_mem_region(res->start, resource_size(res)); 1273 return ret; 1274 } 1275 1276 static int i2c_pxa_remove(struct platform_device *dev) 1277 { 1278 struct pxa_i2c *i2c = platform_get_drvdata(dev); 1279 1280 i2c_del_adapter(&i2c->adap); 1281 if (!i2c->use_pio) 1282 free_irq(i2c->irq, i2c); 1283 1284 clk_disable_unprepare(i2c->clk); 1285 clk_put(i2c->clk); 1286 1287 iounmap(i2c->reg_base); 1288 release_mem_region(i2c->iobase, i2c->iosize); 1289 kfree(i2c); 1290 1291 return 0; 1292 } 1293 1294 #ifdef CONFIG_PM 1295 static int i2c_pxa_suspend_noirq(struct device *dev) 1296 { 1297 struct platform_device *pdev = to_platform_device(dev); 1298 struct pxa_i2c *i2c = platform_get_drvdata(pdev); 1299 1300 clk_disable(i2c->clk); 1301 1302 return 0; 1303 } 1304 1305 static int i2c_pxa_resume_noirq(struct device *dev) 1306 { 1307 struct platform_device *pdev = to_platform_device(dev); 1308 struct pxa_i2c *i2c = platform_get_drvdata(pdev); 1309 1310 clk_enable(i2c->clk); 1311 i2c_pxa_reset(i2c); 1312 1313 return 0; 1314 } 1315 1316 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = { 1317 .suspend_noirq = i2c_pxa_suspend_noirq, 1318 .resume_noirq = i2c_pxa_resume_noirq, 1319 }; 1320 1321 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops) 1322 #else 1323 #define I2C_PXA_DEV_PM_OPS NULL 1324 #endif 1325 1326 static struct platform_driver i2c_pxa_driver = { 1327 .probe = i2c_pxa_probe, 1328 .remove = i2c_pxa_remove, 1329 .driver = { 1330 .name = "pxa2xx-i2c", 1331 .owner = THIS_MODULE, 1332 .pm = I2C_PXA_DEV_PM_OPS, 1333 .of_match_table = i2c_pxa_dt_ids, 1334 }, 1335 .id_table = i2c_pxa_id_table, 1336 }; 1337 1338 static int __init i2c_adap_pxa_init(void) 1339 { 1340 return platform_driver_register(&i2c_pxa_driver); 1341 } 1342 1343 static void __exit i2c_adap_pxa_exit(void) 1344 { 1345 platform_driver_unregister(&i2c_pxa_driver); 1346 } 1347 1348 MODULE_LICENSE("GPL"); 1349 MODULE_ALIAS("platform:pxa2xx-i2c"); 1350 1351 subsys_initcall(i2c_adap_pxa_init); 1352 module_exit(i2c_adap_pxa_exit); 1353