1 /* 2 * i2c_adap_pxa.c 3 * 4 * I2C adapter for the PXA I2C bus access. 5 * 6 * Copyright (C) 2002 Intrinsyc Software Inc. 7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * History: 14 * Apr 2002: Initial version [CS] 15 * Jun 2002: Properly separated algo/adap [FB] 16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] 17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem] 18 * Sep 2004: Major rework to ensure efficient bus handling [RMK] 19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] 20 * Feb 2005: Rework slave mode handling [RMK] 21 */ 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/i2c.h> 25 #include <linux/init.h> 26 #include <linux/time.h> 27 #include <linux/sched.h> 28 #include <linux/delay.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/i2c-pxa.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/platform_device.h> 35 #include <linux/err.h> 36 #include <linux/clk.h> 37 #include <linux/slab.h> 38 #include <linux/io.h> 39 #include <linux/i2c/pxa-i2c.h> 40 41 #include <asm/irq.h> 42 43 struct pxa_reg_layout { 44 u32 ibmr; 45 u32 idbr; 46 u32 icr; 47 u32 isr; 48 u32 isar; 49 u32 ilcr; 50 u32 iwcr; 51 u32 fm; 52 u32 hs; 53 }; 54 55 enum pxa_i2c_types { 56 REGS_PXA2XX, 57 REGS_PXA3XX, 58 REGS_CE4100, 59 REGS_PXA910, 60 REGS_A3700, 61 }; 62 63 #define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */ 64 #define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */ 65 66 /* 67 * I2C registers definitions 68 */ 69 static struct pxa_reg_layout pxa_reg_layout[] = { 70 [REGS_PXA2XX] = { 71 .ibmr = 0x00, 72 .idbr = 0x08, 73 .icr = 0x10, 74 .isr = 0x18, 75 .isar = 0x20, 76 }, 77 [REGS_PXA3XX] = { 78 .ibmr = 0x00, 79 .idbr = 0x04, 80 .icr = 0x08, 81 .isr = 0x0c, 82 .isar = 0x10, 83 }, 84 [REGS_CE4100] = { 85 .ibmr = 0x14, 86 .idbr = 0x0c, 87 .icr = 0x00, 88 .isr = 0x04, 89 /* no isar register */ 90 }, 91 [REGS_PXA910] = { 92 .ibmr = 0x00, 93 .idbr = 0x08, 94 .icr = 0x10, 95 .isr = 0x18, 96 .isar = 0x20, 97 .ilcr = 0x28, 98 .iwcr = 0x30, 99 }, 100 [REGS_A3700] = { 101 .ibmr = 0x00, 102 .idbr = 0x04, 103 .icr = 0x08, 104 .isr = 0x0c, 105 .isar = 0x10, 106 .fm = ICR_BUSMODE_FM, 107 .hs = ICR_BUSMODE_HS, 108 }, 109 }; 110 111 static const struct platform_device_id i2c_pxa_id_table[] = { 112 { "pxa2xx-i2c", REGS_PXA2XX }, 113 { "pxa3xx-pwri2c", REGS_PXA3XX }, 114 { "ce4100-i2c", REGS_CE4100 }, 115 { "pxa910-i2c", REGS_PXA910 }, 116 { "armada-3700-i2c", REGS_A3700 }, 117 { }, 118 }; 119 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); 120 121 /* 122 * I2C bit definitions 123 */ 124 125 #define ICR_START (1 << 0) /* start bit */ 126 #define ICR_STOP (1 << 1) /* stop bit */ 127 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ 128 #define ICR_TB (1 << 3) /* transfer byte bit */ 129 #define ICR_MA (1 << 4) /* master abort */ 130 #define ICR_SCLE (1 << 5) /* master clock enable */ 131 #define ICR_IUE (1 << 6) /* unit enable */ 132 #define ICR_GCD (1 << 7) /* general call disable */ 133 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ 134 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ 135 #define ICR_BEIE (1 << 10) /* enable bus error ints */ 136 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ 137 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ 138 #define ICR_SADIE (1 << 13) /* slave address detected int enable */ 139 #define ICR_UR (1 << 14) /* unit reset */ 140 #define ICR_FM (1 << 15) /* fast mode */ 141 #define ICR_HS (1 << 16) /* High Speed mode */ 142 #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */ 143 144 #define ISR_RWM (1 << 0) /* read/write mode */ 145 #define ISR_ACKNAK (1 << 1) /* ack/nak status */ 146 #define ISR_UB (1 << 2) /* unit busy */ 147 #define ISR_IBB (1 << 3) /* bus busy */ 148 #define ISR_SSD (1 << 4) /* slave stop detected */ 149 #define ISR_ALD (1 << 5) /* arbitration loss detected */ 150 #define ISR_ITE (1 << 6) /* tx buffer empty */ 151 #define ISR_IRF (1 << 7) /* rx buffer full */ 152 #define ISR_GCAD (1 << 8) /* general call address detected */ 153 #define ISR_SAD (1 << 9) /* slave address detected */ 154 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ 155 156 /* bit field shift & mask */ 157 #define ILCR_SLV_SHIFT 0 158 #define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT) 159 #define ILCR_FLV_SHIFT 9 160 #define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT) 161 #define ILCR_HLVL_SHIFT 18 162 #define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT) 163 #define ILCR_HLVH_SHIFT 27 164 #define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT) 165 166 #define IWCR_CNT_SHIFT 0 167 #define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT) 168 #define IWCR_HS_CNT1_SHIFT 5 169 #define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT) 170 #define IWCR_HS_CNT2_SHIFT 10 171 #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT) 172 173 struct pxa_i2c { 174 spinlock_t lock; 175 wait_queue_head_t wait; 176 struct i2c_msg *msg; 177 unsigned int msg_num; 178 unsigned int msg_idx; 179 unsigned int msg_ptr; 180 unsigned int slave_addr; 181 unsigned int req_slave_addr; 182 183 struct i2c_adapter adap; 184 struct clk *clk; 185 #ifdef CONFIG_I2C_PXA_SLAVE 186 struct i2c_slave_client *slave; 187 #endif 188 189 unsigned int irqlogidx; 190 u32 isrlog[32]; 191 u32 icrlog[32]; 192 193 void __iomem *reg_base; 194 void __iomem *reg_ibmr; 195 void __iomem *reg_idbr; 196 void __iomem *reg_icr; 197 void __iomem *reg_isr; 198 void __iomem *reg_isar; 199 void __iomem *reg_ilcr; 200 void __iomem *reg_iwcr; 201 202 unsigned long iobase; 203 unsigned long iosize; 204 205 int irq; 206 unsigned int use_pio :1; 207 unsigned int fast_mode :1; 208 unsigned int high_mode:1; 209 unsigned char master_code; 210 unsigned long rate; 211 bool highmode_enter; 212 u32 fm_mask; 213 u32 hs_mask; 214 }; 215 216 #define _IBMR(i2c) ((i2c)->reg_ibmr) 217 #define _IDBR(i2c) ((i2c)->reg_idbr) 218 #define _ICR(i2c) ((i2c)->reg_icr) 219 #define _ISR(i2c) ((i2c)->reg_isr) 220 #define _ISAR(i2c) ((i2c)->reg_isar) 221 #define _ILCR(i2c) ((i2c)->reg_ilcr) 222 #define _IWCR(i2c) ((i2c)->reg_iwcr) 223 224 /* 225 * I2C Slave mode address 226 */ 227 #define I2C_PXA_SLAVE_ADDR 0x1 228 229 #ifdef DEBUG 230 231 struct bits { 232 u32 mask; 233 const char *set; 234 const char *unset; 235 }; 236 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } 237 238 static inline void 239 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) 240 { 241 printk("%s %08x: ", prefix, val); 242 while (num--) { 243 const char *str = val & bits->mask ? bits->set : bits->unset; 244 if (str) 245 printk("%s ", str); 246 bits++; 247 } 248 } 249 250 static const struct bits isr_bits[] = { 251 PXA_BIT(ISR_RWM, "RX", "TX"), 252 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), 253 PXA_BIT(ISR_UB, "Bsy", "Rdy"), 254 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), 255 PXA_BIT(ISR_SSD, "SlaveStop", NULL), 256 PXA_BIT(ISR_ALD, "ALD", NULL), 257 PXA_BIT(ISR_ITE, "TxEmpty", NULL), 258 PXA_BIT(ISR_IRF, "RxFull", NULL), 259 PXA_BIT(ISR_GCAD, "GenCall", NULL), 260 PXA_BIT(ISR_SAD, "SlaveAddr", NULL), 261 PXA_BIT(ISR_BED, "BusErr", NULL), 262 }; 263 264 static void decode_ISR(unsigned int val) 265 { 266 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); 267 printk("\n"); 268 } 269 270 static const struct bits icr_bits[] = { 271 PXA_BIT(ICR_START, "START", NULL), 272 PXA_BIT(ICR_STOP, "STOP", NULL), 273 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), 274 PXA_BIT(ICR_TB, "TB", NULL), 275 PXA_BIT(ICR_MA, "MA", NULL), 276 PXA_BIT(ICR_SCLE, "SCLE", "scle"), 277 PXA_BIT(ICR_IUE, "IUE", "iue"), 278 PXA_BIT(ICR_GCD, "GCD", NULL), 279 PXA_BIT(ICR_ITEIE, "ITEIE", NULL), 280 PXA_BIT(ICR_IRFIE, "IRFIE", NULL), 281 PXA_BIT(ICR_BEIE, "BEIE", NULL), 282 PXA_BIT(ICR_SSDIE, "SSDIE", NULL), 283 PXA_BIT(ICR_ALDIE, "ALDIE", NULL), 284 PXA_BIT(ICR_SADIE, "SADIE", NULL), 285 PXA_BIT(ICR_UR, "UR", "ur"), 286 }; 287 288 #ifdef CONFIG_I2C_PXA_SLAVE 289 static void decode_ICR(unsigned int val) 290 { 291 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); 292 printk("\n"); 293 } 294 #endif 295 296 static unsigned int i2c_debug = DEBUG; 297 298 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) 299 { 300 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, 301 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 302 } 303 304 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) 305 306 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) 307 { 308 unsigned int i; 309 struct device *dev = &i2c->adap.dev; 310 311 dev_err(dev, "slave_0x%x error: %s\n", 312 i2c->req_slave_addr >> 1, why); 313 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n", 314 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); 315 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n", 316 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)), 317 readl(_ISR(i2c))); 318 dev_dbg(dev, "log: "); 319 for (i = 0; i < i2c->irqlogidx; i++) 320 pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); 321 322 pr_debug("\n"); 323 } 324 325 #else /* ifdef DEBUG */ 326 327 #define i2c_debug 0 328 329 #define show_state(i2c) do { } while (0) 330 #define decode_ISR(val) do { } while (0) 331 #define decode_ICR(val) do { } while (0) 332 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0) 333 334 #endif /* ifdef DEBUG / else */ 335 336 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); 337 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); 338 339 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) 340 { 341 return !(readl(_ICR(i2c)) & ICR_SCLE); 342 } 343 344 static void i2c_pxa_abort(struct pxa_i2c *i2c) 345 { 346 int i = 250; 347 348 if (i2c_pxa_is_slavemode(i2c)) { 349 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); 350 return; 351 } 352 353 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { 354 unsigned long icr = readl(_ICR(i2c)); 355 356 icr &= ~ICR_START; 357 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; 358 359 writel(icr, _ICR(i2c)); 360 361 show_state(i2c); 362 363 mdelay(1); 364 i --; 365 } 366 367 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), 368 _ICR(i2c)); 369 } 370 371 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) 372 { 373 int timeout = DEF_TIMEOUT; 374 375 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { 376 if ((readl(_ISR(i2c)) & ISR_SAD) != 0) 377 timeout += 4; 378 379 msleep(2); 380 show_state(i2c); 381 } 382 383 if (timeout < 0) 384 show_state(i2c); 385 386 return timeout < 0 ? I2C_RETRY : 0; 387 } 388 389 static int i2c_pxa_wait_master(struct pxa_i2c *i2c) 390 { 391 unsigned long timeout = jiffies + HZ*4; 392 393 while (time_before(jiffies, timeout)) { 394 if (i2c_debug > 1) 395 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 396 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 397 398 if (readl(_ISR(i2c)) & ISR_SAD) { 399 if (i2c_debug > 0) 400 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); 401 goto out; 402 } 403 404 /* wait for unit and bus being not busy, and we also do a 405 * quick check of the i2c lines themselves to ensure they've 406 * gone high... 407 */ 408 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { 409 if (i2c_debug > 0) 410 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 411 return 1; 412 } 413 414 msleep(1); 415 } 416 417 if (i2c_debug > 0) 418 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 419 out: 420 return 0; 421 } 422 423 static int i2c_pxa_set_master(struct pxa_i2c *i2c) 424 { 425 if (i2c_debug) 426 dev_dbg(&i2c->adap.dev, "setting to bus master\n"); 427 428 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { 429 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); 430 if (!i2c_pxa_wait_master(i2c)) { 431 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); 432 return I2C_RETRY; 433 } 434 } 435 436 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); 437 return 0; 438 } 439 440 #ifdef CONFIG_I2C_PXA_SLAVE 441 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) 442 { 443 unsigned long timeout = jiffies + HZ*1; 444 445 /* wait for stop */ 446 447 show_state(i2c); 448 449 while (time_before(jiffies, timeout)) { 450 if (i2c_debug > 1) 451 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 452 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 453 454 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || 455 (readl(_ISR(i2c)) & ISR_SAD) != 0 || 456 (readl(_ICR(i2c)) & ICR_SCLE) == 0) { 457 if (i2c_debug > 1) 458 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 459 return 1; 460 } 461 462 msleep(1); 463 } 464 465 if (i2c_debug > 0) 466 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 467 return 0; 468 } 469 470 /* 471 * clear the hold on the bus, and take of anything else 472 * that has been configured 473 */ 474 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) 475 { 476 show_state(i2c); 477 478 if (errcode < 0) { 479 udelay(100); /* simple delay */ 480 } else { 481 /* we need to wait for the stop condition to end */ 482 483 /* if we where in stop, then clear... */ 484 if (readl(_ICR(i2c)) & ICR_STOP) { 485 udelay(100); 486 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); 487 } 488 489 if (!i2c_pxa_wait_slave(i2c)) { 490 dev_err(&i2c->adap.dev, "%s: wait timedout\n", 491 __func__); 492 return; 493 } 494 } 495 496 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); 497 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 498 499 if (i2c_debug) { 500 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); 501 decode_ICR(readl(_ICR(i2c))); 502 } 503 } 504 #else 505 #define i2c_pxa_set_slave(i2c, err) do { } while (0) 506 #endif 507 508 static void i2c_pxa_reset(struct pxa_i2c *i2c) 509 { 510 pr_debug("Resetting I2C Controller Unit\n"); 511 512 /* abort any transfer currently under way */ 513 i2c_pxa_abort(i2c); 514 515 /* reset according to 9.8 */ 516 writel(ICR_UR, _ICR(i2c)); 517 writel(I2C_ISR_INIT, _ISR(i2c)); 518 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); 519 520 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE)) 521 writel(i2c->slave_addr, _ISAR(i2c)); 522 523 /* set control register values */ 524 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c)); 525 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c)); 526 527 #ifdef CONFIG_I2C_PXA_SLAVE 528 dev_info(&i2c->adap.dev, "Enabling slave mode\n"); 529 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); 530 #endif 531 532 i2c_pxa_set_slave(i2c, 0); 533 534 /* enable unit */ 535 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); 536 udelay(100); 537 } 538 539 540 #ifdef CONFIG_I2C_PXA_SLAVE 541 /* 542 * PXA I2C Slave mode 543 */ 544 545 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 546 { 547 if (isr & ISR_BED) { 548 /* what should we do here? */ 549 } else { 550 int ret = 0; 551 552 if (i2c->slave != NULL) 553 ret = i2c->slave->read(i2c->slave->data); 554 555 writel(ret, _IDBR(i2c)); 556 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ 557 } 558 } 559 560 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 561 { 562 unsigned int byte = readl(_IDBR(i2c)); 563 564 if (i2c->slave != NULL) 565 i2c->slave->write(i2c->slave->data, byte); 566 567 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 568 } 569 570 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 571 { 572 int timeout; 573 574 if (i2c_debug > 0) 575 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", 576 (isr & ISR_RWM) ? 'r' : 't'); 577 578 if (i2c->slave != NULL) 579 i2c->slave->event(i2c->slave->data, 580 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); 581 582 /* 583 * slave could interrupt in the middle of us generating a 584 * start condition... if this happens, we'd better back off 585 * and stop holding the poor thing up 586 */ 587 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); 588 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 589 590 timeout = 0x10000; 591 592 while (1) { 593 if ((readl(_IBMR(i2c)) & 2) == 2) 594 break; 595 596 timeout--; 597 598 if (timeout <= 0) { 599 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 600 break; 601 } 602 } 603 604 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 605 } 606 607 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 608 { 609 if (i2c_debug > 2) 610 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); 611 612 if (i2c->slave != NULL) 613 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); 614 615 if (i2c_debug > 2) 616 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); 617 618 /* 619 * If we have a master-mode message waiting, 620 * kick it off now that the slave has completed. 621 */ 622 if (i2c->msg) 623 i2c_pxa_master_complete(i2c, I2C_RETRY); 624 } 625 #else 626 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 627 { 628 if (isr & ISR_BED) { 629 /* what should we do here? */ 630 } else { 631 writel(0, _IDBR(i2c)); 632 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 633 } 634 } 635 636 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 637 { 638 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); 639 } 640 641 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 642 { 643 int timeout; 644 645 /* 646 * slave could interrupt in the middle of us generating a 647 * start condition... if this happens, we'd better back off 648 * and stop holding the poor thing up 649 */ 650 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); 651 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); 652 653 timeout = 0x10000; 654 655 while (1) { 656 if ((readl(_IBMR(i2c)) & 2) == 2) 657 break; 658 659 timeout--; 660 661 if (timeout <= 0) { 662 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 663 break; 664 } 665 } 666 667 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 668 } 669 670 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 671 { 672 if (i2c->msg) 673 i2c_pxa_master_complete(i2c, I2C_RETRY); 674 } 675 #endif 676 677 /* 678 * PXA I2C Master mode 679 */ 680 681 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) 682 { 683 unsigned int addr = (msg->addr & 0x7f) << 1; 684 685 if (msg->flags & I2C_M_RD) 686 addr |= 1; 687 688 return addr; 689 } 690 691 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) 692 { 693 u32 icr; 694 695 /* 696 * Step 1: target slave address into IDBR 697 */ 698 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); 699 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg); 700 701 /* 702 * Step 2: initiate the write. 703 */ 704 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); 705 writel(icr | ICR_START | ICR_TB, _ICR(i2c)); 706 } 707 708 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) 709 { 710 u32 icr; 711 712 /* 713 * Clear the STOP and ACK flags 714 */ 715 icr = readl(_ICR(i2c)); 716 icr &= ~(ICR_STOP | ICR_ACKNAK); 717 writel(icr, _ICR(i2c)); 718 } 719 720 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) 721 { 722 /* make timeout the same as for interrupt based functions */ 723 long timeout = 2 * DEF_TIMEOUT; 724 725 /* 726 * Wait for the bus to become free. 727 */ 728 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { 729 udelay(1000); 730 show_state(i2c); 731 } 732 733 if (timeout < 0) { 734 show_state(i2c); 735 dev_err(&i2c->adap.dev, 736 "i2c_pxa: timeout waiting for bus free\n"); 737 return I2C_RETRY; 738 } 739 740 /* 741 * Set master mode. 742 */ 743 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); 744 745 return 0; 746 } 747 748 /* 749 * PXA I2C send master code 750 * 1. Load master code to IDBR and send it. 751 * Note for HS mode, set ICR [GPIOEN]. 752 * 2. Wait until win arbitration. 753 */ 754 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c) 755 { 756 u32 icr; 757 long timeout; 758 759 spin_lock_irq(&i2c->lock); 760 i2c->highmode_enter = true; 761 writel(i2c->master_code, _IDBR(i2c)); 762 763 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); 764 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE; 765 writel(icr, _ICR(i2c)); 766 767 spin_unlock_irq(&i2c->lock); 768 timeout = wait_event_timeout(i2c->wait, 769 i2c->highmode_enter == false, HZ * 1); 770 771 i2c->highmode_enter = false; 772 773 return (timeout == 0) ? I2C_RETRY : 0; 774 } 775 776 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, 777 struct i2c_msg *msg, int num) 778 { 779 unsigned long timeout = 500000; /* 5 seconds */ 780 int ret = 0; 781 782 ret = i2c_pxa_pio_set_master(i2c); 783 if (ret) 784 goto out; 785 786 i2c->msg = msg; 787 i2c->msg_num = num; 788 i2c->msg_idx = 0; 789 i2c->msg_ptr = 0; 790 i2c->irqlogidx = 0; 791 792 i2c_pxa_start_message(i2c); 793 794 while (i2c->msg_num > 0 && --timeout) { 795 i2c_pxa_handler(0, i2c); 796 udelay(10); 797 } 798 799 i2c_pxa_stop_message(i2c); 800 801 /* 802 * We place the return code in i2c->msg_idx. 803 */ 804 ret = i2c->msg_idx; 805 806 out: 807 if (timeout == 0) { 808 i2c_pxa_scream_blue_murder(i2c, "timeout"); 809 ret = I2C_RETRY; 810 } 811 812 return ret; 813 } 814 815 /* 816 * We are protected by the adapter bus mutex. 817 */ 818 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) 819 { 820 long timeout; 821 int ret; 822 823 /* 824 * Wait for the bus to become free. 825 */ 826 ret = i2c_pxa_wait_bus_not_busy(i2c); 827 if (ret) { 828 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); 829 goto out; 830 } 831 832 /* 833 * Set master mode. 834 */ 835 ret = i2c_pxa_set_master(i2c); 836 if (ret) { 837 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); 838 goto out; 839 } 840 841 if (i2c->high_mode) { 842 ret = i2c_pxa_send_mastercode(i2c); 843 if (ret) { 844 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n"); 845 goto out; 846 } 847 } 848 849 spin_lock_irq(&i2c->lock); 850 851 i2c->msg = msg; 852 i2c->msg_num = num; 853 i2c->msg_idx = 0; 854 i2c->msg_ptr = 0; 855 i2c->irqlogidx = 0; 856 857 i2c_pxa_start_message(i2c); 858 859 spin_unlock_irq(&i2c->lock); 860 861 /* 862 * The rest of the processing occurs in the interrupt handler. 863 */ 864 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 865 i2c_pxa_stop_message(i2c); 866 867 /* 868 * We place the return code in i2c->msg_idx. 869 */ 870 ret = i2c->msg_idx; 871 872 if (!timeout && i2c->msg_num) { 873 i2c_pxa_scream_blue_murder(i2c, "timeout"); 874 ret = I2C_RETRY; 875 } 876 877 out: 878 return ret; 879 } 880 881 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, 882 struct i2c_msg msgs[], int num) 883 { 884 struct pxa_i2c *i2c = adap->algo_data; 885 int ret, i; 886 887 /* If the I2C controller is disabled we need to reset it 888 (probably due to a suspend/resume destroying state). We do 889 this here as we can then avoid worrying about resuming the 890 controller before its users. */ 891 if (!(readl(_ICR(i2c)) & ICR_IUE)) 892 i2c_pxa_reset(i2c); 893 894 for (i = adap->retries; i >= 0; i--) { 895 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); 896 if (ret != I2C_RETRY) 897 goto out; 898 899 if (i2c_debug) 900 dev_dbg(&adap->dev, "Retrying transmission\n"); 901 udelay(100); 902 } 903 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 904 ret = -EREMOTEIO; 905 out: 906 i2c_pxa_set_slave(i2c, ret); 907 return ret; 908 } 909 910 /* 911 * i2c_pxa_master_complete - complete the message and wake up. 912 */ 913 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) 914 { 915 i2c->msg_ptr = 0; 916 i2c->msg = NULL; 917 i2c->msg_idx ++; 918 i2c->msg_num = 0; 919 if (ret) 920 i2c->msg_idx = ret; 921 if (!i2c->use_pio) 922 wake_up(&i2c->wait); 923 } 924 925 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) 926 { 927 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 928 929 again: 930 /* 931 * If ISR_ALD is set, we lost arbitration. 932 */ 933 if (isr & ISR_ALD) { 934 /* 935 * Do we need to do anything here? The PXA docs 936 * are vague about what happens. 937 */ 938 i2c_pxa_scream_blue_murder(i2c, "ALD set"); 939 940 /* 941 * We ignore this error. We seem to see spurious ALDs 942 * for seemingly no reason. If we handle them as I think 943 * they should, we end up causing an I2C error, which 944 * is painful for some systems. 945 */ 946 return; /* ignore */ 947 } 948 949 if ((isr & ISR_BED) && 950 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) && 951 (isr & ISR_ACKNAK)))) { 952 int ret = BUS_ERROR; 953 954 /* 955 * I2C bus error - either the device NAK'd us, or 956 * something more serious happened. If we were NAK'd 957 * on the initial address phase, we can retry. 958 */ 959 if (isr & ISR_ACKNAK) { 960 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) 961 ret = I2C_RETRY; 962 else 963 ret = XFER_NAKED; 964 } 965 i2c_pxa_master_complete(i2c, ret); 966 } else if (isr & ISR_RWM) { 967 /* 968 * Read mode. We have just sent the address byte, and 969 * now we must initiate the transfer. 970 */ 971 if (i2c->msg_ptr == i2c->msg->len - 1 && 972 i2c->msg_idx == i2c->msg_num - 1) 973 icr |= ICR_STOP | ICR_ACKNAK; 974 975 icr |= ICR_ALDIE | ICR_TB; 976 } else if (i2c->msg_ptr < i2c->msg->len) { 977 /* 978 * Write mode. Write the next data byte. 979 */ 980 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); 981 982 icr |= ICR_ALDIE | ICR_TB; 983 984 /* 985 * If this is the last byte of the last message or last byte 986 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP. 987 */ 988 if ((i2c->msg_ptr == i2c->msg->len) && 989 ((i2c->msg->flags & I2C_M_STOP) || 990 (i2c->msg_idx == i2c->msg_num - 1))) 991 icr |= ICR_STOP; 992 993 } else if (i2c->msg_idx < i2c->msg_num - 1) { 994 /* 995 * Next segment of the message. 996 */ 997 i2c->msg_ptr = 0; 998 i2c->msg_idx ++; 999 i2c->msg++; 1000 1001 /* 1002 * If we aren't doing a repeated start and address, 1003 * go back and try to send the next byte. Note that 1004 * we do not support switching the R/W direction here. 1005 */ 1006 if (i2c->msg->flags & I2C_M_NOSTART) 1007 goto again; 1008 1009 /* 1010 * Write the next address. 1011 */ 1012 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); 1013 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg); 1014 1015 /* 1016 * And trigger a repeated start, and send the byte. 1017 */ 1018 icr &= ~ICR_ALDIE; 1019 icr |= ICR_START | ICR_TB; 1020 } else { 1021 if (i2c->msg->len == 0) { 1022 /* 1023 * Device probes have a message length of zero 1024 * and need the bus to be reset before it can 1025 * be used again. 1026 */ 1027 i2c_pxa_reset(i2c); 1028 } 1029 i2c_pxa_master_complete(i2c, 0); 1030 } 1031 1032 i2c->icrlog[i2c->irqlogidx-1] = icr; 1033 1034 writel(icr, _ICR(i2c)); 1035 show_state(i2c); 1036 } 1037 1038 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) 1039 { 1040 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 1041 1042 /* 1043 * Read the byte. 1044 */ 1045 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); 1046 1047 if (i2c->msg_ptr < i2c->msg->len) { 1048 /* 1049 * If this is the last byte of the last 1050 * message, send a STOP. 1051 */ 1052 if (i2c->msg_ptr == i2c->msg->len - 1) 1053 icr |= ICR_STOP | ICR_ACKNAK; 1054 1055 icr |= ICR_ALDIE | ICR_TB; 1056 } else { 1057 i2c_pxa_master_complete(i2c, 0); 1058 } 1059 1060 i2c->icrlog[i2c->irqlogidx-1] = icr; 1061 1062 writel(icr, _ICR(i2c)); 1063 } 1064 1065 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \ 1066 ISR_SAD | ISR_BED) 1067 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) 1068 { 1069 struct pxa_i2c *i2c = dev_id; 1070 u32 isr = readl(_ISR(i2c)); 1071 1072 if (!(isr & VALID_INT_SOURCE)) 1073 return IRQ_NONE; 1074 1075 if (i2c_debug > 2 && 0) { 1076 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", 1077 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); 1078 decode_ISR(isr); 1079 } 1080 1081 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) 1082 i2c->isrlog[i2c->irqlogidx++] = isr; 1083 1084 show_state(i2c); 1085 1086 /* 1087 * Always clear all pending IRQs. 1088 */ 1089 writel(isr & VALID_INT_SOURCE, _ISR(i2c)); 1090 1091 if (isr & ISR_SAD) 1092 i2c_pxa_slave_start(i2c, isr); 1093 if (isr & ISR_SSD) 1094 i2c_pxa_slave_stop(i2c); 1095 1096 if (i2c_pxa_is_slavemode(i2c)) { 1097 if (isr & ISR_ITE) 1098 i2c_pxa_slave_txempty(i2c, isr); 1099 if (isr & ISR_IRF) 1100 i2c_pxa_slave_rxfull(i2c, isr); 1101 } else if (i2c->msg && (!i2c->highmode_enter)) { 1102 if (isr & ISR_ITE) 1103 i2c_pxa_irq_txempty(i2c, isr); 1104 if (isr & ISR_IRF) 1105 i2c_pxa_irq_rxfull(i2c, isr); 1106 } else if ((isr & ISR_ITE) && i2c->highmode_enter) { 1107 i2c->highmode_enter = false; 1108 wake_up(&i2c->wait); 1109 } else { 1110 i2c_pxa_scream_blue_murder(i2c, "spurious irq"); 1111 } 1112 1113 return IRQ_HANDLED; 1114 } 1115 1116 1117 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 1118 { 1119 struct pxa_i2c *i2c = adap->algo_data; 1120 int ret, i; 1121 1122 for (i = adap->retries; i >= 0; i--) { 1123 ret = i2c_pxa_do_xfer(i2c, msgs, num); 1124 if (ret != I2C_RETRY) 1125 goto out; 1126 1127 if (i2c_debug) 1128 dev_dbg(&adap->dev, "Retrying transmission\n"); 1129 udelay(100); 1130 } 1131 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 1132 ret = -EREMOTEIO; 1133 out: 1134 i2c_pxa_set_slave(i2c, ret); 1135 return ret; 1136 } 1137 1138 static u32 i2c_pxa_functionality(struct i2c_adapter *adap) 1139 { 1140 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1141 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART; 1142 } 1143 1144 static const struct i2c_algorithm i2c_pxa_algorithm = { 1145 .master_xfer = i2c_pxa_xfer, 1146 .functionality = i2c_pxa_functionality, 1147 }; 1148 1149 static const struct i2c_algorithm i2c_pxa_pio_algorithm = { 1150 .master_xfer = i2c_pxa_pio_xfer, 1151 .functionality = i2c_pxa_functionality, 1152 }; 1153 1154 static const struct of_device_id i2c_pxa_dt_ids[] = { 1155 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX }, 1156 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX }, 1157 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 }, 1158 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 }, 1159 {} 1160 }; 1161 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); 1162 1163 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c, 1164 enum pxa_i2c_types *i2c_types) 1165 { 1166 struct device_node *np = pdev->dev.of_node; 1167 const struct of_device_id *of_id = 1168 of_match_device(i2c_pxa_dt_ids, &pdev->dev); 1169 1170 if (!of_id) 1171 return 1; 1172 1173 /* For device tree we always use the dynamic or alias-assigned ID */ 1174 i2c->adap.nr = -1; 1175 1176 if (of_get_property(np, "mrvl,i2c-polling", NULL)) 1177 i2c->use_pio = 1; 1178 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL)) 1179 i2c->fast_mode = 1; 1180 1181 *i2c_types = (enum pxa_i2c_types)(of_id->data); 1182 1183 return 0; 1184 } 1185 1186 static int i2c_pxa_probe_pdata(struct platform_device *pdev, 1187 struct pxa_i2c *i2c, 1188 enum pxa_i2c_types *i2c_types) 1189 { 1190 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev); 1191 const struct platform_device_id *id = platform_get_device_id(pdev); 1192 1193 *i2c_types = id->driver_data; 1194 if (plat) { 1195 i2c->use_pio = plat->use_pio; 1196 i2c->fast_mode = plat->fast_mode; 1197 i2c->high_mode = plat->high_mode; 1198 i2c->master_code = plat->master_code; 1199 if (!i2c->master_code) 1200 i2c->master_code = 0xe; 1201 i2c->rate = plat->rate; 1202 } 1203 return 0; 1204 } 1205 1206 static int i2c_pxa_probe(struct platform_device *dev) 1207 { 1208 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev); 1209 enum pxa_i2c_types i2c_type; 1210 struct pxa_i2c *i2c; 1211 struct resource *res = NULL; 1212 int ret, irq; 1213 1214 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL); 1215 if (!i2c) 1216 return -ENOMEM; 1217 1218 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1219 i2c->reg_base = devm_ioremap_resource(&dev->dev, res); 1220 if (IS_ERR(i2c->reg_base)) 1221 return PTR_ERR(i2c->reg_base); 1222 1223 irq = platform_get_irq(dev, 0); 1224 if (irq < 0) { 1225 dev_err(&dev->dev, "no irq resource: %d\n", irq); 1226 return irq; 1227 } 1228 1229 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */ 1230 i2c->adap.nr = dev->id; 1231 1232 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type); 1233 if (ret > 0) 1234 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type); 1235 if (ret < 0) 1236 return ret; 1237 1238 i2c->adap.owner = THIS_MODULE; 1239 i2c->adap.retries = 5; 1240 1241 spin_lock_init(&i2c->lock); 1242 init_waitqueue_head(&i2c->wait); 1243 1244 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); 1245 1246 i2c->clk = devm_clk_get(&dev->dev, NULL); 1247 if (IS_ERR(i2c->clk)) { 1248 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk)); 1249 return PTR_ERR(i2c->clk); 1250 } 1251 1252 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; 1253 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; 1254 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; 1255 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; 1256 i2c->fm_mask = pxa_reg_layout[i2c_type].fm ? : ICR_FM; 1257 i2c->hs_mask = pxa_reg_layout[i2c_type].hs ? : ICR_HS; 1258 1259 if (i2c_type != REGS_CE4100) 1260 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; 1261 1262 if (i2c_type == REGS_PXA910) { 1263 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr; 1264 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr; 1265 } 1266 1267 i2c->iobase = res->start; 1268 i2c->iosize = resource_size(res); 1269 1270 i2c->irq = irq; 1271 1272 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 1273 i2c->highmode_enter = false; 1274 1275 if (plat) { 1276 #ifdef CONFIG_I2C_PXA_SLAVE 1277 i2c->slave_addr = plat->slave_addr; 1278 i2c->slave = plat->slave; 1279 #endif 1280 i2c->adap.class = plat->class; 1281 } 1282 1283 if (i2c->high_mode) { 1284 if (i2c->rate) { 1285 clk_set_rate(i2c->clk, i2c->rate); 1286 pr_info("i2c: <%s> set rate to %ld\n", 1287 i2c->adap.name, clk_get_rate(i2c->clk)); 1288 } else 1289 pr_warn("i2c: <%s> clock rate not set\n", 1290 i2c->adap.name); 1291 } 1292 1293 clk_prepare_enable(i2c->clk); 1294 1295 if (i2c->use_pio) { 1296 i2c->adap.algo = &i2c_pxa_pio_algorithm; 1297 } else { 1298 i2c->adap.algo = &i2c_pxa_algorithm; 1299 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler, 1300 IRQF_SHARED | IRQF_NO_SUSPEND, 1301 dev_name(&dev->dev), i2c); 1302 if (ret) { 1303 dev_err(&dev->dev, "failed to request irq: %d\n", ret); 1304 goto ereqirq; 1305 } 1306 } 1307 1308 i2c_pxa_reset(i2c); 1309 1310 i2c->adap.algo_data = i2c; 1311 i2c->adap.dev.parent = &dev->dev; 1312 #ifdef CONFIG_OF 1313 i2c->adap.dev.of_node = dev->dev.of_node; 1314 #endif 1315 1316 ret = i2c_add_numbered_adapter(&i2c->adap); 1317 if (ret < 0) 1318 goto ereqirq; 1319 1320 platform_set_drvdata(dev, i2c); 1321 1322 #ifdef CONFIG_I2C_PXA_SLAVE 1323 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n", 1324 i2c->slave_addr); 1325 #else 1326 dev_info(&i2c->adap.dev, " PXA I2C adapter\n"); 1327 #endif 1328 return 0; 1329 1330 ereqirq: 1331 clk_disable_unprepare(i2c->clk); 1332 return ret; 1333 } 1334 1335 static int i2c_pxa_remove(struct platform_device *dev) 1336 { 1337 struct pxa_i2c *i2c = platform_get_drvdata(dev); 1338 1339 i2c_del_adapter(&i2c->adap); 1340 1341 clk_disable_unprepare(i2c->clk); 1342 1343 return 0; 1344 } 1345 1346 #ifdef CONFIG_PM 1347 static int i2c_pxa_suspend_noirq(struct device *dev) 1348 { 1349 struct platform_device *pdev = to_platform_device(dev); 1350 struct pxa_i2c *i2c = platform_get_drvdata(pdev); 1351 1352 clk_disable(i2c->clk); 1353 1354 return 0; 1355 } 1356 1357 static int i2c_pxa_resume_noirq(struct device *dev) 1358 { 1359 struct platform_device *pdev = to_platform_device(dev); 1360 struct pxa_i2c *i2c = platform_get_drvdata(pdev); 1361 1362 clk_enable(i2c->clk); 1363 i2c_pxa_reset(i2c); 1364 1365 return 0; 1366 } 1367 1368 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = { 1369 .suspend_noirq = i2c_pxa_suspend_noirq, 1370 .resume_noirq = i2c_pxa_resume_noirq, 1371 }; 1372 1373 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops) 1374 #else 1375 #define I2C_PXA_DEV_PM_OPS NULL 1376 #endif 1377 1378 static struct platform_driver i2c_pxa_driver = { 1379 .probe = i2c_pxa_probe, 1380 .remove = i2c_pxa_remove, 1381 .driver = { 1382 .name = "pxa2xx-i2c", 1383 .pm = I2C_PXA_DEV_PM_OPS, 1384 .of_match_table = i2c_pxa_dt_ids, 1385 }, 1386 .id_table = i2c_pxa_id_table, 1387 }; 1388 1389 static int __init i2c_adap_pxa_init(void) 1390 { 1391 return platform_driver_register(&i2c_pxa_driver); 1392 } 1393 1394 static void __exit i2c_adap_pxa_exit(void) 1395 { 1396 platform_driver_unregister(&i2c_pxa_driver); 1397 } 1398 1399 MODULE_LICENSE("GPL"); 1400 MODULE_ALIAS("platform:pxa2xx-i2c"); 1401 1402 subsys_initcall(i2c_adap_pxa_init); 1403 module_exit(i2c_adap_pxa_exit); 1404