1 /* 2 * i2c_adap_pxa.c 3 * 4 * I2C adapter for the PXA I2C bus access. 5 * 6 * Copyright (C) 2002 Intrinsyc Software Inc. 7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * History: 14 * Apr 2002: Initial version [CS] 15 * Jun 2002: Properly separated algo/adap [FB] 16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] 17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem] 18 * Sep 2004: Major rework to ensure efficient bus handling [RMK] 19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] 20 * Feb 2005: Rework slave mode handling [RMK] 21 */ 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/i2c.h> 25 #include <linux/init.h> 26 #include <linux/time.h> 27 #include <linux/sched.h> 28 #include <linux/delay.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/i2c-pxa.h> 32 #include <linux/of_i2c.h> 33 #include <linux/platform_device.h> 34 #include <linux/err.h> 35 #include <linux/clk.h> 36 #include <linux/slab.h> 37 #include <linux/io.h> 38 #include <linux/i2c/pxa-i2c.h> 39 40 #include <asm/irq.h> 41 42 #ifndef CONFIG_HAVE_CLK 43 #define clk_get(dev, id) NULL 44 #define clk_put(clk) do { } while (0) 45 #define clk_disable(clk) do { } while (0) 46 #define clk_enable(clk) do { } while (0) 47 #endif 48 49 struct pxa_reg_layout { 50 u32 ibmr; 51 u32 idbr; 52 u32 icr; 53 u32 isr; 54 u32 isar; 55 }; 56 57 enum pxa_i2c_types { 58 REGS_PXA2XX, 59 REGS_PXA3XX, 60 REGS_CE4100, 61 }; 62 63 /* 64 * I2C registers definitions 65 */ 66 static struct pxa_reg_layout pxa_reg_layout[] = { 67 [REGS_PXA2XX] = { 68 .ibmr = 0x00, 69 .idbr = 0x08, 70 .icr = 0x10, 71 .isr = 0x18, 72 .isar = 0x20, 73 }, 74 [REGS_PXA3XX] = { 75 .ibmr = 0x00, 76 .idbr = 0x04, 77 .icr = 0x08, 78 .isr = 0x0c, 79 .isar = 0x10, 80 }, 81 [REGS_CE4100] = { 82 .ibmr = 0x14, 83 .idbr = 0x0c, 84 .icr = 0x00, 85 .isr = 0x04, 86 /* no isar register */ 87 }, 88 }; 89 90 static const struct platform_device_id i2c_pxa_id_table[] = { 91 { "pxa2xx-i2c", REGS_PXA2XX }, 92 { "pxa3xx-pwri2c", REGS_PXA3XX }, 93 { "ce4100-i2c", REGS_CE4100 }, 94 { }, 95 }; 96 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); 97 98 /* 99 * I2C bit definitions 100 */ 101 102 #define ICR_START (1 << 0) /* start bit */ 103 #define ICR_STOP (1 << 1) /* stop bit */ 104 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ 105 #define ICR_TB (1 << 3) /* transfer byte bit */ 106 #define ICR_MA (1 << 4) /* master abort */ 107 #define ICR_SCLE (1 << 5) /* master clock enable */ 108 #define ICR_IUE (1 << 6) /* unit enable */ 109 #define ICR_GCD (1 << 7) /* general call disable */ 110 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ 111 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ 112 #define ICR_BEIE (1 << 10) /* enable bus error ints */ 113 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ 114 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ 115 #define ICR_SADIE (1 << 13) /* slave address detected int enable */ 116 #define ICR_UR (1 << 14) /* unit reset */ 117 #define ICR_FM (1 << 15) /* fast mode */ 118 119 #define ISR_RWM (1 << 0) /* read/write mode */ 120 #define ISR_ACKNAK (1 << 1) /* ack/nak status */ 121 #define ISR_UB (1 << 2) /* unit busy */ 122 #define ISR_IBB (1 << 3) /* bus busy */ 123 #define ISR_SSD (1 << 4) /* slave stop detected */ 124 #define ISR_ALD (1 << 5) /* arbitration loss detected */ 125 #define ISR_ITE (1 << 6) /* tx buffer empty */ 126 #define ISR_IRF (1 << 7) /* rx buffer full */ 127 #define ISR_GCAD (1 << 8) /* general call address detected */ 128 #define ISR_SAD (1 << 9) /* slave address detected */ 129 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ 130 131 struct pxa_i2c { 132 spinlock_t lock; 133 wait_queue_head_t wait; 134 struct i2c_msg *msg; 135 unsigned int msg_num; 136 unsigned int msg_idx; 137 unsigned int msg_ptr; 138 unsigned int slave_addr; 139 140 struct i2c_adapter adap; 141 struct clk *clk; 142 #ifdef CONFIG_I2C_PXA_SLAVE 143 struct i2c_slave_client *slave; 144 #endif 145 146 unsigned int irqlogidx; 147 u32 isrlog[32]; 148 u32 icrlog[32]; 149 150 void __iomem *reg_base; 151 void __iomem *reg_ibmr; 152 void __iomem *reg_idbr; 153 void __iomem *reg_icr; 154 void __iomem *reg_isr; 155 void __iomem *reg_isar; 156 157 unsigned long iobase; 158 unsigned long iosize; 159 160 int irq; 161 unsigned int use_pio :1; 162 unsigned int fast_mode :1; 163 }; 164 165 #define _IBMR(i2c) ((i2c)->reg_ibmr) 166 #define _IDBR(i2c) ((i2c)->reg_idbr) 167 #define _ICR(i2c) ((i2c)->reg_icr) 168 #define _ISR(i2c) ((i2c)->reg_isr) 169 #define _ISAR(i2c) ((i2c)->reg_isar) 170 171 /* 172 * I2C Slave mode address 173 */ 174 #define I2C_PXA_SLAVE_ADDR 0x1 175 176 #ifdef DEBUG 177 178 struct bits { 179 u32 mask; 180 const char *set; 181 const char *unset; 182 }; 183 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } 184 185 static inline void 186 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) 187 { 188 printk("%s %08x: ", prefix, val); 189 while (num--) { 190 const char *str = val & bits->mask ? bits->set : bits->unset; 191 if (str) 192 printk("%s ", str); 193 bits++; 194 } 195 } 196 197 static const struct bits isr_bits[] = { 198 PXA_BIT(ISR_RWM, "RX", "TX"), 199 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), 200 PXA_BIT(ISR_UB, "Bsy", "Rdy"), 201 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), 202 PXA_BIT(ISR_SSD, "SlaveStop", NULL), 203 PXA_BIT(ISR_ALD, "ALD", NULL), 204 PXA_BIT(ISR_ITE, "TxEmpty", NULL), 205 PXA_BIT(ISR_IRF, "RxFull", NULL), 206 PXA_BIT(ISR_GCAD, "GenCall", NULL), 207 PXA_BIT(ISR_SAD, "SlaveAddr", NULL), 208 PXA_BIT(ISR_BED, "BusErr", NULL), 209 }; 210 211 static void decode_ISR(unsigned int val) 212 { 213 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); 214 printk("\n"); 215 } 216 217 static const struct bits icr_bits[] = { 218 PXA_BIT(ICR_START, "START", NULL), 219 PXA_BIT(ICR_STOP, "STOP", NULL), 220 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), 221 PXA_BIT(ICR_TB, "TB", NULL), 222 PXA_BIT(ICR_MA, "MA", NULL), 223 PXA_BIT(ICR_SCLE, "SCLE", "scle"), 224 PXA_BIT(ICR_IUE, "IUE", "iue"), 225 PXA_BIT(ICR_GCD, "GCD", NULL), 226 PXA_BIT(ICR_ITEIE, "ITEIE", NULL), 227 PXA_BIT(ICR_IRFIE, "IRFIE", NULL), 228 PXA_BIT(ICR_BEIE, "BEIE", NULL), 229 PXA_BIT(ICR_SSDIE, "SSDIE", NULL), 230 PXA_BIT(ICR_ALDIE, "ALDIE", NULL), 231 PXA_BIT(ICR_SADIE, "SADIE", NULL), 232 PXA_BIT(ICR_UR, "UR", "ur"), 233 }; 234 235 #ifdef CONFIG_I2C_PXA_SLAVE 236 static void decode_ICR(unsigned int val) 237 { 238 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); 239 printk("\n"); 240 } 241 #endif 242 243 static unsigned int i2c_debug = DEBUG; 244 245 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) 246 { 247 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, 248 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 249 } 250 251 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) 252 253 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) 254 { 255 unsigned int i; 256 printk(KERN_ERR "i2c: error: %s\n", why); 257 printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", 258 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); 259 printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n", 260 readl(_ICR(i2c)), readl(_ISR(i2c))); 261 printk(KERN_DEBUG "i2c: log: "); 262 for (i = 0; i < i2c->irqlogidx; i++) 263 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); 264 printk("\n"); 265 } 266 267 #else /* ifdef DEBUG */ 268 269 #define i2c_debug 0 270 271 #define show_state(i2c) do { } while (0) 272 #define decode_ISR(val) do { } while (0) 273 #define decode_ICR(val) do { } while (0) 274 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0) 275 276 #endif /* ifdef DEBUG / else */ 277 278 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); 279 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); 280 281 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) 282 { 283 return !(readl(_ICR(i2c)) & ICR_SCLE); 284 } 285 286 static void i2c_pxa_abort(struct pxa_i2c *i2c) 287 { 288 int i = 250; 289 290 if (i2c_pxa_is_slavemode(i2c)) { 291 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); 292 return; 293 } 294 295 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { 296 unsigned long icr = readl(_ICR(i2c)); 297 298 icr &= ~ICR_START; 299 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; 300 301 writel(icr, _ICR(i2c)); 302 303 show_state(i2c); 304 305 mdelay(1); 306 i --; 307 } 308 309 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), 310 _ICR(i2c)); 311 } 312 313 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) 314 { 315 int timeout = DEF_TIMEOUT; 316 317 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { 318 if ((readl(_ISR(i2c)) & ISR_SAD) != 0) 319 timeout += 4; 320 321 msleep(2); 322 show_state(i2c); 323 } 324 325 if (timeout < 0) 326 show_state(i2c); 327 328 return timeout < 0 ? I2C_RETRY : 0; 329 } 330 331 static int i2c_pxa_wait_master(struct pxa_i2c *i2c) 332 { 333 unsigned long timeout = jiffies + HZ*4; 334 335 while (time_before(jiffies, timeout)) { 336 if (i2c_debug > 1) 337 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 338 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 339 340 if (readl(_ISR(i2c)) & ISR_SAD) { 341 if (i2c_debug > 0) 342 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); 343 goto out; 344 } 345 346 /* wait for unit and bus being not busy, and we also do a 347 * quick check of the i2c lines themselves to ensure they've 348 * gone high... 349 */ 350 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { 351 if (i2c_debug > 0) 352 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 353 return 1; 354 } 355 356 msleep(1); 357 } 358 359 if (i2c_debug > 0) 360 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 361 out: 362 return 0; 363 } 364 365 static int i2c_pxa_set_master(struct pxa_i2c *i2c) 366 { 367 if (i2c_debug) 368 dev_dbg(&i2c->adap.dev, "setting to bus master\n"); 369 370 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { 371 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); 372 if (!i2c_pxa_wait_master(i2c)) { 373 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); 374 return I2C_RETRY; 375 } 376 } 377 378 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); 379 return 0; 380 } 381 382 #ifdef CONFIG_I2C_PXA_SLAVE 383 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) 384 { 385 unsigned long timeout = jiffies + HZ*1; 386 387 /* wait for stop */ 388 389 show_state(i2c); 390 391 while (time_before(jiffies, timeout)) { 392 if (i2c_debug > 1) 393 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 394 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 395 396 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || 397 (readl(_ISR(i2c)) & ISR_SAD) != 0 || 398 (readl(_ICR(i2c)) & ICR_SCLE) == 0) { 399 if (i2c_debug > 1) 400 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 401 return 1; 402 } 403 404 msleep(1); 405 } 406 407 if (i2c_debug > 0) 408 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 409 return 0; 410 } 411 412 /* 413 * clear the hold on the bus, and take of anything else 414 * that has been configured 415 */ 416 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) 417 { 418 show_state(i2c); 419 420 if (errcode < 0) { 421 udelay(100); /* simple delay */ 422 } else { 423 /* we need to wait for the stop condition to end */ 424 425 /* if we where in stop, then clear... */ 426 if (readl(_ICR(i2c)) & ICR_STOP) { 427 udelay(100); 428 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); 429 } 430 431 if (!i2c_pxa_wait_slave(i2c)) { 432 dev_err(&i2c->adap.dev, "%s: wait timedout\n", 433 __func__); 434 return; 435 } 436 } 437 438 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); 439 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 440 441 if (i2c_debug) { 442 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); 443 decode_ICR(readl(_ICR(i2c))); 444 } 445 } 446 #else 447 #define i2c_pxa_set_slave(i2c, err) do { } while (0) 448 #endif 449 450 static void i2c_pxa_reset(struct pxa_i2c *i2c) 451 { 452 pr_debug("Resetting I2C Controller Unit\n"); 453 454 /* abort any transfer currently under way */ 455 i2c_pxa_abort(i2c); 456 457 /* reset according to 9.8 */ 458 writel(ICR_UR, _ICR(i2c)); 459 writel(I2C_ISR_INIT, _ISR(i2c)); 460 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); 461 462 if (i2c->reg_isar) 463 writel(i2c->slave_addr, _ISAR(i2c)); 464 465 /* set control register values */ 466 writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c)); 467 468 #ifdef CONFIG_I2C_PXA_SLAVE 469 dev_info(&i2c->adap.dev, "Enabling slave mode\n"); 470 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); 471 #endif 472 473 i2c_pxa_set_slave(i2c, 0); 474 475 /* enable unit */ 476 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); 477 udelay(100); 478 } 479 480 481 #ifdef CONFIG_I2C_PXA_SLAVE 482 /* 483 * PXA I2C Slave mode 484 */ 485 486 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 487 { 488 if (isr & ISR_BED) { 489 /* what should we do here? */ 490 } else { 491 int ret = 0; 492 493 if (i2c->slave != NULL) 494 ret = i2c->slave->read(i2c->slave->data); 495 496 writel(ret, _IDBR(i2c)); 497 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ 498 } 499 } 500 501 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 502 { 503 unsigned int byte = readl(_IDBR(i2c)); 504 505 if (i2c->slave != NULL) 506 i2c->slave->write(i2c->slave->data, byte); 507 508 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 509 } 510 511 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 512 { 513 int timeout; 514 515 if (i2c_debug > 0) 516 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", 517 (isr & ISR_RWM) ? 'r' : 't'); 518 519 if (i2c->slave != NULL) 520 i2c->slave->event(i2c->slave->data, 521 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); 522 523 /* 524 * slave could interrupt in the middle of us generating a 525 * start condition... if this happens, we'd better back off 526 * and stop holding the poor thing up 527 */ 528 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); 529 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 530 531 timeout = 0x10000; 532 533 while (1) { 534 if ((readl(_IBMR(i2c)) & 2) == 2) 535 break; 536 537 timeout--; 538 539 if (timeout <= 0) { 540 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 541 break; 542 } 543 } 544 545 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 546 } 547 548 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 549 { 550 if (i2c_debug > 2) 551 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); 552 553 if (i2c->slave != NULL) 554 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); 555 556 if (i2c_debug > 2) 557 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); 558 559 /* 560 * If we have a master-mode message waiting, 561 * kick it off now that the slave has completed. 562 */ 563 if (i2c->msg) 564 i2c_pxa_master_complete(i2c, I2C_RETRY); 565 } 566 #else 567 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 568 { 569 if (isr & ISR_BED) { 570 /* what should we do here? */ 571 } else { 572 writel(0, _IDBR(i2c)); 573 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 574 } 575 } 576 577 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 578 { 579 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); 580 } 581 582 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 583 { 584 int timeout; 585 586 /* 587 * slave could interrupt in the middle of us generating a 588 * start condition... if this happens, we'd better back off 589 * and stop holding the poor thing up 590 */ 591 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); 592 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); 593 594 timeout = 0x10000; 595 596 while (1) { 597 if ((readl(_IBMR(i2c)) & 2) == 2) 598 break; 599 600 timeout--; 601 602 if (timeout <= 0) { 603 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 604 break; 605 } 606 } 607 608 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 609 } 610 611 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 612 { 613 if (i2c->msg) 614 i2c_pxa_master_complete(i2c, I2C_RETRY); 615 } 616 #endif 617 618 /* 619 * PXA I2C Master mode 620 */ 621 622 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) 623 { 624 unsigned int addr = (msg->addr & 0x7f) << 1; 625 626 if (msg->flags & I2C_M_RD) 627 addr |= 1; 628 629 return addr; 630 } 631 632 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) 633 { 634 u32 icr; 635 636 /* 637 * Step 1: target slave address into IDBR 638 */ 639 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); 640 641 /* 642 * Step 2: initiate the write. 643 */ 644 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); 645 writel(icr | ICR_START | ICR_TB, _ICR(i2c)); 646 } 647 648 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) 649 { 650 u32 icr; 651 652 /* 653 * Clear the STOP and ACK flags 654 */ 655 icr = readl(_ICR(i2c)); 656 icr &= ~(ICR_STOP | ICR_ACKNAK); 657 writel(icr, _ICR(i2c)); 658 } 659 660 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) 661 { 662 /* make timeout the same as for interrupt based functions */ 663 long timeout = 2 * DEF_TIMEOUT; 664 665 /* 666 * Wait for the bus to become free. 667 */ 668 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { 669 udelay(1000); 670 show_state(i2c); 671 } 672 673 if (timeout < 0) { 674 show_state(i2c); 675 dev_err(&i2c->adap.dev, 676 "i2c_pxa: timeout waiting for bus free\n"); 677 return I2C_RETRY; 678 } 679 680 /* 681 * Set master mode. 682 */ 683 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); 684 685 return 0; 686 } 687 688 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, 689 struct i2c_msg *msg, int num) 690 { 691 unsigned long timeout = 500000; /* 5 seconds */ 692 int ret = 0; 693 694 ret = i2c_pxa_pio_set_master(i2c); 695 if (ret) 696 goto out; 697 698 i2c->msg = msg; 699 i2c->msg_num = num; 700 i2c->msg_idx = 0; 701 i2c->msg_ptr = 0; 702 i2c->irqlogidx = 0; 703 704 i2c_pxa_start_message(i2c); 705 706 while (i2c->msg_num > 0 && --timeout) { 707 i2c_pxa_handler(0, i2c); 708 udelay(10); 709 } 710 711 i2c_pxa_stop_message(i2c); 712 713 /* 714 * We place the return code in i2c->msg_idx. 715 */ 716 ret = i2c->msg_idx; 717 718 out: 719 if (timeout == 0) 720 i2c_pxa_scream_blue_murder(i2c, "timeout"); 721 722 return ret; 723 } 724 725 /* 726 * We are protected by the adapter bus mutex. 727 */ 728 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) 729 { 730 long timeout; 731 int ret; 732 733 /* 734 * Wait for the bus to become free. 735 */ 736 ret = i2c_pxa_wait_bus_not_busy(i2c); 737 if (ret) { 738 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); 739 goto out; 740 } 741 742 /* 743 * Set master mode. 744 */ 745 ret = i2c_pxa_set_master(i2c); 746 if (ret) { 747 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); 748 goto out; 749 } 750 751 spin_lock_irq(&i2c->lock); 752 753 i2c->msg = msg; 754 i2c->msg_num = num; 755 i2c->msg_idx = 0; 756 i2c->msg_ptr = 0; 757 i2c->irqlogidx = 0; 758 759 i2c_pxa_start_message(i2c); 760 761 spin_unlock_irq(&i2c->lock); 762 763 /* 764 * The rest of the processing occurs in the interrupt handler. 765 */ 766 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 767 i2c_pxa_stop_message(i2c); 768 769 /* 770 * We place the return code in i2c->msg_idx. 771 */ 772 ret = i2c->msg_idx; 773 774 if (!timeout && i2c->msg_num) { 775 i2c_pxa_scream_blue_murder(i2c, "timeout"); 776 ret = I2C_RETRY; 777 } 778 779 out: 780 return ret; 781 } 782 783 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, 784 struct i2c_msg msgs[], int num) 785 { 786 struct pxa_i2c *i2c = adap->algo_data; 787 int ret, i; 788 789 /* If the I2C controller is disabled we need to reset it 790 (probably due to a suspend/resume destroying state). We do 791 this here as we can then avoid worrying about resuming the 792 controller before its users. */ 793 if (!(readl(_ICR(i2c)) & ICR_IUE)) 794 i2c_pxa_reset(i2c); 795 796 for (i = adap->retries; i >= 0; i--) { 797 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); 798 if (ret != I2C_RETRY) 799 goto out; 800 801 if (i2c_debug) 802 dev_dbg(&adap->dev, "Retrying transmission\n"); 803 udelay(100); 804 } 805 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 806 ret = -EREMOTEIO; 807 out: 808 i2c_pxa_set_slave(i2c, ret); 809 return ret; 810 } 811 812 /* 813 * i2c_pxa_master_complete - complete the message and wake up. 814 */ 815 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) 816 { 817 i2c->msg_ptr = 0; 818 i2c->msg = NULL; 819 i2c->msg_idx ++; 820 i2c->msg_num = 0; 821 if (ret) 822 i2c->msg_idx = ret; 823 if (!i2c->use_pio) 824 wake_up(&i2c->wait); 825 } 826 827 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) 828 { 829 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 830 831 again: 832 /* 833 * If ISR_ALD is set, we lost arbitration. 834 */ 835 if (isr & ISR_ALD) { 836 /* 837 * Do we need to do anything here? The PXA docs 838 * are vague about what happens. 839 */ 840 i2c_pxa_scream_blue_murder(i2c, "ALD set"); 841 842 /* 843 * We ignore this error. We seem to see spurious ALDs 844 * for seemingly no reason. If we handle them as I think 845 * they should, we end up causing an I2C error, which 846 * is painful for some systems. 847 */ 848 return; /* ignore */ 849 } 850 851 if (isr & ISR_BED) { 852 int ret = BUS_ERROR; 853 854 /* 855 * I2C bus error - either the device NAK'd us, or 856 * something more serious happened. If we were NAK'd 857 * on the initial address phase, we can retry. 858 */ 859 if (isr & ISR_ACKNAK) { 860 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) 861 ret = I2C_RETRY; 862 else 863 ret = XFER_NAKED; 864 } 865 i2c_pxa_master_complete(i2c, ret); 866 } else if (isr & ISR_RWM) { 867 /* 868 * Read mode. We have just sent the address byte, and 869 * now we must initiate the transfer. 870 */ 871 if (i2c->msg_ptr == i2c->msg->len - 1 && 872 i2c->msg_idx == i2c->msg_num - 1) 873 icr |= ICR_STOP | ICR_ACKNAK; 874 875 icr |= ICR_ALDIE | ICR_TB; 876 } else if (i2c->msg_ptr < i2c->msg->len) { 877 /* 878 * Write mode. Write the next data byte. 879 */ 880 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); 881 882 icr |= ICR_ALDIE | ICR_TB; 883 884 /* 885 * If this is the last byte of the last message, send 886 * a STOP. 887 */ 888 if (i2c->msg_ptr == i2c->msg->len && 889 i2c->msg_idx == i2c->msg_num - 1) 890 icr |= ICR_STOP; 891 } else if (i2c->msg_idx < i2c->msg_num - 1) { 892 /* 893 * Next segment of the message. 894 */ 895 i2c->msg_ptr = 0; 896 i2c->msg_idx ++; 897 i2c->msg++; 898 899 /* 900 * If we aren't doing a repeated start and address, 901 * go back and try to send the next byte. Note that 902 * we do not support switching the R/W direction here. 903 */ 904 if (i2c->msg->flags & I2C_M_NOSTART) 905 goto again; 906 907 /* 908 * Write the next address. 909 */ 910 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); 911 912 /* 913 * And trigger a repeated start, and send the byte. 914 */ 915 icr &= ~ICR_ALDIE; 916 icr |= ICR_START | ICR_TB; 917 } else { 918 if (i2c->msg->len == 0) { 919 /* 920 * Device probes have a message length of zero 921 * and need the bus to be reset before it can 922 * be used again. 923 */ 924 i2c_pxa_reset(i2c); 925 } 926 i2c_pxa_master_complete(i2c, 0); 927 } 928 929 i2c->icrlog[i2c->irqlogidx-1] = icr; 930 931 writel(icr, _ICR(i2c)); 932 show_state(i2c); 933 } 934 935 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) 936 { 937 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 938 939 /* 940 * Read the byte. 941 */ 942 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); 943 944 if (i2c->msg_ptr < i2c->msg->len) { 945 /* 946 * If this is the last byte of the last 947 * message, send a STOP. 948 */ 949 if (i2c->msg_ptr == i2c->msg->len - 1) 950 icr |= ICR_STOP | ICR_ACKNAK; 951 952 icr |= ICR_ALDIE | ICR_TB; 953 } else { 954 i2c_pxa_master_complete(i2c, 0); 955 } 956 957 i2c->icrlog[i2c->irqlogidx-1] = icr; 958 959 writel(icr, _ICR(i2c)); 960 } 961 962 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \ 963 ISR_SAD | ISR_BED) 964 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) 965 { 966 struct pxa_i2c *i2c = dev_id; 967 u32 isr = readl(_ISR(i2c)); 968 969 if (!(isr & VALID_INT_SOURCE)) 970 return IRQ_NONE; 971 972 if (i2c_debug > 2 && 0) { 973 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", 974 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); 975 decode_ISR(isr); 976 } 977 978 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) 979 i2c->isrlog[i2c->irqlogidx++] = isr; 980 981 show_state(i2c); 982 983 /* 984 * Always clear all pending IRQs. 985 */ 986 writel(isr & VALID_INT_SOURCE, _ISR(i2c)); 987 988 if (isr & ISR_SAD) 989 i2c_pxa_slave_start(i2c, isr); 990 if (isr & ISR_SSD) 991 i2c_pxa_slave_stop(i2c); 992 993 if (i2c_pxa_is_slavemode(i2c)) { 994 if (isr & ISR_ITE) 995 i2c_pxa_slave_txempty(i2c, isr); 996 if (isr & ISR_IRF) 997 i2c_pxa_slave_rxfull(i2c, isr); 998 } else if (i2c->msg) { 999 if (isr & ISR_ITE) 1000 i2c_pxa_irq_txempty(i2c, isr); 1001 if (isr & ISR_IRF) 1002 i2c_pxa_irq_rxfull(i2c, isr); 1003 } else { 1004 i2c_pxa_scream_blue_murder(i2c, "spurious irq"); 1005 } 1006 1007 return IRQ_HANDLED; 1008 } 1009 1010 1011 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 1012 { 1013 struct pxa_i2c *i2c = adap->algo_data; 1014 int ret, i; 1015 1016 for (i = adap->retries; i >= 0; i--) { 1017 ret = i2c_pxa_do_xfer(i2c, msgs, num); 1018 if (ret != I2C_RETRY) 1019 goto out; 1020 1021 if (i2c_debug) 1022 dev_dbg(&adap->dev, "Retrying transmission\n"); 1023 udelay(100); 1024 } 1025 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 1026 ret = -EREMOTEIO; 1027 out: 1028 i2c_pxa_set_slave(i2c, ret); 1029 return ret; 1030 } 1031 1032 static u32 i2c_pxa_functionality(struct i2c_adapter *adap) 1033 { 1034 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1035 } 1036 1037 static const struct i2c_algorithm i2c_pxa_algorithm = { 1038 .master_xfer = i2c_pxa_xfer, 1039 .functionality = i2c_pxa_functionality, 1040 }; 1041 1042 static const struct i2c_algorithm i2c_pxa_pio_algorithm = { 1043 .master_xfer = i2c_pxa_pio_xfer, 1044 .functionality = i2c_pxa_functionality, 1045 }; 1046 1047 static int i2c_pxa_probe(struct platform_device *dev) 1048 { 1049 struct pxa_i2c *i2c; 1050 struct resource *res; 1051 struct i2c_pxa_platform_data *plat = dev->dev.platform_data; 1052 const struct platform_device_id *id = platform_get_device_id(dev); 1053 enum pxa_i2c_types i2c_type = id->driver_data; 1054 int ret; 1055 int irq; 1056 1057 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1058 irq = platform_get_irq(dev, 0); 1059 if (res == NULL || irq < 0) 1060 return -ENODEV; 1061 1062 if (!request_mem_region(res->start, resource_size(res), res->name)) 1063 return -ENOMEM; 1064 1065 i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); 1066 if (!i2c) { 1067 ret = -ENOMEM; 1068 goto emalloc; 1069 } 1070 1071 i2c->adap.owner = THIS_MODULE; 1072 i2c->adap.retries = 5; 1073 1074 spin_lock_init(&i2c->lock); 1075 init_waitqueue_head(&i2c->wait); 1076 1077 /* 1078 * If "dev->id" is negative we consider it as zero. 1079 * The reason to do so is to avoid sysfs names that only make 1080 * sense when there are multiple adapters. 1081 */ 1082 i2c->adap.nr = dev->id; 1083 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u", 1084 i2c->adap.nr); 1085 1086 i2c->clk = clk_get(&dev->dev, NULL); 1087 if (IS_ERR(i2c->clk)) { 1088 ret = PTR_ERR(i2c->clk); 1089 goto eclk; 1090 } 1091 1092 i2c->reg_base = ioremap(res->start, resource_size(res)); 1093 if (!i2c->reg_base) { 1094 ret = -EIO; 1095 goto eremap; 1096 } 1097 1098 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; 1099 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; 1100 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; 1101 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; 1102 if (i2c_type != REGS_CE4100) 1103 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; 1104 1105 i2c->iobase = res->start; 1106 i2c->iosize = resource_size(res); 1107 1108 i2c->irq = irq; 1109 1110 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 1111 1112 #ifdef CONFIG_I2C_PXA_SLAVE 1113 if (plat) { 1114 i2c->slave_addr = plat->slave_addr; 1115 i2c->slave = plat->slave; 1116 } 1117 #endif 1118 1119 clk_enable(i2c->clk); 1120 1121 if (plat) { 1122 i2c->adap.class = plat->class; 1123 i2c->use_pio = plat->use_pio; 1124 i2c->fast_mode = plat->fast_mode; 1125 } 1126 1127 if (i2c->use_pio) { 1128 i2c->adap.algo = &i2c_pxa_pio_algorithm; 1129 } else { 1130 i2c->adap.algo = &i2c_pxa_algorithm; 1131 ret = request_irq(irq, i2c_pxa_handler, IRQF_SHARED, 1132 i2c->adap.name, i2c); 1133 if (ret) 1134 goto ereqirq; 1135 } 1136 1137 i2c_pxa_reset(i2c); 1138 1139 i2c->adap.algo_data = i2c; 1140 i2c->adap.dev.parent = &dev->dev; 1141 #ifdef CONFIG_OF 1142 i2c->adap.dev.of_node = dev->dev.of_node; 1143 #endif 1144 1145 ret = i2c_add_numbered_adapter(&i2c->adap); 1146 if (ret < 0) { 1147 printk(KERN_INFO "I2C: Failed to add bus\n"); 1148 goto eadapt; 1149 } 1150 of_i2c_register_devices(&i2c->adap); 1151 1152 platform_set_drvdata(dev, i2c); 1153 1154 #ifdef CONFIG_I2C_PXA_SLAVE 1155 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", 1156 dev_name(&i2c->adap.dev), i2c->slave_addr); 1157 #else 1158 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", 1159 dev_name(&i2c->adap.dev)); 1160 #endif 1161 return 0; 1162 1163 eadapt: 1164 if (!i2c->use_pio) 1165 free_irq(irq, i2c); 1166 ereqirq: 1167 clk_disable(i2c->clk); 1168 iounmap(i2c->reg_base); 1169 eremap: 1170 clk_put(i2c->clk); 1171 eclk: 1172 kfree(i2c); 1173 emalloc: 1174 release_mem_region(res->start, resource_size(res)); 1175 return ret; 1176 } 1177 1178 static int __exit i2c_pxa_remove(struct platform_device *dev) 1179 { 1180 struct pxa_i2c *i2c = platform_get_drvdata(dev); 1181 1182 platform_set_drvdata(dev, NULL); 1183 1184 i2c_del_adapter(&i2c->adap); 1185 if (!i2c->use_pio) 1186 free_irq(i2c->irq, i2c); 1187 1188 clk_disable(i2c->clk); 1189 clk_put(i2c->clk); 1190 1191 iounmap(i2c->reg_base); 1192 release_mem_region(i2c->iobase, i2c->iosize); 1193 kfree(i2c); 1194 1195 return 0; 1196 } 1197 1198 #ifdef CONFIG_PM 1199 static int i2c_pxa_suspend_noirq(struct device *dev) 1200 { 1201 struct platform_device *pdev = to_platform_device(dev); 1202 struct pxa_i2c *i2c = platform_get_drvdata(pdev); 1203 1204 clk_disable(i2c->clk); 1205 1206 return 0; 1207 } 1208 1209 static int i2c_pxa_resume_noirq(struct device *dev) 1210 { 1211 struct platform_device *pdev = to_platform_device(dev); 1212 struct pxa_i2c *i2c = platform_get_drvdata(pdev); 1213 1214 clk_enable(i2c->clk); 1215 i2c_pxa_reset(i2c); 1216 1217 return 0; 1218 } 1219 1220 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = { 1221 .suspend_noirq = i2c_pxa_suspend_noirq, 1222 .resume_noirq = i2c_pxa_resume_noirq, 1223 }; 1224 1225 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops) 1226 #else 1227 #define I2C_PXA_DEV_PM_OPS NULL 1228 #endif 1229 1230 static struct platform_driver i2c_pxa_driver = { 1231 .probe = i2c_pxa_probe, 1232 .remove = __exit_p(i2c_pxa_remove), 1233 .driver = { 1234 .name = "pxa2xx-i2c", 1235 .owner = THIS_MODULE, 1236 .pm = I2C_PXA_DEV_PM_OPS, 1237 }, 1238 .id_table = i2c_pxa_id_table, 1239 }; 1240 1241 static int __init i2c_adap_pxa_init(void) 1242 { 1243 return platform_driver_register(&i2c_pxa_driver); 1244 } 1245 1246 static void __exit i2c_adap_pxa_exit(void) 1247 { 1248 platform_driver_unregister(&i2c_pxa_driver); 1249 } 1250 1251 MODULE_LICENSE("GPL"); 1252 MODULE_ALIAS("platform:pxa2xx-i2c"); 1253 1254 subsys_initcall(i2c_adap_pxa_init); 1255 module_exit(i2c_adap_pxa_exit); 1256