1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 4 Philip Edelbrock <phil@netroedge.com> 5 6 */ 7 8 /* 9 Supports: 10 Intel PIIX4, 440MX 11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 12 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 13 AMD Hudson-2, ML, CZ 14 Hygon CZ 15 SMSC Victory66 16 17 Note: we assume there can only be one device, with one or more 18 SMBus interfaces. 19 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS). 20 For devices supporting multiple ports the i2c_adapter should provide 21 an i2c_algorithm to access them. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/pci.h> 27 #include <linux/kernel.h> 28 #include <linux/delay.h> 29 #include <linux/stddef.h> 30 #include <linux/ioport.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/dmi.h> 34 #include <linux/acpi.h> 35 #include <linux/io.h> 36 37 38 /* PIIX4 SMBus address offsets */ 39 #define SMBHSTSTS (0 + piix4_smba) 40 #define SMBHSLVSTS (1 + piix4_smba) 41 #define SMBHSTCNT (2 + piix4_smba) 42 #define SMBHSTCMD (3 + piix4_smba) 43 #define SMBHSTADD (4 + piix4_smba) 44 #define SMBHSTDAT0 (5 + piix4_smba) 45 #define SMBHSTDAT1 (6 + piix4_smba) 46 #define SMBBLKDAT (7 + piix4_smba) 47 #define SMBSLVCNT (8 + piix4_smba) 48 #define SMBSHDWCMD (9 + piix4_smba) 49 #define SMBSLVEVT (0xA + piix4_smba) 50 #define SMBSLVDAT (0xC + piix4_smba) 51 52 /* count for request_region */ 53 #define SMBIOSIZE 9 54 55 /* PCI Address Constants */ 56 #define SMBBA 0x090 57 #define SMBHSTCFG 0x0D2 58 #define SMBSLVC 0x0D3 59 #define SMBSHDW1 0x0D4 60 #define SMBSHDW2 0x0D5 61 #define SMBREV 0x0D6 62 63 /* Other settings */ 64 #define MAX_TIMEOUT 500 65 #define ENABLE_INT9 0 66 67 /* PIIX4 constants */ 68 #define PIIX4_QUICK 0x00 69 #define PIIX4_BYTE 0x04 70 #define PIIX4_BYTE_DATA 0x08 71 #define PIIX4_WORD_DATA 0x0C 72 #define PIIX4_BLOCK_DATA 0x14 73 74 /* Multi-port constants */ 75 #define PIIX4_MAX_ADAPTERS 4 76 77 /* SB800 constants */ 78 #define SB800_PIIX4_SMB_IDX 0xcd6 79 80 #define KERNCZ_IMC_IDX 0x3e 81 #define KERNCZ_IMC_DATA 0x3f 82 83 /* 84 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c) 85 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f. 86 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f. 87 */ 88 #define SB800_PIIX4_PORT_IDX 0x2c 89 #define SB800_PIIX4_PORT_IDX_ALT 0x2e 90 #define SB800_PIIX4_PORT_IDX_SEL 0x2f 91 #define SB800_PIIX4_PORT_IDX_MASK 0x06 92 #define SB800_PIIX4_PORT_IDX_SHIFT 1 93 94 /* On kerncz, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */ 95 #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02 96 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18 97 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3 98 99 /* insmod parameters */ 100 101 /* If force is set to anything different from 0, we forcibly enable the 102 PIIX4. DANGEROUS! */ 103 static int force; 104 module_param (force, int, 0); 105 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); 106 107 /* If force_addr is set to anything different from 0, we forcibly enable 108 the PIIX4 at the given address. VERY DANGEROUS! */ 109 static int force_addr; 110 module_param_hw(force_addr, int, ioport, 0); 111 MODULE_PARM_DESC(force_addr, 112 "Forcibly enable the PIIX4 at the given address. " 113 "EXTREMELY DANGEROUS!"); 114 115 static int srvrworks_csb5_delay; 116 static struct pci_driver piix4_driver; 117 118 static const struct dmi_system_id piix4_dmi_blacklist[] = { 119 { 120 .ident = "Sapphire AM2RD790", 121 .matches = { 122 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), 123 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), 124 }, 125 }, 126 { 127 .ident = "DFI Lanparty UT 790FX", 128 .matches = { 129 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), 130 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), 131 }, 132 }, 133 { } 134 }; 135 136 /* The IBM entry is in a separate table because we only check it 137 on Intel-based systems */ 138 static const struct dmi_system_id piix4_dmi_ibm[] = { 139 { 140 .ident = "IBM", 141 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, 142 }, 143 { }, 144 }; 145 146 /* 147 * SB800 globals 148 */ 149 static u8 piix4_port_sel_sb800; 150 static u8 piix4_port_mask_sb800; 151 static u8 piix4_port_shift_sb800; 152 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = { 153 " port 0", " port 2", " port 3", " port 4" 154 }; 155 static const char *piix4_aux_port_name_sb800 = " port 1"; 156 157 struct i2c_piix4_adapdata { 158 unsigned short smba; 159 160 /* SB800 */ 161 bool sb800_main; 162 bool notify_imc; 163 u8 port; /* Port number, shifted */ 164 }; 165 166 static int piix4_setup(struct pci_dev *PIIX4_dev, 167 const struct pci_device_id *id) 168 { 169 unsigned char temp; 170 unsigned short piix4_smba; 171 172 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && 173 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) 174 srvrworks_csb5_delay = 1; 175 176 /* On some motherboards, it was reported that accessing the SMBus 177 caused severe hardware problems */ 178 if (dmi_check_system(piix4_dmi_blacklist)) { 179 dev_err(&PIIX4_dev->dev, 180 "Accessing the SMBus on this system is unsafe!\n"); 181 return -EPERM; 182 } 183 184 /* Don't access SMBus on IBM systems which get corrupted eeproms */ 185 if (dmi_check_system(piix4_dmi_ibm) && 186 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { 187 dev_err(&PIIX4_dev->dev, "IBM system detected; this module " 188 "may corrupt your serial eeprom! Refusing to load " 189 "module!\n"); 190 return -EPERM; 191 } 192 193 /* Determine the address of the SMBus areas */ 194 if (force_addr) { 195 piix4_smba = force_addr & 0xfff0; 196 force = 0; 197 } else { 198 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); 199 piix4_smba &= 0xfff0; 200 if(piix4_smba == 0) { 201 dev_err(&PIIX4_dev->dev, "SMBus base address " 202 "uninitialized - upgrade BIOS or use " 203 "force_addr=0xaddr\n"); 204 return -ENODEV; 205 } 206 } 207 208 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 209 return -ENODEV; 210 211 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 212 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 213 piix4_smba); 214 return -EBUSY; 215 } 216 217 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); 218 219 /* If force_addr is set, we program the new address here. Just to make 220 sure, we disable the PIIX4 first. */ 221 if (force_addr) { 222 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); 223 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); 224 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); 225 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " 226 "new address %04x!\n", piix4_smba); 227 } else if ((temp & 1) == 0) { 228 if (force) { 229 /* This should never need to be done, but has been 230 * noted that many Dell machines have the SMBus 231 * interface on the PIIX4 disabled!? NOTE: This assumes 232 * I/O space and other allocations WERE done by the 233 * Bios! Don't complain if your hardware does weird 234 * things after enabling this. :') Check for Bios 235 * updates before resorting to this. 236 */ 237 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, 238 temp | 1); 239 dev_notice(&PIIX4_dev->dev, 240 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); 241 } else { 242 dev_err(&PIIX4_dev->dev, 243 "SMBus Host Controller not enabled!\n"); 244 release_region(piix4_smba, SMBIOSIZE); 245 return -ENODEV; 246 } 247 } 248 249 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) 250 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 251 else if ((temp & 0x0E) == 0) 252 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 253 else 254 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " 255 "(or code out of date)!\n"); 256 257 pci_read_config_byte(PIIX4_dev, SMBREV, &temp); 258 dev_info(&PIIX4_dev->dev, 259 "SMBus Host Controller at 0x%x, revision %d\n", 260 piix4_smba, temp); 261 262 return piix4_smba; 263 } 264 265 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, 266 const struct pci_device_id *id, u8 aux) 267 { 268 unsigned short piix4_smba; 269 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel; 270 u8 i2ccfg, i2ccfg_offset = 0x10; 271 272 /* SB800 and later SMBus does not support forcing address */ 273 if (force || force_addr) { 274 dev_err(&PIIX4_dev->dev, "SMBus does not support " 275 "forcing address!\n"); 276 return -EINVAL; 277 } 278 279 /* Determine the address of the SMBus areas */ 280 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 281 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 282 PIIX4_dev->revision >= 0x41) || 283 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 284 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 285 PIIX4_dev->revision >= 0x49) || 286 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON && 287 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) 288 smb_en = 0x00; 289 else 290 smb_en = (aux) ? 0x28 : 0x2c; 291 292 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) { 293 dev_err(&PIIX4_dev->dev, 294 "SMB base address index region 0x%x already in use.\n", 295 SB800_PIIX4_SMB_IDX); 296 return -EBUSY; 297 } 298 299 outb_p(smb_en, SB800_PIIX4_SMB_IDX); 300 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 301 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); 302 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); 303 304 release_region(SB800_PIIX4_SMB_IDX, 2); 305 306 if (!smb_en) { 307 smb_en_status = smba_en_lo & 0x10; 308 piix4_smba = smba_en_hi << 8; 309 if (aux) 310 piix4_smba |= 0x20; 311 } else { 312 smb_en_status = smba_en_lo & 0x01; 313 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; 314 } 315 316 if (!smb_en_status) { 317 dev_err(&PIIX4_dev->dev, 318 "SMBus Host Controller not enabled!\n"); 319 return -ENODEV; 320 } 321 322 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 323 return -ENODEV; 324 325 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 326 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 327 piix4_smba); 328 return -EBUSY; 329 } 330 331 /* Aux SMBus does not support IRQ information */ 332 if (aux) { 333 dev_info(&PIIX4_dev->dev, 334 "Auxiliary SMBus Host Controller at 0x%x\n", 335 piix4_smba); 336 return piix4_smba; 337 } 338 339 /* Request the SMBus I2C bus config region */ 340 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { 341 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " 342 "0x%x already in use!\n", piix4_smba + i2ccfg_offset); 343 release_region(piix4_smba, SMBIOSIZE); 344 return -EBUSY; 345 } 346 i2ccfg = inb_p(piix4_smba + i2ccfg_offset); 347 release_region(piix4_smba + i2ccfg_offset, 1); 348 349 if (i2ccfg & 1) 350 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 351 else 352 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 353 354 dev_info(&PIIX4_dev->dev, 355 "SMBus Host Controller at 0x%x, revision %d\n", 356 piix4_smba, i2ccfg >> 4); 357 358 /* Find which register is used for port selection */ 359 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD || 360 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) { 361 switch (PIIX4_dev->device) { 362 case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS: 363 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ; 364 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ; 365 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ; 366 break; 367 case PCI_DEVICE_ID_AMD_HUDSON2_SMBUS: 368 default: 369 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT; 370 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; 371 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; 372 break; 373 } 374 } else { 375 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, 376 "sb800_piix4_smb")) { 377 release_region(piix4_smba, SMBIOSIZE); 378 return -EBUSY; 379 } 380 381 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX); 382 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); 383 piix4_port_sel_sb800 = (port_sel & 0x01) ? 384 SB800_PIIX4_PORT_IDX_ALT : 385 SB800_PIIX4_PORT_IDX; 386 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; 387 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; 388 release_region(SB800_PIIX4_SMB_IDX, 2); 389 } 390 391 dev_info(&PIIX4_dev->dev, 392 "Using register 0x%02x for SMBus port selection\n", 393 (unsigned int)piix4_port_sel_sb800); 394 395 return piix4_smba; 396 } 397 398 static int piix4_setup_aux(struct pci_dev *PIIX4_dev, 399 const struct pci_device_id *id, 400 unsigned short base_reg_addr) 401 { 402 /* Set up auxiliary SMBus controllers found on some 403 * AMD chipsets e.g. SP5100 (SB700 derivative) */ 404 405 unsigned short piix4_smba; 406 407 /* Read address of auxiliary SMBus controller */ 408 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); 409 if ((piix4_smba & 1) == 0) { 410 dev_dbg(&PIIX4_dev->dev, 411 "Auxiliary SMBus controller not enabled\n"); 412 return -ENODEV; 413 } 414 415 piix4_smba &= 0xfff0; 416 if (piix4_smba == 0) { 417 dev_dbg(&PIIX4_dev->dev, 418 "Auxiliary SMBus base address uninitialized\n"); 419 return -ENODEV; 420 } 421 422 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 423 return -ENODEV; 424 425 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 426 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " 427 "already in use!\n", piix4_smba); 428 return -EBUSY; 429 } 430 431 dev_info(&PIIX4_dev->dev, 432 "Auxiliary SMBus Host Controller at 0x%x\n", 433 piix4_smba); 434 435 return piix4_smba; 436 } 437 438 static int piix4_transaction(struct i2c_adapter *piix4_adapter) 439 { 440 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter); 441 unsigned short piix4_smba = adapdata->smba; 442 int temp; 443 int result = 0; 444 int timeout = 0; 445 446 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 447 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 448 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 449 inb_p(SMBHSTDAT1)); 450 451 /* Make sure the SMBus host is ready to start transmitting */ 452 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 453 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " 454 "Resetting...\n", temp); 455 outb_p(temp, SMBHSTSTS); 456 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 457 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); 458 return -EBUSY; 459 } else { 460 dev_dbg(&piix4_adapter->dev, "Successful!\n"); 461 } 462 } 463 464 /* start the transaction by setting bit 6 */ 465 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); 466 467 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ 468 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ 469 usleep_range(2000, 2100); 470 else 471 usleep_range(250, 500); 472 473 while ((++timeout < MAX_TIMEOUT) && 474 ((temp = inb_p(SMBHSTSTS)) & 0x01)) 475 usleep_range(250, 500); 476 477 /* If the SMBus is still busy, we give up */ 478 if (timeout == MAX_TIMEOUT) { 479 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); 480 result = -ETIMEDOUT; 481 } 482 483 if (temp & 0x10) { 484 result = -EIO; 485 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); 486 } 487 488 if (temp & 0x08) { 489 result = -EIO; 490 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " 491 "locked until next hard reset. (sorry!)\n"); 492 /* Clock stops and slave is stuck in mid-transmission */ 493 } 494 495 if (temp & 0x04) { 496 result = -ENXIO; 497 dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); 498 } 499 500 if (inb_p(SMBHSTSTS) != 0x00) 501 outb_p(inb(SMBHSTSTS), SMBHSTSTS); 502 503 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 504 dev_err(&piix4_adapter->dev, "Failed reset at end of " 505 "transaction (%02x)\n", temp); 506 } 507 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " 508 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 509 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 510 inb_p(SMBHSTDAT1)); 511 return result; 512 } 513 514 /* Return negative errno on error. */ 515 static s32 piix4_access(struct i2c_adapter * adap, u16 addr, 516 unsigned short flags, char read_write, 517 u8 command, int size, union i2c_smbus_data * data) 518 { 519 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 520 unsigned short piix4_smba = adapdata->smba; 521 int i, len; 522 int status; 523 524 switch (size) { 525 case I2C_SMBUS_QUICK: 526 outb_p((addr << 1) | read_write, 527 SMBHSTADD); 528 size = PIIX4_QUICK; 529 break; 530 case I2C_SMBUS_BYTE: 531 outb_p((addr << 1) | read_write, 532 SMBHSTADD); 533 if (read_write == I2C_SMBUS_WRITE) 534 outb_p(command, SMBHSTCMD); 535 size = PIIX4_BYTE; 536 break; 537 case I2C_SMBUS_BYTE_DATA: 538 outb_p((addr << 1) | read_write, 539 SMBHSTADD); 540 outb_p(command, SMBHSTCMD); 541 if (read_write == I2C_SMBUS_WRITE) 542 outb_p(data->byte, SMBHSTDAT0); 543 size = PIIX4_BYTE_DATA; 544 break; 545 case I2C_SMBUS_WORD_DATA: 546 outb_p((addr << 1) | read_write, 547 SMBHSTADD); 548 outb_p(command, SMBHSTCMD); 549 if (read_write == I2C_SMBUS_WRITE) { 550 outb_p(data->word & 0xff, SMBHSTDAT0); 551 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); 552 } 553 size = PIIX4_WORD_DATA; 554 break; 555 case I2C_SMBUS_BLOCK_DATA: 556 outb_p((addr << 1) | read_write, 557 SMBHSTADD); 558 outb_p(command, SMBHSTCMD); 559 if (read_write == I2C_SMBUS_WRITE) { 560 len = data->block[0]; 561 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 562 return -EINVAL; 563 outb_p(len, SMBHSTDAT0); 564 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 565 for (i = 1; i <= len; i++) 566 outb_p(data->block[i], SMBBLKDAT); 567 } 568 size = PIIX4_BLOCK_DATA; 569 break; 570 default: 571 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 572 return -EOPNOTSUPP; 573 } 574 575 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); 576 577 status = piix4_transaction(adap); 578 if (status) 579 return status; 580 581 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) 582 return 0; 583 584 585 switch (size) { 586 case PIIX4_BYTE: 587 case PIIX4_BYTE_DATA: 588 data->byte = inb_p(SMBHSTDAT0); 589 break; 590 case PIIX4_WORD_DATA: 591 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); 592 break; 593 case PIIX4_BLOCK_DATA: 594 data->block[0] = inb_p(SMBHSTDAT0); 595 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 596 return -EPROTO; 597 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 598 for (i = 1; i <= data->block[0]; i++) 599 data->block[i] = inb_p(SMBBLKDAT); 600 break; 601 } 602 return 0; 603 } 604 605 static uint8_t piix4_imc_read(uint8_t idx) 606 { 607 outb_p(idx, KERNCZ_IMC_IDX); 608 return inb_p(KERNCZ_IMC_DATA); 609 } 610 611 static void piix4_imc_write(uint8_t idx, uint8_t value) 612 { 613 outb_p(idx, KERNCZ_IMC_IDX); 614 outb_p(value, KERNCZ_IMC_DATA); 615 } 616 617 static int piix4_imc_sleep(void) 618 { 619 int timeout = MAX_TIMEOUT; 620 621 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) 622 return -EBUSY; 623 624 /* clear response register */ 625 piix4_imc_write(0x82, 0x00); 626 /* request ownership flag */ 627 piix4_imc_write(0x83, 0xB4); 628 /* kick off IMC Mailbox command 96 */ 629 piix4_imc_write(0x80, 0x96); 630 631 while (timeout--) { 632 if (piix4_imc_read(0x82) == 0xfa) { 633 release_region(KERNCZ_IMC_IDX, 2); 634 return 0; 635 } 636 usleep_range(1000, 2000); 637 } 638 639 release_region(KERNCZ_IMC_IDX, 2); 640 return -ETIMEDOUT; 641 } 642 643 static void piix4_imc_wakeup(void) 644 { 645 int timeout = MAX_TIMEOUT; 646 647 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) 648 return; 649 650 /* clear response register */ 651 piix4_imc_write(0x82, 0x00); 652 /* release ownership flag */ 653 piix4_imc_write(0x83, 0xB5); 654 /* kick off IMC Mailbox command 96 */ 655 piix4_imc_write(0x80, 0x96); 656 657 while (timeout--) { 658 if (piix4_imc_read(0x82) == 0xfa) 659 break; 660 usleep_range(1000, 2000); 661 } 662 663 release_region(KERNCZ_IMC_IDX, 2); 664 } 665 666 /* 667 * Handles access to multiple SMBus ports on the SB800. 668 * The port is selected by bits 2:1 of the smb_en register (0x2c). 669 * Returns negative errno on error. 670 * 671 * Note: The selected port must be returned to the initial selection to avoid 672 * problems on certain systems. 673 */ 674 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, 675 unsigned short flags, char read_write, 676 u8 command, int size, union i2c_smbus_data *data) 677 { 678 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 679 unsigned short piix4_smba = adapdata->smba; 680 int retries = MAX_TIMEOUT; 681 int smbslvcnt; 682 u8 smba_en_lo; 683 u8 port; 684 int retval; 685 686 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) 687 return -EBUSY; 688 689 /* Request the SMBUS semaphore, avoid conflicts with the IMC */ 690 smbslvcnt = inb_p(SMBSLVCNT); 691 do { 692 outb_p(smbslvcnt | 0x10, SMBSLVCNT); 693 694 /* Check the semaphore status */ 695 smbslvcnt = inb_p(SMBSLVCNT); 696 if (smbslvcnt & 0x10) 697 break; 698 699 usleep_range(1000, 2000); 700 } while (--retries); 701 /* SMBus is still owned by the IMC, we give up */ 702 if (!retries) { 703 retval = -EBUSY; 704 goto release; 705 } 706 707 /* 708 * Notify the IMC (Integrated Micro Controller) if required. 709 * Among other responsibilities, the IMC is in charge of monitoring 710 * the System fans and temperature sensors, and act accordingly. 711 * All this is done through SMBus and can/will collide 712 * with our transactions if they are long (BLOCK_DATA). 713 * Therefore we need to request the ownership flag during those 714 * transactions. 715 */ 716 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) { 717 int ret; 718 719 ret = piix4_imc_sleep(); 720 switch (ret) { 721 case -EBUSY: 722 dev_warn(&adap->dev, 723 "IMC base address index region 0x%x already in use.\n", 724 KERNCZ_IMC_IDX); 725 break; 726 case -ETIMEDOUT: 727 dev_warn(&adap->dev, 728 "Failed to communicate with the IMC.\n"); 729 break; 730 default: 731 break; 732 } 733 734 /* If IMC communication fails do not retry */ 735 if (ret) { 736 dev_warn(&adap->dev, 737 "Continuing without IMC notification.\n"); 738 adapdata->notify_imc = false; 739 } 740 } 741 742 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); 743 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 744 745 port = adapdata->port; 746 if ((smba_en_lo & piix4_port_mask_sb800) != port) 747 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port, 748 SB800_PIIX4_SMB_IDX + 1); 749 750 retval = piix4_access(adap, addr, flags, read_write, 751 command, size, data); 752 753 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1); 754 755 /* Release the semaphore */ 756 outb_p(smbslvcnt | 0x20, SMBSLVCNT); 757 758 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) 759 piix4_imc_wakeup(); 760 761 release: 762 release_region(SB800_PIIX4_SMB_IDX, 2); 763 return retval; 764 } 765 766 static u32 piix4_func(struct i2c_adapter *adapter) 767 { 768 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 769 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 770 I2C_FUNC_SMBUS_BLOCK_DATA; 771 } 772 773 static const struct i2c_algorithm smbus_algorithm = { 774 .smbus_xfer = piix4_access, 775 .functionality = piix4_func, 776 }; 777 778 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = { 779 .smbus_xfer = piix4_access_sb800, 780 .functionality = piix4_func, 781 }; 782 783 static const struct pci_device_id piix4_ids[] = { 784 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, 785 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, 786 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, 787 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, 788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, 789 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, 790 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, 791 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, 792 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 793 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 794 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 795 PCI_DEVICE_ID_SERVERWORKS_OSB4) }, 796 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 797 PCI_DEVICE_ID_SERVERWORKS_CSB5) }, 798 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 799 PCI_DEVICE_ID_SERVERWORKS_CSB6) }, 800 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 801 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, 802 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 803 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, 804 { 0, } 805 }; 806 807 MODULE_DEVICE_TABLE (pci, piix4_ids); 808 809 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS]; 810 static struct i2c_adapter *piix4_aux_adapter; 811 812 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, 813 bool sb800_main, u8 port, bool notify_imc, 814 const char *name, struct i2c_adapter **padap) 815 { 816 struct i2c_adapter *adap; 817 struct i2c_piix4_adapdata *adapdata; 818 int retval; 819 820 adap = kzalloc(sizeof(*adap), GFP_KERNEL); 821 if (adap == NULL) { 822 release_region(smba, SMBIOSIZE); 823 return -ENOMEM; 824 } 825 826 adap->owner = THIS_MODULE; 827 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 828 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800 829 : &smbus_algorithm; 830 831 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); 832 if (adapdata == NULL) { 833 kfree(adap); 834 release_region(smba, SMBIOSIZE); 835 return -ENOMEM; 836 } 837 838 adapdata->smba = smba; 839 adapdata->sb800_main = sb800_main; 840 adapdata->port = port << piix4_port_shift_sb800; 841 adapdata->notify_imc = notify_imc; 842 843 /* set up the sysfs linkage to our parent device */ 844 adap->dev.parent = &dev->dev; 845 846 snprintf(adap->name, sizeof(adap->name), 847 "SMBus PIIX4 adapter%s at %04x", name, smba); 848 849 i2c_set_adapdata(adap, adapdata); 850 851 retval = i2c_add_adapter(adap); 852 if (retval) { 853 kfree(adapdata); 854 kfree(adap); 855 release_region(smba, SMBIOSIZE); 856 return retval; 857 } 858 859 *padap = adap; 860 return 0; 861 } 862 863 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba, 864 bool notify_imc) 865 { 866 struct i2c_piix4_adapdata *adapdata; 867 int port; 868 int retval; 869 870 for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) { 871 retval = piix4_add_adapter(dev, smba, true, port, notify_imc, 872 piix4_main_port_names_sb800[port], 873 &piix4_main_adapters[port]); 874 if (retval < 0) 875 goto error; 876 } 877 878 return retval; 879 880 error: 881 dev_err(&dev->dev, 882 "Error setting up SB800 adapters. Unregistering!\n"); 883 while (--port >= 0) { 884 adapdata = i2c_get_adapdata(piix4_main_adapters[port]); 885 if (adapdata->smba) { 886 i2c_del_adapter(piix4_main_adapters[port]); 887 kfree(adapdata); 888 kfree(piix4_main_adapters[port]); 889 piix4_main_adapters[port] = NULL; 890 } 891 } 892 893 return retval; 894 } 895 896 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) 897 { 898 int retval; 899 bool is_sb800 = false; 900 901 if ((dev->vendor == PCI_VENDOR_ID_ATI && 902 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && 903 dev->revision >= 0x40) || 904 dev->vendor == PCI_VENDOR_ID_AMD || 905 dev->vendor == PCI_VENDOR_ID_HYGON) { 906 bool notify_imc = false; 907 is_sb800 = true; 908 909 if ((dev->vendor == PCI_VENDOR_ID_AMD || 910 dev->vendor == PCI_VENDOR_ID_HYGON) && 911 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) { 912 u8 imc; 913 914 /* 915 * Detect if IMC is active or not, this method is 916 * described on coreboot's AMD IMC notes 917 */ 918 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3), 919 0x40, &imc); 920 if (imc & 0x80) 921 notify_imc = true; 922 } 923 924 /* base address location etc changed in SB800 */ 925 retval = piix4_setup_sb800(dev, id, 0); 926 if (retval < 0) 927 return retval; 928 929 /* 930 * Try to register multiplexed main SMBus adapter, 931 * give up if we can't 932 */ 933 retval = piix4_add_adapters_sb800(dev, retval, notify_imc); 934 if (retval < 0) 935 return retval; 936 } else { 937 retval = piix4_setup(dev, id); 938 if (retval < 0) 939 return retval; 940 941 /* Try to register main SMBus adapter, give up if we can't */ 942 retval = piix4_add_adapter(dev, retval, false, 0, false, "", 943 &piix4_main_adapters[0]); 944 if (retval < 0) 945 return retval; 946 } 947 948 /* Check for auxiliary SMBus on some AMD chipsets */ 949 retval = -ENODEV; 950 951 if (dev->vendor == PCI_VENDOR_ID_ATI && 952 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { 953 if (dev->revision < 0x40) { 954 retval = piix4_setup_aux(dev, id, 0x58); 955 } else { 956 /* SB800 added aux bus too */ 957 retval = piix4_setup_sb800(dev, id, 1); 958 } 959 } 960 961 if (dev->vendor == PCI_VENDOR_ID_AMD && 962 dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { 963 retval = piix4_setup_sb800(dev, id, 1); 964 } 965 966 if (retval > 0) { 967 /* Try to add the aux adapter if it exists, 968 * piix4_add_adapter will clean up if this fails */ 969 piix4_add_adapter(dev, retval, false, 0, false, 970 is_sb800 ? piix4_aux_port_name_sb800 : "", 971 &piix4_aux_adapter); 972 } 973 974 return 0; 975 } 976 977 static void piix4_adap_remove(struct i2c_adapter *adap) 978 { 979 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 980 981 if (adapdata->smba) { 982 i2c_del_adapter(adap); 983 if (adapdata->port == (0 << piix4_port_shift_sb800)) 984 release_region(adapdata->smba, SMBIOSIZE); 985 kfree(adapdata); 986 kfree(adap); 987 } 988 } 989 990 static void piix4_remove(struct pci_dev *dev) 991 { 992 int port = PIIX4_MAX_ADAPTERS; 993 994 while (--port >= 0) { 995 if (piix4_main_adapters[port]) { 996 piix4_adap_remove(piix4_main_adapters[port]); 997 piix4_main_adapters[port] = NULL; 998 } 999 } 1000 1001 if (piix4_aux_adapter) { 1002 piix4_adap_remove(piix4_aux_adapter); 1003 piix4_aux_adapter = NULL; 1004 } 1005 } 1006 1007 static struct pci_driver piix4_driver = { 1008 .name = "piix4_smbus", 1009 .id_table = piix4_ids, 1010 .probe = piix4_probe, 1011 .remove = piix4_remove, 1012 }; 1013 1014 module_pci_driver(piix4_driver); 1015 1016 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " 1017 "Philip Edelbrock <phil@netroedge.com>"); 1018 MODULE_DESCRIPTION("PIIX4 SMBus driver"); 1019 MODULE_LICENSE("GPL"); 1020