1 /* 2 piix4.c - Part of lm_sensors, Linux kernel modules for hardware 3 monitoring 4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 5 Philip Edelbrock <phil@netroedge.com> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 /* 23 Supports: 24 Intel PIIX4, 440MX 25 Serverworks OSB4, CSB5, CSB6 26 SMSC Victory66 27 28 Note: we assume there can only be one device, with one SMBus interface. 29 */ 30 31 #include <linux/module.h> 32 #include <linux/moduleparam.h> 33 #include <linux/pci.h> 34 #include <linux/kernel.h> 35 #include <linux/delay.h> 36 #include <linux/stddef.h> 37 #include <linux/sched.h> 38 #include <linux/ioport.h> 39 #include <linux/i2c.h> 40 #include <linux/init.h> 41 #include <linux/apm_bios.h> 42 #include <linux/dmi.h> 43 #include <asm/io.h> 44 45 46 struct sd { 47 const unsigned short mfr; 48 const unsigned short dev; 49 const unsigned char fn; 50 const char *name; 51 }; 52 53 /* PIIX4 SMBus address offsets */ 54 #define SMBHSTSTS (0 + piix4_smba) 55 #define SMBHSLVSTS (1 + piix4_smba) 56 #define SMBHSTCNT (2 + piix4_smba) 57 #define SMBHSTCMD (3 + piix4_smba) 58 #define SMBHSTADD (4 + piix4_smba) 59 #define SMBHSTDAT0 (5 + piix4_smba) 60 #define SMBHSTDAT1 (6 + piix4_smba) 61 #define SMBBLKDAT (7 + piix4_smba) 62 #define SMBSLVCNT (8 + piix4_smba) 63 #define SMBSHDWCMD (9 + piix4_smba) 64 #define SMBSLVEVT (0xA + piix4_smba) 65 #define SMBSLVDAT (0xC + piix4_smba) 66 67 /* count for request_region */ 68 #define SMBIOSIZE 8 69 70 /* PCI Address Constants */ 71 #define SMBBA 0x090 72 #define SMBHSTCFG 0x0D2 73 #define SMBSLVC 0x0D3 74 #define SMBSHDW1 0x0D4 75 #define SMBSHDW2 0x0D5 76 #define SMBREV 0x0D6 77 78 /* Other settings */ 79 #define MAX_TIMEOUT 500 80 #define ENABLE_INT9 0 81 82 /* PIIX4 constants */ 83 #define PIIX4_QUICK 0x00 84 #define PIIX4_BYTE 0x04 85 #define PIIX4_BYTE_DATA 0x08 86 #define PIIX4_WORD_DATA 0x0C 87 #define PIIX4_BLOCK_DATA 0x14 88 89 /* insmod parameters */ 90 91 /* If force is set to anything different from 0, we forcibly enable the 92 PIIX4. DANGEROUS! */ 93 static int force; 94 module_param (force, int, 0); 95 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); 96 97 /* If force_addr is set to anything different from 0, we forcibly enable 98 the PIIX4 at the given address. VERY DANGEROUS! */ 99 static int force_addr; 100 module_param (force_addr, int, 0); 101 MODULE_PARM_DESC(force_addr, 102 "Forcibly enable the PIIX4 at the given address. " 103 "EXTREMELY DANGEROUS!"); 104 105 /* If fix_hstcfg is set to anything different from 0, we reset one of the 106 registers to be a valid value. */ 107 static int fix_hstcfg; 108 module_param (fix_hstcfg, int, 0); 109 MODULE_PARM_DESC(fix_hstcfg, 110 "Fix config register. Needed on some boards (Force CPCI735)."); 111 112 static int piix4_transaction(void); 113 114 static unsigned short piix4_smba; 115 static struct pci_driver piix4_driver; 116 static struct i2c_adapter piix4_adapter; 117 118 static struct dmi_system_id __devinitdata piix4_dmi_table[] = { 119 { 120 .ident = "IBM", 121 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, 122 }, 123 { }, 124 }; 125 126 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev, 127 const struct pci_device_id *id) 128 { 129 unsigned char temp; 130 131 /* match up the function */ 132 if (PCI_FUNC(PIIX4_dev->devfn) != id->driver_data) 133 return -ENODEV; 134 135 dev_info(&PIIX4_dev->dev, "Found %s device\n", pci_name(PIIX4_dev)); 136 137 /* Don't access SMBus on IBM systems which get corrupted eeproms */ 138 if (dmi_check_system(piix4_dmi_table) && 139 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { 140 dev_err(&PIIX4_dev->dev, "IBM Laptop detected; this module " 141 "may corrupt your serial eeprom! Refusing to load " 142 "module!\n"); 143 return -EPERM; 144 } 145 146 /* Determine the address of the SMBus areas */ 147 if (force_addr) { 148 piix4_smba = force_addr & 0xfff0; 149 force = 0; 150 } else { 151 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); 152 piix4_smba &= 0xfff0; 153 if(piix4_smba == 0) { 154 dev_err(&PIIX4_dev->dev, "SMB base address " 155 "uninitialized - upgrade BIOS or use " 156 "force_addr=0xaddr\n"); 157 return -ENODEV; 158 } 159 } 160 161 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 162 dev_err(&PIIX4_dev->dev, "SMB region 0x%x already in use!\n", 163 piix4_smba); 164 return -ENODEV; 165 } 166 167 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); 168 169 /* Some BIOS will set up the chipset incorrectly and leave a register 170 in an undefined state (causing I2C to act very strangely). */ 171 if (temp & 0x02) { 172 if (fix_hstcfg) { 173 dev_info(&PIIX4_dev->dev, "Working around buggy BIOS " 174 "(I2C)\n"); 175 temp &= 0xfd; 176 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp); 177 } else { 178 dev_info(&PIIX4_dev->dev, "Unusual config register " 179 "value\n"); 180 dev_info(&PIIX4_dev->dev, "Try using fix_hstcfg=1 if " 181 "you experience problems\n"); 182 } 183 } 184 185 /* If force_addr is set, we program the new address here. Just to make 186 sure, we disable the PIIX4 first. */ 187 if (force_addr) { 188 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); 189 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); 190 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); 191 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " 192 "new address %04x!\n", piix4_smba); 193 } else if ((temp & 1) == 0) { 194 if (force) { 195 /* This should never need to be done, but has been 196 * noted that many Dell machines have the SMBus 197 * interface on the PIIX4 disabled!? NOTE: This assumes 198 * I/O space and other allocations WERE done by the 199 * Bios! Don't complain if your hardware does weird 200 * things after enabling this. :') Check for Bios 201 * updates before resorting to this. 202 */ 203 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, 204 temp | 1); 205 dev_printk(KERN_NOTICE, &PIIX4_dev->dev, 206 "WARNING: SMBus interface has been " 207 "FORCEFULLY ENABLED!\n"); 208 } else { 209 dev_err(&PIIX4_dev->dev, 210 "Host SMBus controller not enabled!\n"); 211 release_region(piix4_smba, SMBIOSIZE); 212 piix4_smba = 0; 213 return -ENODEV; 214 } 215 } 216 217 if ((temp & 0x0E) == 8) 218 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n"); 219 else if ((temp & 0x0E) == 0) 220 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n"); 221 else 222 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " 223 "(or code out of date)!\n"); 224 225 pci_read_config_byte(PIIX4_dev, SMBREV, &temp); 226 dev_dbg(&PIIX4_dev->dev, "SMBREV = 0x%X\n", temp); 227 dev_dbg(&PIIX4_dev->dev, "SMBA = 0x%X\n", piix4_smba); 228 229 return 0; 230 } 231 232 /* Another internally used function */ 233 static int piix4_transaction(void) 234 { 235 int temp; 236 int result = 0; 237 int timeout = 0; 238 239 dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 240 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 241 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 242 inb_p(SMBHSTDAT1)); 243 244 /* Make sure the SMBus host is ready to start transmitting */ 245 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 246 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). " 247 "Resetting...\n", temp); 248 outb_p(temp, SMBHSTSTS); 249 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 250 dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp); 251 return -1; 252 } else { 253 dev_dbg(&piix4_adapter.dev, "Successfull!\n"); 254 } 255 } 256 257 /* start the transaction by setting bit 6 */ 258 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); 259 260 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ 261 do { 262 msleep(1); 263 temp = inb_p(SMBHSTSTS); 264 } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT)); 265 266 /* If the SMBus is still busy, we give up */ 267 if (timeout >= MAX_TIMEOUT) { 268 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n"); 269 result = -1; 270 } 271 272 if (temp & 0x10) { 273 result = -1; 274 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n"); 275 } 276 277 if (temp & 0x08) { 278 result = -1; 279 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be " 280 "locked until next hard reset. (sorry!)\n"); 281 /* Clock stops and slave is stuck in mid-transmission */ 282 } 283 284 if (temp & 0x04) { 285 result = -1; 286 dev_dbg(&piix4_adapter.dev, "Error: no response!\n"); 287 } 288 289 if (inb_p(SMBHSTSTS) != 0x00) 290 outb_p(inb(SMBHSTSTS), SMBHSTSTS); 291 292 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 293 dev_err(&piix4_adapter.dev, "Failed reset at end of " 294 "transaction (%02x)\n", temp); 295 } 296 dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, " 297 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 298 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 299 inb_p(SMBHSTDAT1)); 300 return result; 301 } 302 303 /* Return -1 on error. */ 304 static s32 piix4_access(struct i2c_adapter * adap, u16 addr, 305 unsigned short flags, char read_write, 306 u8 command, int size, union i2c_smbus_data * data) 307 { 308 int i, len; 309 310 switch (size) { 311 case I2C_SMBUS_PROC_CALL: 312 dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n"); 313 return -1; 314 case I2C_SMBUS_QUICK: 315 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 316 SMBHSTADD); 317 size = PIIX4_QUICK; 318 break; 319 case I2C_SMBUS_BYTE: 320 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 321 SMBHSTADD); 322 if (read_write == I2C_SMBUS_WRITE) 323 outb_p(command, SMBHSTCMD); 324 size = PIIX4_BYTE; 325 break; 326 case I2C_SMBUS_BYTE_DATA: 327 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 328 SMBHSTADD); 329 outb_p(command, SMBHSTCMD); 330 if (read_write == I2C_SMBUS_WRITE) 331 outb_p(data->byte, SMBHSTDAT0); 332 size = PIIX4_BYTE_DATA; 333 break; 334 case I2C_SMBUS_WORD_DATA: 335 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 336 SMBHSTADD); 337 outb_p(command, SMBHSTCMD); 338 if (read_write == I2C_SMBUS_WRITE) { 339 outb_p(data->word & 0xff, SMBHSTDAT0); 340 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); 341 } 342 size = PIIX4_WORD_DATA; 343 break; 344 case I2C_SMBUS_BLOCK_DATA: 345 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 346 SMBHSTADD); 347 outb_p(command, SMBHSTCMD); 348 if (read_write == I2C_SMBUS_WRITE) { 349 len = data->block[0]; 350 if (len < 0) 351 len = 0; 352 if (len > 32) 353 len = 32; 354 outb_p(len, SMBHSTDAT0); 355 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 356 for (i = 1; i <= len; i++) 357 outb_p(data->block[i], SMBBLKDAT); 358 } 359 size = PIIX4_BLOCK_DATA; 360 break; 361 } 362 363 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); 364 365 if (piix4_transaction()) /* Error in transaction */ 366 return -1; 367 368 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) 369 return 0; 370 371 372 switch (size) { 373 case PIIX4_BYTE: /* Where is the result put? I assume here it is in 374 SMBHSTDAT0 but it might just as well be in the 375 SMBHSTCMD. No clue in the docs */ 376 377 data->byte = inb_p(SMBHSTDAT0); 378 break; 379 case PIIX4_BYTE_DATA: 380 data->byte = inb_p(SMBHSTDAT0); 381 break; 382 case PIIX4_WORD_DATA: 383 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); 384 break; 385 case PIIX4_BLOCK_DATA: 386 data->block[0] = inb_p(SMBHSTDAT0); 387 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 388 for (i = 1; i <= data->block[0]; i++) 389 data->block[i] = inb_p(SMBBLKDAT); 390 break; 391 } 392 return 0; 393 } 394 395 static u32 piix4_func(struct i2c_adapter *adapter) 396 { 397 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 398 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 399 I2C_FUNC_SMBUS_BLOCK_DATA; 400 } 401 402 static struct i2c_algorithm smbus_algorithm = { 403 .smbus_xfer = piix4_access, 404 .functionality = piix4_func, 405 }; 406 407 static struct i2c_adapter piix4_adapter = { 408 .owner = THIS_MODULE, 409 .class = I2C_CLASS_HWMON, 410 .algo = &smbus_algorithm, 411 }; 412 413 static struct pci_device_id piix4_ids[] = { 414 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3), 415 .driver_data = 3 }, 416 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4), 417 .driver_data = 0 }, 418 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5), 419 .driver_data = 0 }, 420 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6), 421 .driver_data = 0 }, 422 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3), 423 .driver_data = 3 }, 424 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3), 425 .driver_data = 0 }, 426 { 0, } 427 }; 428 429 MODULE_DEVICE_TABLE (pci, piix4_ids); 430 431 static int __devinit piix4_probe(struct pci_dev *dev, 432 const struct pci_device_id *id) 433 { 434 int retval; 435 436 retval = piix4_setup(dev, id); 437 if (retval) 438 return retval; 439 440 /* set up the driverfs linkage to our parent device */ 441 piix4_adapter.dev.parent = &dev->dev; 442 443 snprintf(piix4_adapter.name, I2C_NAME_SIZE, 444 "SMBus PIIX4 adapter at %04x", piix4_smba); 445 446 if ((retval = i2c_add_adapter(&piix4_adapter))) { 447 dev_err(&dev->dev, "Couldn't register adapter!\n"); 448 release_region(piix4_smba, SMBIOSIZE); 449 piix4_smba = 0; 450 } 451 452 return retval; 453 } 454 455 static void __devexit piix4_remove(struct pci_dev *dev) 456 { 457 if (piix4_smba) { 458 i2c_del_adapter(&piix4_adapter); 459 release_region(piix4_smba, SMBIOSIZE); 460 piix4_smba = 0; 461 } 462 } 463 464 static struct pci_driver piix4_driver = { 465 .name = "piix4_smbus", 466 .id_table = piix4_ids, 467 .probe = piix4_probe, 468 .remove = __devexit_p(piix4_remove), 469 }; 470 471 static int __init i2c_piix4_init(void) 472 { 473 return pci_register_driver(&piix4_driver); 474 } 475 476 static void __exit i2c_piix4_exit(void) 477 { 478 pci_unregister_driver(&piix4_driver); 479 } 480 481 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " 482 "Philip Edelbrock <phil@netroedge.com>"); 483 MODULE_DESCRIPTION("PIIX4 SMBus driver"); 484 MODULE_LICENSE("GPL"); 485 486 module_init(i2c_piix4_init); 487 module_exit(i2c_piix4_exit); 488