1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 3 Philip Edelbrock <phil@netroedge.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 /* 21 Supports: 22 Intel PIIX4, 440MX 23 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 24 ATI IXP200, IXP300, IXP400, SB600, SB700, SB800 25 SMSC Victory66 26 27 Note: we assume there can only be one device, with one SMBus interface. 28 */ 29 30 #include <linux/module.h> 31 #include <linux/moduleparam.h> 32 #include <linux/pci.h> 33 #include <linux/kernel.h> 34 #include <linux/delay.h> 35 #include <linux/stddef.h> 36 #include <linux/ioport.h> 37 #include <linux/i2c.h> 38 #include <linux/init.h> 39 #include <linux/dmi.h> 40 #include <linux/acpi.h> 41 #include <asm/io.h> 42 43 44 /* PIIX4 SMBus address offsets */ 45 #define SMBHSTSTS (0 + piix4_smba) 46 #define SMBHSLVSTS (1 + piix4_smba) 47 #define SMBHSTCNT (2 + piix4_smba) 48 #define SMBHSTCMD (3 + piix4_smba) 49 #define SMBHSTADD (4 + piix4_smba) 50 #define SMBHSTDAT0 (5 + piix4_smba) 51 #define SMBHSTDAT1 (6 + piix4_smba) 52 #define SMBBLKDAT (7 + piix4_smba) 53 #define SMBSLVCNT (8 + piix4_smba) 54 #define SMBSHDWCMD (9 + piix4_smba) 55 #define SMBSLVEVT (0xA + piix4_smba) 56 #define SMBSLVDAT (0xC + piix4_smba) 57 58 /* count for request_region */ 59 #define SMBIOSIZE 8 60 61 /* PCI Address Constants */ 62 #define SMBBA 0x090 63 #define SMBHSTCFG 0x0D2 64 #define SMBSLVC 0x0D3 65 #define SMBSHDW1 0x0D4 66 #define SMBSHDW2 0x0D5 67 #define SMBREV 0x0D6 68 69 /* Other settings */ 70 #define MAX_TIMEOUT 500 71 #define ENABLE_INT9 0 72 73 /* PIIX4 constants */ 74 #define PIIX4_QUICK 0x00 75 #define PIIX4_BYTE 0x04 76 #define PIIX4_BYTE_DATA 0x08 77 #define PIIX4_WORD_DATA 0x0C 78 #define PIIX4_BLOCK_DATA 0x14 79 80 /* insmod parameters */ 81 82 /* If force is set to anything different from 0, we forcibly enable the 83 PIIX4. DANGEROUS! */ 84 static int force; 85 module_param (force, int, 0); 86 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); 87 88 /* If force_addr is set to anything different from 0, we forcibly enable 89 the PIIX4 at the given address. VERY DANGEROUS! */ 90 static int force_addr; 91 module_param (force_addr, int, 0); 92 MODULE_PARM_DESC(force_addr, 93 "Forcibly enable the PIIX4 at the given address. " 94 "EXTREMELY DANGEROUS!"); 95 96 static unsigned short piix4_smba; 97 static int srvrworks_csb5_delay; 98 static struct pci_driver piix4_driver; 99 static struct i2c_adapter piix4_adapter; 100 101 static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = { 102 { 103 .ident = "Sapphire AM2RD790", 104 .matches = { 105 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), 106 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), 107 }, 108 }, 109 { 110 .ident = "DFI Lanparty UT 790FX", 111 .matches = { 112 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), 113 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), 114 }, 115 }, 116 { } 117 }; 118 119 /* The IBM entry is in a separate table because we only check it 120 on Intel-based systems */ 121 static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = { 122 { 123 .ident = "IBM", 124 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, 125 }, 126 { }, 127 }; 128 129 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev, 130 const struct pci_device_id *id) 131 { 132 unsigned char temp; 133 134 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && 135 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) 136 srvrworks_csb5_delay = 1; 137 138 /* On some motherboards, it was reported that accessing the SMBus 139 caused severe hardware problems */ 140 if (dmi_check_system(piix4_dmi_blacklist)) { 141 dev_err(&PIIX4_dev->dev, 142 "Accessing the SMBus on this system is unsafe!\n"); 143 return -EPERM; 144 } 145 146 /* Don't access SMBus on IBM systems which get corrupted eeproms */ 147 if (dmi_check_system(piix4_dmi_ibm) && 148 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { 149 dev_err(&PIIX4_dev->dev, "IBM system detected; this module " 150 "may corrupt your serial eeprom! Refusing to load " 151 "module!\n"); 152 return -EPERM; 153 } 154 155 /* Determine the address of the SMBus areas */ 156 if (force_addr) { 157 piix4_smba = force_addr & 0xfff0; 158 force = 0; 159 } else { 160 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); 161 piix4_smba &= 0xfff0; 162 if(piix4_smba == 0) { 163 dev_err(&PIIX4_dev->dev, "SMBus base address " 164 "uninitialized - upgrade BIOS or use " 165 "force_addr=0xaddr\n"); 166 return -ENODEV; 167 } 168 } 169 170 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 171 return -EBUSY; 172 173 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 174 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 175 piix4_smba); 176 return -EBUSY; 177 } 178 179 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); 180 181 /* If force_addr is set, we program the new address here. Just to make 182 sure, we disable the PIIX4 first. */ 183 if (force_addr) { 184 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); 185 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); 186 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); 187 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " 188 "new address %04x!\n", piix4_smba); 189 } else if ((temp & 1) == 0) { 190 if (force) { 191 /* This should never need to be done, but has been 192 * noted that many Dell machines have the SMBus 193 * interface on the PIIX4 disabled!? NOTE: This assumes 194 * I/O space and other allocations WERE done by the 195 * Bios! Don't complain if your hardware does weird 196 * things after enabling this. :') Check for Bios 197 * updates before resorting to this. 198 */ 199 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, 200 temp | 1); 201 dev_printk(KERN_NOTICE, &PIIX4_dev->dev, 202 "WARNING: SMBus interface has been " 203 "FORCEFULLY ENABLED!\n"); 204 } else { 205 dev_err(&PIIX4_dev->dev, 206 "Host SMBus controller not enabled!\n"); 207 release_region(piix4_smba, SMBIOSIZE); 208 piix4_smba = 0; 209 return -ENODEV; 210 } 211 } 212 213 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) 214 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n"); 215 else if ((temp & 0x0E) == 0) 216 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n"); 217 else 218 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " 219 "(or code out of date)!\n"); 220 221 pci_read_config_byte(PIIX4_dev, SMBREV, &temp); 222 dev_info(&PIIX4_dev->dev, 223 "SMBus Host Controller at 0x%x, revision %d\n", 224 piix4_smba, temp); 225 226 return 0; 227 } 228 229 static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev, 230 const struct pci_device_id *id) 231 { 232 unsigned short smba_idx = 0xcd6; 233 u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c; 234 235 /* SB800 SMBus does not support forcing address */ 236 if (force || force_addr) { 237 dev_err(&PIIX4_dev->dev, "SB800 SMBus does not support " 238 "forcing address!\n"); 239 return -EINVAL; 240 } 241 242 /* Determine the address of the SMBus areas */ 243 if (!request_region(smba_idx, 2, "smba_idx")) { 244 dev_err(&PIIX4_dev->dev, "SMBus base address index region " 245 "0x%x already in use!\n", smba_idx); 246 return -EBUSY; 247 } 248 outb_p(smb_en, smba_idx); 249 smba_en_lo = inb_p(smba_idx + 1); 250 outb_p(smb_en + 1, smba_idx); 251 smba_en_hi = inb_p(smba_idx + 1); 252 release_region(smba_idx, 2); 253 254 if ((smba_en_lo & 1) == 0) { 255 dev_err(&PIIX4_dev->dev, 256 "Host SMBus controller not enabled!\n"); 257 return -ENODEV; 258 } 259 260 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; 261 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 262 return -EBUSY; 263 264 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 265 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 266 piix4_smba); 267 return -EBUSY; 268 } 269 270 /* Request the SMBus I2C bus config region */ 271 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { 272 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " 273 "0x%x already in use!\n", piix4_smba + i2ccfg_offset); 274 release_region(piix4_smba, SMBIOSIZE); 275 piix4_smba = 0; 276 return -EBUSY; 277 } 278 i2ccfg = inb_p(piix4_smba + i2ccfg_offset); 279 release_region(piix4_smba + i2ccfg_offset, 1); 280 281 if (i2ccfg & 1) 282 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n"); 283 else 284 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n"); 285 286 dev_info(&PIIX4_dev->dev, 287 "SMBus Host Controller at 0x%x, revision %d\n", 288 piix4_smba, i2ccfg >> 4); 289 290 return 0; 291 } 292 293 static int piix4_transaction(void) 294 { 295 int temp; 296 int result = 0; 297 int timeout = 0; 298 299 dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 300 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 301 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 302 inb_p(SMBHSTDAT1)); 303 304 /* Make sure the SMBus host is ready to start transmitting */ 305 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 306 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). " 307 "Resetting...\n", temp); 308 outb_p(temp, SMBHSTSTS); 309 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 310 dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp); 311 return -EBUSY; 312 } else { 313 dev_dbg(&piix4_adapter.dev, "Successful!\n"); 314 } 315 } 316 317 /* start the transaction by setting bit 6 */ 318 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); 319 320 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ 321 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ 322 msleep(2); 323 else 324 msleep(1); 325 326 while ((timeout++ < MAX_TIMEOUT) && 327 ((temp = inb_p(SMBHSTSTS)) & 0x01)) 328 msleep(1); 329 330 /* If the SMBus is still busy, we give up */ 331 if (timeout >= MAX_TIMEOUT) { 332 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n"); 333 result = -ETIMEDOUT; 334 } 335 336 if (temp & 0x10) { 337 result = -EIO; 338 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n"); 339 } 340 341 if (temp & 0x08) { 342 result = -EIO; 343 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be " 344 "locked until next hard reset. (sorry!)\n"); 345 /* Clock stops and slave is stuck in mid-transmission */ 346 } 347 348 if (temp & 0x04) { 349 result = -ENXIO; 350 dev_dbg(&piix4_adapter.dev, "Error: no response!\n"); 351 } 352 353 if (inb_p(SMBHSTSTS) != 0x00) 354 outb_p(inb(SMBHSTSTS), SMBHSTSTS); 355 356 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 357 dev_err(&piix4_adapter.dev, "Failed reset at end of " 358 "transaction (%02x)\n", temp); 359 } 360 dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, " 361 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 362 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 363 inb_p(SMBHSTDAT1)); 364 return result; 365 } 366 367 /* Return negative errno on error. */ 368 static s32 piix4_access(struct i2c_adapter * adap, u16 addr, 369 unsigned short flags, char read_write, 370 u8 command, int size, union i2c_smbus_data * data) 371 { 372 int i, len; 373 int status; 374 375 switch (size) { 376 case I2C_SMBUS_QUICK: 377 outb_p((addr << 1) | read_write, 378 SMBHSTADD); 379 size = PIIX4_QUICK; 380 break; 381 case I2C_SMBUS_BYTE: 382 outb_p((addr << 1) | read_write, 383 SMBHSTADD); 384 if (read_write == I2C_SMBUS_WRITE) 385 outb_p(command, SMBHSTCMD); 386 size = PIIX4_BYTE; 387 break; 388 case I2C_SMBUS_BYTE_DATA: 389 outb_p((addr << 1) | read_write, 390 SMBHSTADD); 391 outb_p(command, SMBHSTCMD); 392 if (read_write == I2C_SMBUS_WRITE) 393 outb_p(data->byte, SMBHSTDAT0); 394 size = PIIX4_BYTE_DATA; 395 break; 396 case I2C_SMBUS_WORD_DATA: 397 outb_p((addr << 1) | read_write, 398 SMBHSTADD); 399 outb_p(command, SMBHSTCMD); 400 if (read_write == I2C_SMBUS_WRITE) { 401 outb_p(data->word & 0xff, SMBHSTDAT0); 402 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); 403 } 404 size = PIIX4_WORD_DATA; 405 break; 406 case I2C_SMBUS_BLOCK_DATA: 407 outb_p((addr << 1) | read_write, 408 SMBHSTADD); 409 outb_p(command, SMBHSTCMD); 410 if (read_write == I2C_SMBUS_WRITE) { 411 len = data->block[0]; 412 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 413 return -EINVAL; 414 outb_p(len, SMBHSTDAT0); 415 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 416 for (i = 1; i <= len; i++) 417 outb_p(data->block[i], SMBBLKDAT); 418 } 419 size = PIIX4_BLOCK_DATA; 420 break; 421 default: 422 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 423 return -EOPNOTSUPP; 424 } 425 426 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); 427 428 status = piix4_transaction(); 429 if (status) 430 return status; 431 432 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) 433 return 0; 434 435 436 switch (size) { 437 case PIIX4_BYTE: 438 case PIIX4_BYTE_DATA: 439 data->byte = inb_p(SMBHSTDAT0); 440 break; 441 case PIIX4_WORD_DATA: 442 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); 443 break; 444 case PIIX4_BLOCK_DATA: 445 data->block[0] = inb_p(SMBHSTDAT0); 446 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 447 return -EPROTO; 448 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 449 for (i = 1; i <= data->block[0]; i++) 450 data->block[i] = inb_p(SMBBLKDAT); 451 break; 452 } 453 return 0; 454 } 455 456 static u32 piix4_func(struct i2c_adapter *adapter) 457 { 458 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 459 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 460 I2C_FUNC_SMBUS_BLOCK_DATA; 461 } 462 463 static const struct i2c_algorithm smbus_algorithm = { 464 .smbus_xfer = piix4_access, 465 .functionality = piix4_func, 466 }; 467 468 static struct i2c_adapter piix4_adapter = { 469 .owner = THIS_MODULE, 470 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 471 .algo = &smbus_algorithm, 472 }; 473 474 static struct pci_device_id piix4_ids[] = { 475 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, 476 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, 477 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, 478 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, 479 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, 480 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, 481 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, 482 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 483 PCI_DEVICE_ID_SERVERWORKS_OSB4) }, 484 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 485 PCI_DEVICE_ID_SERVERWORKS_CSB5) }, 486 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 487 PCI_DEVICE_ID_SERVERWORKS_CSB6) }, 488 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 489 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, 490 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 491 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, 492 { 0, } 493 }; 494 495 MODULE_DEVICE_TABLE (pci, piix4_ids); 496 497 static int __devinit piix4_probe(struct pci_dev *dev, 498 const struct pci_device_id *id) 499 { 500 int retval; 501 502 if ((dev->vendor == PCI_VENDOR_ID_ATI) && 503 (dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) && 504 (dev->revision >= 0x40)) 505 /* base address location etc changed in SB800 */ 506 retval = piix4_setup_sb800(dev, id); 507 else 508 retval = piix4_setup(dev, id); 509 510 if (retval) 511 return retval; 512 513 /* set up the sysfs linkage to our parent device */ 514 piix4_adapter.dev.parent = &dev->dev; 515 516 snprintf(piix4_adapter.name, sizeof(piix4_adapter.name), 517 "SMBus PIIX4 adapter at %04x", piix4_smba); 518 519 if ((retval = i2c_add_adapter(&piix4_adapter))) { 520 dev_err(&dev->dev, "Couldn't register adapter!\n"); 521 release_region(piix4_smba, SMBIOSIZE); 522 piix4_smba = 0; 523 } 524 525 return retval; 526 } 527 528 static void __devexit piix4_remove(struct pci_dev *dev) 529 { 530 if (piix4_smba) { 531 i2c_del_adapter(&piix4_adapter); 532 release_region(piix4_smba, SMBIOSIZE); 533 piix4_smba = 0; 534 } 535 } 536 537 static struct pci_driver piix4_driver = { 538 .name = "piix4_smbus", 539 .id_table = piix4_ids, 540 .probe = piix4_probe, 541 .remove = __devexit_p(piix4_remove), 542 }; 543 544 static int __init i2c_piix4_init(void) 545 { 546 return pci_register_driver(&piix4_driver); 547 } 548 549 static void __exit i2c_piix4_exit(void) 550 { 551 pci_unregister_driver(&piix4_driver); 552 } 553 554 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " 555 "Philip Edelbrock <phil@netroedge.com>"); 556 MODULE_DESCRIPTION("PIIX4 SMBus driver"); 557 MODULE_LICENSE("GPL"); 558 559 module_init(i2c_piix4_init); 560 module_exit(i2c_piix4_exit); 561