1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 3 Philip Edelbrock <phil@netroedge.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 */ 15 16 /* 17 Supports: 18 Intel PIIX4, 440MX 19 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 20 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 21 AMD Hudson-2, ML, CZ 22 Hygon CZ 23 SMSC Victory66 24 25 Note: we assume there can only be one device, with one or more 26 SMBus interfaces. 27 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS). 28 For devices supporting multiple ports the i2c_adapter should provide 29 an i2c_algorithm to access them. 30 */ 31 32 #include <linux/module.h> 33 #include <linux/moduleparam.h> 34 #include <linux/pci.h> 35 #include <linux/kernel.h> 36 #include <linux/delay.h> 37 #include <linux/stddef.h> 38 #include <linux/ioport.h> 39 #include <linux/i2c.h> 40 #include <linux/slab.h> 41 #include <linux/dmi.h> 42 #include <linux/acpi.h> 43 #include <linux/io.h> 44 45 46 /* PIIX4 SMBus address offsets */ 47 #define SMBHSTSTS (0 + piix4_smba) 48 #define SMBHSLVSTS (1 + piix4_smba) 49 #define SMBHSTCNT (2 + piix4_smba) 50 #define SMBHSTCMD (3 + piix4_smba) 51 #define SMBHSTADD (4 + piix4_smba) 52 #define SMBHSTDAT0 (5 + piix4_smba) 53 #define SMBHSTDAT1 (6 + piix4_smba) 54 #define SMBBLKDAT (7 + piix4_smba) 55 #define SMBSLVCNT (8 + piix4_smba) 56 #define SMBSHDWCMD (9 + piix4_smba) 57 #define SMBSLVEVT (0xA + piix4_smba) 58 #define SMBSLVDAT (0xC + piix4_smba) 59 60 /* count for request_region */ 61 #define SMBIOSIZE 9 62 63 /* PCI Address Constants */ 64 #define SMBBA 0x090 65 #define SMBHSTCFG 0x0D2 66 #define SMBSLVC 0x0D3 67 #define SMBSHDW1 0x0D4 68 #define SMBSHDW2 0x0D5 69 #define SMBREV 0x0D6 70 71 /* Other settings */ 72 #define MAX_TIMEOUT 500 73 #define ENABLE_INT9 0 74 75 /* PIIX4 constants */ 76 #define PIIX4_QUICK 0x00 77 #define PIIX4_BYTE 0x04 78 #define PIIX4_BYTE_DATA 0x08 79 #define PIIX4_WORD_DATA 0x0C 80 #define PIIX4_BLOCK_DATA 0x14 81 82 /* Multi-port constants */ 83 #define PIIX4_MAX_ADAPTERS 4 84 85 /* SB800 constants */ 86 #define SB800_PIIX4_SMB_IDX 0xcd6 87 88 #define KERNCZ_IMC_IDX 0x3e 89 #define KERNCZ_IMC_DATA 0x3f 90 91 /* 92 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c) 93 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f. 94 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f. 95 */ 96 #define SB800_PIIX4_PORT_IDX 0x2c 97 #define SB800_PIIX4_PORT_IDX_ALT 0x2e 98 #define SB800_PIIX4_PORT_IDX_SEL 0x2f 99 #define SB800_PIIX4_PORT_IDX_MASK 0x06 100 #define SB800_PIIX4_PORT_IDX_SHIFT 1 101 102 /* On kerncz, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */ 103 #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02 104 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18 105 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3 106 107 /* insmod parameters */ 108 109 /* If force is set to anything different from 0, we forcibly enable the 110 PIIX4. DANGEROUS! */ 111 static int force; 112 module_param (force, int, 0); 113 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); 114 115 /* If force_addr is set to anything different from 0, we forcibly enable 116 the PIIX4 at the given address. VERY DANGEROUS! */ 117 static int force_addr; 118 module_param_hw(force_addr, int, ioport, 0); 119 MODULE_PARM_DESC(force_addr, 120 "Forcibly enable the PIIX4 at the given address. " 121 "EXTREMELY DANGEROUS!"); 122 123 static int srvrworks_csb5_delay; 124 static struct pci_driver piix4_driver; 125 126 static const struct dmi_system_id piix4_dmi_blacklist[] = { 127 { 128 .ident = "Sapphire AM2RD790", 129 .matches = { 130 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), 131 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), 132 }, 133 }, 134 { 135 .ident = "DFI Lanparty UT 790FX", 136 .matches = { 137 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), 138 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), 139 }, 140 }, 141 { } 142 }; 143 144 /* The IBM entry is in a separate table because we only check it 145 on Intel-based systems */ 146 static const struct dmi_system_id piix4_dmi_ibm[] = { 147 { 148 .ident = "IBM", 149 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, 150 }, 151 { }, 152 }; 153 154 /* 155 * SB800 globals 156 */ 157 static u8 piix4_port_sel_sb800; 158 static u8 piix4_port_mask_sb800; 159 static u8 piix4_port_shift_sb800; 160 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = { 161 " port 0", " port 2", " port 3", " port 4" 162 }; 163 static const char *piix4_aux_port_name_sb800 = " port 1"; 164 165 struct i2c_piix4_adapdata { 166 unsigned short smba; 167 168 /* SB800 */ 169 bool sb800_main; 170 bool notify_imc; 171 u8 port; /* Port number, shifted */ 172 }; 173 174 static int piix4_setup(struct pci_dev *PIIX4_dev, 175 const struct pci_device_id *id) 176 { 177 unsigned char temp; 178 unsigned short piix4_smba; 179 180 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && 181 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) 182 srvrworks_csb5_delay = 1; 183 184 /* On some motherboards, it was reported that accessing the SMBus 185 caused severe hardware problems */ 186 if (dmi_check_system(piix4_dmi_blacklist)) { 187 dev_err(&PIIX4_dev->dev, 188 "Accessing the SMBus on this system is unsafe!\n"); 189 return -EPERM; 190 } 191 192 /* Don't access SMBus on IBM systems which get corrupted eeproms */ 193 if (dmi_check_system(piix4_dmi_ibm) && 194 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { 195 dev_err(&PIIX4_dev->dev, "IBM system detected; this module " 196 "may corrupt your serial eeprom! Refusing to load " 197 "module!\n"); 198 return -EPERM; 199 } 200 201 /* Determine the address of the SMBus areas */ 202 if (force_addr) { 203 piix4_smba = force_addr & 0xfff0; 204 force = 0; 205 } else { 206 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); 207 piix4_smba &= 0xfff0; 208 if(piix4_smba == 0) { 209 dev_err(&PIIX4_dev->dev, "SMBus base address " 210 "uninitialized - upgrade BIOS or use " 211 "force_addr=0xaddr\n"); 212 return -ENODEV; 213 } 214 } 215 216 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 217 return -ENODEV; 218 219 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 220 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 221 piix4_smba); 222 return -EBUSY; 223 } 224 225 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); 226 227 /* If force_addr is set, we program the new address here. Just to make 228 sure, we disable the PIIX4 first. */ 229 if (force_addr) { 230 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); 231 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); 232 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); 233 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " 234 "new address %04x!\n", piix4_smba); 235 } else if ((temp & 1) == 0) { 236 if (force) { 237 /* This should never need to be done, but has been 238 * noted that many Dell machines have the SMBus 239 * interface on the PIIX4 disabled!? NOTE: This assumes 240 * I/O space and other allocations WERE done by the 241 * Bios! Don't complain if your hardware does weird 242 * things after enabling this. :') Check for Bios 243 * updates before resorting to this. 244 */ 245 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, 246 temp | 1); 247 dev_notice(&PIIX4_dev->dev, 248 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); 249 } else { 250 dev_err(&PIIX4_dev->dev, 251 "SMBus Host Controller not enabled!\n"); 252 release_region(piix4_smba, SMBIOSIZE); 253 return -ENODEV; 254 } 255 } 256 257 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) 258 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 259 else if ((temp & 0x0E) == 0) 260 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 261 else 262 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " 263 "(or code out of date)!\n"); 264 265 pci_read_config_byte(PIIX4_dev, SMBREV, &temp); 266 dev_info(&PIIX4_dev->dev, 267 "SMBus Host Controller at 0x%x, revision %d\n", 268 piix4_smba, temp); 269 270 return piix4_smba; 271 } 272 273 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, 274 const struct pci_device_id *id, u8 aux) 275 { 276 unsigned short piix4_smba; 277 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel; 278 u8 i2ccfg, i2ccfg_offset = 0x10; 279 280 /* SB800 and later SMBus does not support forcing address */ 281 if (force || force_addr) { 282 dev_err(&PIIX4_dev->dev, "SMBus does not support " 283 "forcing address!\n"); 284 return -EINVAL; 285 } 286 287 /* Determine the address of the SMBus areas */ 288 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 289 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 290 PIIX4_dev->revision >= 0x41) || 291 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 292 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 293 PIIX4_dev->revision >= 0x49) || 294 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON && 295 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) 296 smb_en = 0x00; 297 else 298 smb_en = (aux) ? 0x28 : 0x2c; 299 300 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) { 301 dev_err(&PIIX4_dev->dev, 302 "SMB base address index region 0x%x already in use.\n", 303 SB800_PIIX4_SMB_IDX); 304 return -EBUSY; 305 } 306 307 outb_p(smb_en, SB800_PIIX4_SMB_IDX); 308 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 309 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); 310 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); 311 312 release_region(SB800_PIIX4_SMB_IDX, 2); 313 314 if (!smb_en) { 315 smb_en_status = smba_en_lo & 0x10; 316 piix4_smba = smba_en_hi << 8; 317 if (aux) 318 piix4_smba |= 0x20; 319 } else { 320 smb_en_status = smba_en_lo & 0x01; 321 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; 322 } 323 324 if (!smb_en_status) { 325 dev_err(&PIIX4_dev->dev, 326 "SMBus Host Controller not enabled!\n"); 327 return -ENODEV; 328 } 329 330 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 331 return -ENODEV; 332 333 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 334 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 335 piix4_smba); 336 return -EBUSY; 337 } 338 339 /* Aux SMBus does not support IRQ information */ 340 if (aux) { 341 dev_info(&PIIX4_dev->dev, 342 "Auxiliary SMBus Host Controller at 0x%x\n", 343 piix4_smba); 344 return piix4_smba; 345 } 346 347 /* Request the SMBus I2C bus config region */ 348 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { 349 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " 350 "0x%x already in use!\n", piix4_smba + i2ccfg_offset); 351 release_region(piix4_smba, SMBIOSIZE); 352 return -EBUSY; 353 } 354 i2ccfg = inb_p(piix4_smba + i2ccfg_offset); 355 release_region(piix4_smba + i2ccfg_offset, 1); 356 357 if (i2ccfg & 1) 358 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 359 else 360 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 361 362 dev_info(&PIIX4_dev->dev, 363 "SMBus Host Controller at 0x%x, revision %d\n", 364 piix4_smba, i2ccfg >> 4); 365 366 /* Find which register is used for port selection */ 367 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD || 368 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) { 369 switch (PIIX4_dev->device) { 370 case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS: 371 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ; 372 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ; 373 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ; 374 break; 375 case PCI_DEVICE_ID_AMD_HUDSON2_SMBUS: 376 default: 377 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT; 378 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; 379 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; 380 break; 381 } 382 } else { 383 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, 384 "sb800_piix4_smb")) { 385 release_region(piix4_smba, SMBIOSIZE); 386 return -EBUSY; 387 } 388 389 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX); 390 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); 391 piix4_port_sel_sb800 = (port_sel & 0x01) ? 392 SB800_PIIX4_PORT_IDX_ALT : 393 SB800_PIIX4_PORT_IDX; 394 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; 395 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; 396 release_region(SB800_PIIX4_SMB_IDX, 2); 397 } 398 399 dev_info(&PIIX4_dev->dev, 400 "Using register 0x%02x for SMBus port selection\n", 401 (unsigned int)piix4_port_sel_sb800); 402 403 return piix4_smba; 404 } 405 406 static int piix4_setup_aux(struct pci_dev *PIIX4_dev, 407 const struct pci_device_id *id, 408 unsigned short base_reg_addr) 409 { 410 /* Set up auxiliary SMBus controllers found on some 411 * AMD chipsets e.g. SP5100 (SB700 derivative) */ 412 413 unsigned short piix4_smba; 414 415 /* Read address of auxiliary SMBus controller */ 416 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); 417 if ((piix4_smba & 1) == 0) { 418 dev_dbg(&PIIX4_dev->dev, 419 "Auxiliary SMBus controller not enabled\n"); 420 return -ENODEV; 421 } 422 423 piix4_smba &= 0xfff0; 424 if (piix4_smba == 0) { 425 dev_dbg(&PIIX4_dev->dev, 426 "Auxiliary SMBus base address uninitialized\n"); 427 return -ENODEV; 428 } 429 430 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 431 return -ENODEV; 432 433 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 434 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " 435 "already in use!\n", piix4_smba); 436 return -EBUSY; 437 } 438 439 dev_info(&PIIX4_dev->dev, 440 "Auxiliary SMBus Host Controller at 0x%x\n", 441 piix4_smba); 442 443 return piix4_smba; 444 } 445 446 static int piix4_transaction(struct i2c_adapter *piix4_adapter) 447 { 448 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter); 449 unsigned short piix4_smba = adapdata->smba; 450 int temp; 451 int result = 0; 452 int timeout = 0; 453 454 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 455 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 456 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 457 inb_p(SMBHSTDAT1)); 458 459 /* Make sure the SMBus host is ready to start transmitting */ 460 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 461 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " 462 "Resetting...\n", temp); 463 outb_p(temp, SMBHSTSTS); 464 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 465 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); 466 return -EBUSY; 467 } else { 468 dev_dbg(&piix4_adapter->dev, "Successful!\n"); 469 } 470 } 471 472 /* start the transaction by setting bit 6 */ 473 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); 474 475 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ 476 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ 477 usleep_range(2000, 2100); 478 else 479 usleep_range(250, 500); 480 481 while ((++timeout < MAX_TIMEOUT) && 482 ((temp = inb_p(SMBHSTSTS)) & 0x01)) 483 usleep_range(250, 500); 484 485 /* If the SMBus is still busy, we give up */ 486 if (timeout == MAX_TIMEOUT) { 487 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); 488 result = -ETIMEDOUT; 489 } 490 491 if (temp & 0x10) { 492 result = -EIO; 493 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); 494 } 495 496 if (temp & 0x08) { 497 result = -EIO; 498 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " 499 "locked until next hard reset. (sorry!)\n"); 500 /* Clock stops and slave is stuck in mid-transmission */ 501 } 502 503 if (temp & 0x04) { 504 result = -ENXIO; 505 dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); 506 } 507 508 if (inb_p(SMBHSTSTS) != 0x00) 509 outb_p(inb(SMBHSTSTS), SMBHSTSTS); 510 511 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 512 dev_err(&piix4_adapter->dev, "Failed reset at end of " 513 "transaction (%02x)\n", temp); 514 } 515 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " 516 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 517 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 518 inb_p(SMBHSTDAT1)); 519 return result; 520 } 521 522 /* Return negative errno on error. */ 523 static s32 piix4_access(struct i2c_adapter * adap, u16 addr, 524 unsigned short flags, char read_write, 525 u8 command, int size, union i2c_smbus_data * data) 526 { 527 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 528 unsigned short piix4_smba = adapdata->smba; 529 int i, len; 530 int status; 531 532 switch (size) { 533 case I2C_SMBUS_QUICK: 534 outb_p((addr << 1) | read_write, 535 SMBHSTADD); 536 size = PIIX4_QUICK; 537 break; 538 case I2C_SMBUS_BYTE: 539 outb_p((addr << 1) | read_write, 540 SMBHSTADD); 541 if (read_write == I2C_SMBUS_WRITE) 542 outb_p(command, SMBHSTCMD); 543 size = PIIX4_BYTE; 544 break; 545 case I2C_SMBUS_BYTE_DATA: 546 outb_p((addr << 1) | read_write, 547 SMBHSTADD); 548 outb_p(command, SMBHSTCMD); 549 if (read_write == I2C_SMBUS_WRITE) 550 outb_p(data->byte, SMBHSTDAT0); 551 size = PIIX4_BYTE_DATA; 552 break; 553 case I2C_SMBUS_WORD_DATA: 554 outb_p((addr << 1) | read_write, 555 SMBHSTADD); 556 outb_p(command, SMBHSTCMD); 557 if (read_write == I2C_SMBUS_WRITE) { 558 outb_p(data->word & 0xff, SMBHSTDAT0); 559 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); 560 } 561 size = PIIX4_WORD_DATA; 562 break; 563 case I2C_SMBUS_BLOCK_DATA: 564 outb_p((addr << 1) | read_write, 565 SMBHSTADD); 566 outb_p(command, SMBHSTCMD); 567 if (read_write == I2C_SMBUS_WRITE) { 568 len = data->block[0]; 569 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 570 return -EINVAL; 571 outb_p(len, SMBHSTDAT0); 572 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 573 for (i = 1; i <= len; i++) 574 outb_p(data->block[i], SMBBLKDAT); 575 } 576 size = PIIX4_BLOCK_DATA; 577 break; 578 default: 579 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 580 return -EOPNOTSUPP; 581 } 582 583 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); 584 585 status = piix4_transaction(adap); 586 if (status) 587 return status; 588 589 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) 590 return 0; 591 592 593 switch (size) { 594 case PIIX4_BYTE: 595 case PIIX4_BYTE_DATA: 596 data->byte = inb_p(SMBHSTDAT0); 597 break; 598 case PIIX4_WORD_DATA: 599 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); 600 break; 601 case PIIX4_BLOCK_DATA: 602 data->block[0] = inb_p(SMBHSTDAT0); 603 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 604 return -EPROTO; 605 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 606 for (i = 1; i <= data->block[0]; i++) 607 data->block[i] = inb_p(SMBBLKDAT); 608 break; 609 } 610 return 0; 611 } 612 613 static uint8_t piix4_imc_read(uint8_t idx) 614 { 615 outb_p(idx, KERNCZ_IMC_IDX); 616 return inb_p(KERNCZ_IMC_DATA); 617 } 618 619 static void piix4_imc_write(uint8_t idx, uint8_t value) 620 { 621 outb_p(idx, KERNCZ_IMC_IDX); 622 outb_p(value, KERNCZ_IMC_DATA); 623 } 624 625 static int piix4_imc_sleep(void) 626 { 627 int timeout = MAX_TIMEOUT; 628 629 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) 630 return -EBUSY; 631 632 /* clear response register */ 633 piix4_imc_write(0x82, 0x00); 634 /* request ownership flag */ 635 piix4_imc_write(0x83, 0xB4); 636 /* kick off IMC Mailbox command 96 */ 637 piix4_imc_write(0x80, 0x96); 638 639 while (timeout--) { 640 if (piix4_imc_read(0x82) == 0xfa) { 641 release_region(KERNCZ_IMC_IDX, 2); 642 return 0; 643 } 644 usleep_range(1000, 2000); 645 } 646 647 release_region(KERNCZ_IMC_IDX, 2); 648 return -ETIMEDOUT; 649 } 650 651 static void piix4_imc_wakeup(void) 652 { 653 int timeout = MAX_TIMEOUT; 654 655 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) 656 return; 657 658 /* clear response register */ 659 piix4_imc_write(0x82, 0x00); 660 /* release ownership flag */ 661 piix4_imc_write(0x83, 0xB5); 662 /* kick off IMC Mailbox command 96 */ 663 piix4_imc_write(0x80, 0x96); 664 665 while (timeout--) { 666 if (piix4_imc_read(0x82) == 0xfa) 667 break; 668 usleep_range(1000, 2000); 669 } 670 671 release_region(KERNCZ_IMC_IDX, 2); 672 } 673 674 /* 675 * Handles access to multiple SMBus ports on the SB800. 676 * The port is selected by bits 2:1 of the smb_en register (0x2c). 677 * Returns negative errno on error. 678 * 679 * Note: The selected port must be returned to the initial selection to avoid 680 * problems on certain systems. 681 */ 682 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, 683 unsigned short flags, char read_write, 684 u8 command, int size, union i2c_smbus_data *data) 685 { 686 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 687 unsigned short piix4_smba = adapdata->smba; 688 int retries = MAX_TIMEOUT; 689 int smbslvcnt; 690 u8 smba_en_lo; 691 u8 port; 692 int retval; 693 694 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) 695 return -EBUSY; 696 697 /* Request the SMBUS semaphore, avoid conflicts with the IMC */ 698 smbslvcnt = inb_p(SMBSLVCNT); 699 do { 700 outb_p(smbslvcnt | 0x10, SMBSLVCNT); 701 702 /* Check the semaphore status */ 703 smbslvcnt = inb_p(SMBSLVCNT); 704 if (smbslvcnt & 0x10) 705 break; 706 707 usleep_range(1000, 2000); 708 } while (--retries); 709 /* SMBus is still owned by the IMC, we give up */ 710 if (!retries) { 711 retval = -EBUSY; 712 goto release; 713 } 714 715 /* 716 * Notify the IMC (Integrated Micro Controller) if required. 717 * Among other responsibilities, the IMC is in charge of monitoring 718 * the System fans and temperature sensors, and act accordingly. 719 * All this is done through SMBus and can/will collide 720 * with our transactions if they are long (BLOCK_DATA). 721 * Therefore we need to request the ownership flag during those 722 * transactions. 723 */ 724 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) { 725 int ret; 726 727 ret = piix4_imc_sleep(); 728 switch (ret) { 729 case -EBUSY: 730 dev_warn(&adap->dev, 731 "IMC base address index region 0x%x already in use.\n", 732 KERNCZ_IMC_IDX); 733 break; 734 case -ETIMEDOUT: 735 dev_warn(&adap->dev, 736 "Failed to communicate with the IMC.\n"); 737 break; 738 default: 739 break; 740 } 741 742 /* If IMC communication fails do not retry */ 743 if (ret) { 744 dev_warn(&adap->dev, 745 "Continuing without IMC notification.\n"); 746 adapdata->notify_imc = false; 747 } 748 } 749 750 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); 751 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 752 753 port = adapdata->port; 754 if ((smba_en_lo & piix4_port_mask_sb800) != port) 755 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port, 756 SB800_PIIX4_SMB_IDX + 1); 757 758 retval = piix4_access(adap, addr, flags, read_write, 759 command, size, data); 760 761 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1); 762 763 /* Release the semaphore */ 764 outb_p(smbslvcnt | 0x20, SMBSLVCNT); 765 766 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) 767 piix4_imc_wakeup(); 768 769 release: 770 release_region(SB800_PIIX4_SMB_IDX, 2); 771 return retval; 772 } 773 774 static u32 piix4_func(struct i2c_adapter *adapter) 775 { 776 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 777 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 778 I2C_FUNC_SMBUS_BLOCK_DATA; 779 } 780 781 static const struct i2c_algorithm smbus_algorithm = { 782 .smbus_xfer = piix4_access, 783 .functionality = piix4_func, 784 }; 785 786 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = { 787 .smbus_xfer = piix4_access_sb800, 788 .functionality = piix4_func, 789 }; 790 791 static const struct pci_device_id piix4_ids[] = { 792 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, 793 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, 794 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, 795 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, 796 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, 797 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, 798 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, 799 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, 800 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 801 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 802 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 803 PCI_DEVICE_ID_SERVERWORKS_OSB4) }, 804 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 805 PCI_DEVICE_ID_SERVERWORKS_CSB5) }, 806 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 807 PCI_DEVICE_ID_SERVERWORKS_CSB6) }, 808 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 809 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, 810 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 811 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, 812 { 0, } 813 }; 814 815 MODULE_DEVICE_TABLE (pci, piix4_ids); 816 817 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS]; 818 static struct i2c_adapter *piix4_aux_adapter; 819 820 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, 821 bool sb800_main, u8 port, bool notify_imc, 822 const char *name, struct i2c_adapter **padap) 823 { 824 struct i2c_adapter *adap; 825 struct i2c_piix4_adapdata *adapdata; 826 int retval; 827 828 adap = kzalloc(sizeof(*adap), GFP_KERNEL); 829 if (adap == NULL) { 830 release_region(smba, SMBIOSIZE); 831 return -ENOMEM; 832 } 833 834 adap->owner = THIS_MODULE; 835 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 836 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800 837 : &smbus_algorithm; 838 839 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); 840 if (adapdata == NULL) { 841 kfree(adap); 842 release_region(smba, SMBIOSIZE); 843 return -ENOMEM; 844 } 845 846 adapdata->smba = smba; 847 adapdata->sb800_main = sb800_main; 848 adapdata->port = port << piix4_port_shift_sb800; 849 adapdata->notify_imc = notify_imc; 850 851 /* set up the sysfs linkage to our parent device */ 852 adap->dev.parent = &dev->dev; 853 854 snprintf(adap->name, sizeof(adap->name), 855 "SMBus PIIX4 adapter%s at %04x", name, smba); 856 857 i2c_set_adapdata(adap, adapdata); 858 859 retval = i2c_add_adapter(adap); 860 if (retval) { 861 kfree(adapdata); 862 kfree(adap); 863 release_region(smba, SMBIOSIZE); 864 return retval; 865 } 866 867 *padap = adap; 868 return 0; 869 } 870 871 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba, 872 bool notify_imc) 873 { 874 struct i2c_piix4_adapdata *adapdata; 875 int port; 876 int retval; 877 878 for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) { 879 retval = piix4_add_adapter(dev, smba, true, port, notify_imc, 880 piix4_main_port_names_sb800[port], 881 &piix4_main_adapters[port]); 882 if (retval < 0) 883 goto error; 884 } 885 886 return retval; 887 888 error: 889 dev_err(&dev->dev, 890 "Error setting up SB800 adapters. Unregistering!\n"); 891 while (--port >= 0) { 892 adapdata = i2c_get_adapdata(piix4_main_adapters[port]); 893 if (adapdata->smba) { 894 i2c_del_adapter(piix4_main_adapters[port]); 895 kfree(adapdata); 896 kfree(piix4_main_adapters[port]); 897 piix4_main_adapters[port] = NULL; 898 } 899 } 900 901 return retval; 902 } 903 904 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) 905 { 906 int retval; 907 bool is_sb800 = false; 908 909 if ((dev->vendor == PCI_VENDOR_ID_ATI && 910 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && 911 dev->revision >= 0x40) || 912 dev->vendor == PCI_VENDOR_ID_AMD || 913 dev->vendor == PCI_VENDOR_ID_HYGON) { 914 bool notify_imc = false; 915 is_sb800 = true; 916 917 if ((dev->vendor == PCI_VENDOR_ID_AMD || 918 dev->vendor == PCI_VENDOR_ID_HYGON) && 919 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) { 920 u8 imc; 921 922 /* 923 * Detect if IMC is active or not, this method is 924 * described on coreboot's AMD IMC notes 925 */ 926 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3), 927 0x40, &imc); 928 if (imc & 0x80) 929 notify_imc = true; 930 } 931 932 /* base address location etc changed in SB800 */ 933 retval = piix4_setup_sb800(dev, id, 0); 934 if (retval < 0) 935 return retval; 936 937 /* 938 * Try to register multiplexed main SMBus adapter, 939 * give up if we can't 940 */ 941 retval = piix4_add_adapters_sb800(dev, retval, notify_imc); 942 if (retval < 0) 943 return retval; 944 } else { 945 retval = piix4_setup(dev, id); 946 if (retval < 0) 947 return retval; 948 949 /* Try to register main SMBus adapter, give up if we can't */ 950 retval = piix4_add_adapter(dev, retval, false, 0, false, "", 951 &piix4_main_adapters[0]); 952 if (retval < 0) 953 return retval; 954 } 955 956 /* Check for auxiliary SMBus on some AMD chipsets */ 957 retval = -ENODEV; 958 959 if (dev->vendor == PCI_VENDOR_ID_ATI && 960 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { 961 if (dev->revision < 0x40) { 962 retval = piix4_setup_aux(dev, id, 0x58); 963 } else { 964 /* SB800 added aux bus too */ 965 retval = piix4_setup_sb800(dev, id, 1); 966 } 967 } 968 969 if (dev->vendor == PCI_VENDOR_ID_AMD && 970 dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { 971 retval = piix4_setup_sb800(dev, id, 1); 972 } 973 974 if (retval > 0) { 975 /* Try to add the aux adapter if it exists, 976 * piix4_add_adapter will clean up if this fails */ 977 piix4_add_adapter(dev, retval, false, 0, false, 978 is_sb800 ? piix4_aux_port_name_sb800 : "", 979 &piix4_aux_adapter); 980 } 981 982 return 0; 983 } 984 985 static void piix4_adap_remove(struct i2c_adapter *adap) 986 { 987 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 988 989 if (adapdata->smba) { 990 i2c_del_adapter(adap); 991 if (adapdata->port == (0 << piix4_port_shift_sb800)) 992 release_region(adapdata->smba, SMBIOSIZE); 993 kfree(adapdata); 994 kfree(adap); 995 } 996 } 997 998 static void piix4_remove(struct pci_dev *dev) 999 { 1000 int port = PIIX4_MAX_ADAPTERS; 1001 1002 while (--port >= 0) { 1003 if (piix4_main_adapters[port]) { 1004 piix4_adap_remove(piix4_main_adapters[port]); 1005 piix4_main_adapters[port] = NULL; 1006 } 1007 } 1008 1009 if (piix4_aux_adapter) { 1010 piix4_adap_remove(piix4_aux_adapter); 1011 piix4_aux_adapter = NULL; 1012 } 1013 } 1014 1015 static struct pci_driver piix4_driver = { 1016 .name = "piix4_smbus", 1017 .id_table = piix4_ids, 1018 .probe = piix4_probe, 1019 .remove = piix4_remove, 1020 }; 1021 1022 module_pci_driver(piix4_driver); 1023 1024 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " 1025 "Philip Edelbrock <phil@netroedge.com>"); 1026 MODULE_DESCRIPTION("PIIX4 SMBus driver"); 1027 MODULE_LICENSE("GPL"); 1028