1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2006-2007 PA Semi, Inc 4 * 5 * SMBus host driver for PA Semi PWRficient 6 */ 7 8 #include <linux/module.h> 9 #include <linux/pci.h> 10 #include <linux/kernel.h> 11 #include <linux/stddef.h> 12 #include <linux/sched.h> 13 #include <linux/i2c.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/io.h> 17 18 #include "i2c-pasemi-core.h" 19 20 /* Register offsets */ 21 #define REG_MTXFIFO 0x00 22 #define REG_MRXFIFO 0x04 23 #define REG_SMSTA 0x14 24 #define REG_CTL 0x1c 25 #define REG_REV 0x28 26 27 /* Register defs */ 28 #define MTXFIFO_READ 0x00000400 29 #define MTXFIFO_STOP 0x00000200 30 #define MTXFIFO_START 0x00000100 31 #define MTXFIFO_DATA_M 0x000000ff 32 33 #define MRXFIFO_EMPTY 0x00000100 34 #define MRXFIFO_DATA_M 0x000000ff 35 36 #define SMSTA_XEN 0x08000000 37 #define SMSTA_MTN 0x00200000 38 39 #define CTL_MRR 0x00000400 40 #define CTL_MTR 0x00000200 41 #define CTL_EN 0x00000800 42 #define CTL_CLK_M 0x000000ff 43 44 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) 45 { 46 dev_dbg(smbus->dev, "smbus write reg %x val %08x\n", reg, val); 47 iowrite32(val, smbus->ioaddr + reg); 48 } 49 50 static inline int reg_read(struct pasemi_smbus *smbus, int reg) 51 { 52 int ret; 53 ret = ioread32(smbus->ioaddr + reg); 54 dev_dbg(smbus->dev, "smbus read reg %x val %08x\n", reg, ret); 55 return ret; 56 } 57 58 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg)) 59 #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO) 60 61 static void pasemi_reset(struct pasemi_smbus *smbus) 62 { 63 u32 val = (CTL_MTR | CTL_MRR | (smbus->clk_div & CTL_CLK_M)); 64 65 if (smbus->hw_rev >= 6) 66 val |= CTL_EN; 67 68 reg_write(smbus, REG_CTL, val); 69 } 70 71 static void pasemi_smb_clear(struct pasemi_smbus *smbus) 72 { 73 unsigned int status; 74 75 status = reg_read(smbus, REG_SMSTA); 76 reg_write(smbus, REG_SMSTA, status); 77 } 78 79 static int pasemi_smb_waitready(struct pasemi_smbus *smbus) 80 { 81 int timeout = 10; 82 unsigned int status; 83 84 status = reg_read(smbus, REG_SMSTA); 85 86 while (!(status & SMSTA_XEN) && timeout--) { 87 msleep(1); 88 status = reg_read(smbus, REG_SMSTA); 89 } 90 91 /* Got NACK? */ 92 if (status & SMSTA_MTN) 93 return -ENXIO; 94 95 if (timeout < 0) { 96 dev_warn(smbus->dev, "Timeout, status 0x%08x\n", status); 97 reg_write(smbus, REG_SMSTA, status); 98 return -ETIME; 99 } 100 101 /* Clear XEN */ 102 reg_write(smbus, REG_SMSTA, SMSTA_XEN); 103 104 return 0; 105 } 106 107 static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter, 108 struct i2c_msg *msg, int stop) 109 { 110 struct pasemi_smbus *smbus = adapter->algo_data; 111 int read, i, err; 112 u32 rd; 113 114 read = msg->flags & I2C_M_RD ? 1 : 0; 115 116 TXFIFO_WR(smbus, MTXFIFO_START | i2c_8bit_addr_from_msg(msg)); 117 118 if (read) { 119 TXFIFO_WR(smbus, msg->len | MTXFIFO_READ | 120 (stop ? MTXFIFO_STOP : 0)); 121 122 err = pasemi_smb_waitready(smbus); 123 if (err) 124 goto reset_out; 125 126 for (i = 0; i < msg->len; i++) { 127 rd = RXFIFO_RD(smbus); 128 if (rd & MRXFIFO_EMPTY) { 129 err = -ENODATA; 130 goto reset_out; 131 } 132 msg->buf[i] = rd & MRXFIFO_DATA_M; 133 } 134 } else { 135 for (i = 0; i < msg->len - 1; i++) 136 TXFIFO_WR(smbus, msg->buf[i]); 137 138 TXFIFO_WR(smbus, msg->buf[msg->len-1] | 139 (stop ? MTXFIFO_STOP : 0)); 140 } 141 142 return 0; 143 144 reset_out: 145 pasemi_reset(smbus); 146 return err; 147 } 148 149 static int pasemi_i2c_xfer(struct i2c_adapter *adapter, 150 struct i2c_msg *msgs, int num) 151 { 152 struct pasemi_smbus *smbus = adapter->algo_data; 153 int ret, i; 154 155 pasemi_smb_clear(smbus); 156 157 ret = 0; 158 159 for (i = 0; i < num && !ret; i++) 160 ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1))); 161 162 return ret ? ret : num; 163 } 164 165 static int pasemi_smb_xfer(struct i2c_adapter *adapter, 166 u16 addr, unsigned short flags, char read_write, u8 command, 167 int size, union i2c_smbus_data *data) 168 { 169 struct pasemi_smbus *smbus = adapter->algo_data; 170 unsigned int rd; 171 int read_flag, err; 172 int len = 0, i; 173 174 /* All our ops take 8-bit shifted addresses */ 175 addr <<= 1; 176 read_flag = read_write == I2C_SMBUS_READ; 177 178 pasemi_smb_clear(smbus); 179 180 switch (size) { 181 case I2C_SMBUS_QUICK: 182 TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START | 183 MTXFIFO_STOP); 184 break; 185 case I2C_SMBUS_BYTE: 186 TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START); 187 if (read_write) 188 TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ); 189 else 190 TXFIFO_WR(smbus, MTXFIFO_STOP | command); 191 break; 192 case I2C_SMBUS_BYTE_DATA: 193 TXFIFO_WR(smbus, addr | MTXFIFO_START); 194 TXFIFO_WR(smbus, command); 195 if (read_write) { 196 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START); 197 TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP); 198 } else { 199 TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte); 200 } 201 break; 202 case I2C_SMBUS_WORD_DATA: 203 TXFIFO_WR(smbus, addr | MTXFIFO_START); 204 TXFIFO_WR(smbus, command); 205 if (read_write) { 206 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START); 207 TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP); 208 } else { 209 TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M); 210 TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8)); 211 } 212 break; 213 case I2C_SMBUS_BLOCK_DATA: 214 TXFIFO_WR(smbus, addr | MTXFIFO_START); 215 TXFIFO_WR(smbus, command); 216 if (read_write) { 217 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START); 218 TXFIFO_WR(smbus, 1 | MTXFIFO_READ); 219 rd = RXFIFO_RD(smbus); 220 len = min_t(u8, (rd & MRXFIFO_DATA_M), 221 I2C_SMBUS_BLOCK_MAX); 222 TXFIFO_WR(smbus, len | MTXFIFO_READ | 223 MTXFIFO_STOP); 224 } else { 225 len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX); 226 TXFIFO_WR(smbus, len); 227 for (i = 1; i < len; i++) 228 TXFIFO_WR(smbus, data->block[i]); 229 TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP); 230 } 231 break; 232 case I2C_SMBUS_PROC_CALL: 233 read_write = I2C_SMBUS_READ; 234 TXFIFO_WR(smbus, addr | MTXFIFO_START); 235 TXFIFO_WR(smbus, command); 236 TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M); 237 TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M); 238 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START); 239 TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ); 240 break; 241 case I2C_SMBUS_BLOCK_PROC_CALL: 242 len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1); 243 read_write = I2C_SMBUS_READ; 244 TXFIFO_WR(smbus, addr | MTXFIFO_START); 245 TXFIFO_WR(smbus, command); 246 TXFIFO_WR(smbus, len); 247 for (i = 1; i <= len; i++) 248 TXFIFO_WR(smbus, data->block[i]); 249 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ); 250 TXFIFO_WR(smbus, MTXFIFO_READ | 1); 251 rd = RXFIFO_RD(smbus); 252 len = min_t(u8, (rd & MRXFIFO_DATA_M), 253 I2C_SMBUS_BLOCK_MAX - len); 254 TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP); 255 break; 256 257 default: 258 dev_warn(&adapter->dev, "Unsupported transaction %d\n", size); 259 return -EINVAL; 260 } 261 262 err = pasemi_smb_waitready(smbus); 263 if (err) 264 goto reset_out; 265 266 if (read_write == I2C_SMBUS_WRITE) 267 return 0; 268 269 switch (size) { 270 case I2C_SMBUS_BYTE: 271 case I2C_SMBUS_BYTE_DATA: 272 rd = RXFIFO_RD(smbus); 273 if (rd & MRXFIFO_EMPTY) { 274 err = -ENODATA; 275 goto reset_out; 276 } 277 data->byte = rd & MRXFIFO_DATA_M; 278 break; 279 case I2C_SMBUS_WORD_DATA: 280 case I2C_SMBUS_PROC_CALL: 281 rd = RXFIFO_RD(smbus); 282 if (rd & MRXFIFO_EMPTY) { 283 err = -ENODATA; 284 goto reset_out; 285 } 286 data->word = rd & MRXFIFO_DATA_M; 287 rd = RXFIFO_RD(smbus); 288 if (rd & MRXFIFO_EMPTY) { 289 err = -ENODATA; 290 goto reset_out; 291 } 292 data->word |= (rd & MRXFIFO_DATA_M) << 8; 293 break; 294 case I2C_SMBUS_BLOCK_DATA: 295 case I2C_SMBUS_BLOCK_PROC_CALL: 296 data->block[0] = len; 297 for (i = 1; i <= len; i ++) { 298 rd = RXFIFO_RD(smbus); 299 if (rd & MRXFIFO_EMPTY) { 300 err = -ENODATA; 301 goto reset_out; 302 } 303 data->block[i] = rd & MRXFIFO_DATA_M; 304 } 305 break; 306 } 307 308 return 0; 309 310 reset_out: 311 pasemi_reset(smbus); 312 return err; 313 } 314 315 static u32 pasemi_smb_func(struct i2c_adapter *adapter) 316 { 317 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 318 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 319 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | 320 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C; 321 } 322 323 static const struct i2c_algorithm smbus_algorithm = { 324 .master_xfer = pasemi_i2c_xfer, 325 .smbus_xfer = pasemi_smb_xfer, 326 .functionality = pasemi_smb_func, 327 }; 328 329 int pasemi_i2c_common_probe(struct pasemi_smbus *smbus) 330 { 331 int error; 332 333 smbus->adapter.owner = THIS_MODULE; 334 snprintf(smbus->adapter.name, sizeof(smbus->adapter.name), 335 "PA Semi SMBus adapter (%s)", dev_name(smbus->dev)); 336 smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 337 smbus->adapter.algo = &smbus_algorithm; 338 smbus->adapter.algo_data = smbus; 339 340 /* set up the sysfs linkage to our parent device */ 341 smbus->adapter.dev.parent = smbus->dev; 342 343 if (smbus->hw_rev != PASEMI_HW_REV_PCI) 344 smbus->hw_rev = reg_read(smbus, REG_REV); 345 346 pasemi_reset(smbus); 347 348 error = devm_i2c_add_adapter(smbus->dev, &smbus->adapter); 349 if (error) 350 return error; 351 352 return 0; 353 } 354