1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2006-2007 PA Semi, Inc
4  *
5  * SMBus host driver for PA Semi PWRficient
6  */
7 
8 #include <linux/module.h>
9 #include <linux/pci.h>
10 #include <linux/kernel.h>
11 #include <linux/stddef.h>
12 #include <linux/sched.h>
13 #include <linux/i2c.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 
18 #include "i2c-pasemi-core.h"
19 
20 /* Register offsets */
21 #define REG_MTXFIFO	0x00
22 #define REG_MRXFIFO	0x04
23 #define REG_SMSTA	0x14
24 #define REG_CTL		0x1c
25 #define REG_REV		0x28
26 
27 /* Register defs */
28 #define MTXFIFO_READ	0x00000400
29 #define MTXFIFO_STOP	0x00000200
30 #define MTXFIFO_START	0x00000100
31 #define MTXFIFO_DATA_M	0x000000ff
32 
33 #define MRXFIFO_EMPTY	0x00000100
34 #define MRXFIFO_DATA_M	0x000000ff
35 
36 #define SMSTA_XEN	0x08000000
37 #define SMSTA_MTN	0x00200000
38 
39 #define CTL_MRR		0x00000400
40 #define CTL_MTR		0x00000200
41 #define CTL_EN		0x00000800
42 #define CTL_CLK_M	0x000000ff
43 
44 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
45 {
46 	dev_dbg(smbus->dev, "smbus write reg %x val %08x\n", reg, val);
47 	iowrite32(val, smbus->ioaddr + reg);
48 }
49 
50 static inline int reg_read(struct pasemi_smbus *smbus, int reg)
51 {
52 	int ret;
53 	ret = ioread32(smbus->ioaddr + reg);
54 	dev_dbg(smbus->dev, "smbus read reg %x val %08x\n", reg, ret);
55 	return ret;
56 }
57 
58 #define TXFIFO_WR(smbus, reg)	reg_write((smbus), REG_MTXFIFO, (reg))
59 #define RXFIFO_RD(smbus)	reg_read((smbus), REG_MRXFIFO)
60 
61 static void pasemi_reset(struct pasemi_smbus *smbus)
62 {
63 	u32 val = (CTL_MTR | CTL_MRR | (smbus->clk_div & CTL_CLK_M));
64 
65 	if (smbus->hw_rev >= 6)
66 		val |= CTL_EN;
67 
68 	reg_write(smbus, REG_CTL, val);
69 }
70 
71 static void pasemi_smb_clear(struct pasemi_smbus *smbus)
72 {
73 	unsigned int status;
74 
75 	status = reg_read(smbus, REG_SMSTA);
76 	reg_write(smbus, REG_SMSTA, status);
77 }
78 
79 static int pasemi_smb_waitready(struct pasemi_smbus *smbus)
80 {
81 	int timeout = 10;
82 	unsigned int status;
83 
84 	status = reg_read(smbus, REG_SMSTA);
85 
86 	while (!(status & SMSTA_XEN) && timeout--) {
87 		msleep(1);
88 		status = reg_read(smbus, REG_SMSTA);
89 	}
90 
91 	/* Got NACK? */
92 	if (status & SMSTA_MTN)
93 		return -ENXIO;
94 
95 	if (timeout < 0) {
96 		dev_warn(smbus->dev, "Timeout, status 0x%08x\n", status);
97 		reg_write(smbus, REG_SMSTA, status);
98 		return -ETIME;
99 	}
100 
101 	/* Clear XEN */
102 	reg_write(smbus, REG_SMSTA, SMSTA_XEN);
103 
104 	return 0;
105 }
106 
107 static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
108 			       struct i2c_msg *msg, int stop)
109 {
110 	struct pasemi_smbus *smbus = adapter->algo_data;
111 	int read, i, err;
112 	u32 rd;
113 
114 	read = msg->flags & I2C_M_RD ? 1 : 0;
115 
116 	TXFIFO_WR(smbus, MTXFIFO_START | i2c_8bit_addr_from_msg(msg));
117 
118 	if (read) {
119 		TXFIFO_WR(smbus, msg->len | MTXFIFO_READ |
120 				 (stop ? MTXFIFO_STOP : 0));
121 
122 		err = pasemi_smb_waitready(smbus);
123 		if (err)
124 			goto reset_out;
125 
126 		for (i = 0; i < msg->len; i++) {
127 			rd = RXFIFO_RD(smbus);
128 			if (rd & MRXFIFO_EMPTY) {
129 				err = -ENODATA;
130 				goto reset_out;
131 			}
132 			msg->buf[i] = rd & MRXFIFO_DATA_M;
133 		}
134 	} else {
135 		for (i = 0; i < msg->len - 1; i++)
136 			TXFIFO_WR(smbus, msg->buf[i]);
137 
138 		TXFIFO_WR(smbus, msg->buf[msg->len-1] |
139 			  (stop ? MTXFIFO_STOP : 0));
140 
141 		if (stop) {
142 			err = pasemi_smb_waitready(smbus);
143 			if (err)
144 				goto reset_out;
145 		}
146 	}
147 
148 	return 0;
149 
150  reset_out:
151 	pasemi_reset(smbus);
152 	return err;
153 }
154 
155 static int pasemi_i2c_xfer(struct i2c_adapter *adapter,
156 			   struct i2c_msg *msgs, int num)
157 {
158 	struct pasemi_smbus *smbus = adapter->algo_data;
159 	int ret, i;
160 
161 	pasemi_smb_clear(smbus);
162 
163 	ret = 0;
164 
165 	for (i = 0; i < num && !ret; i++)
166 		ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
167 
168 	return ret ? ret : num;
169 }
170 
171 static int pasemi_smb_xfer(struct i2c_adapter *adapter,
172 		u16 addr, unsigned short flags, char read_write, u8 command,
173 		int size, union i2c_smbus_data *data)
174 {
175 	struct pasemi_smbus *smbus = adapter->algo_data;
176 	unsigned int rd;
177 	int read_flag, err;
178 	int len = 0, i;
179 
180 	/* All our ops take 8-bit shifted addresses */
181 	addr <<= 1;
182 	read_flag = read_write == I2C_SMBUS_READ;
183 
184 	pasemi_smb_clear(smbus);
185 
186 	switch (size) {
187 	case I2C_SMBUS_QUICK:
188 		TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START |
189 			  MTXFIFO_STOP);
190 		break;
191 	case I2C_SMBUS_BYTE:
192 		TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START);
193 		if (read_write)
194 			TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ);
195 		else
196 			TXFIFO_WR(smbus, MTXFIFO_STOP | command);
197 		break;
198 	case I2C_SMBUS_BYTE_DATA:
199 		TXFIFO_WR(smbus, addr | MTXFIFO_START);
200 		TXFIFO_WR(smbus, command);
201 		if (read_write) {
202 			TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
203 			TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP);
204 		} else {
205 			TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte);
206 		}
207 		break;
208 	case I2C_SMBUS_WORD_DATA:
209 		TXFIFO_WR(smbus, addr | MTXFIFO_START);
210 		TXFIFO_WR(smbus, command);
211 		if (read_write) {
212 			TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
213 			TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP);
214 		} else {
215 			TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
216 			TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8));
217 		}
218 		break;
219 	case I2C_SMBUS_BLOCK_DATA:
220 		TXFIFO_WR(smbus, addr | MTXFIFO_START);
221 		TXFIFO_WR(smbus, command);
222 		if (read_write) {
223 			TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
224 			TXFIFO_WR(smbus, 1 | MTXFIFO_READ);
225 			rd = RXFIFO_RD(smbus);
226 			len = min_t(u8, (rd & MRXFIFO_DATA_M),
227 				    I2C_SMBUS_BLOCK_MAX);
228 			TXFIFO_WR(smbus, len | MTXFIFO_READ |
229 					 MTXFIFO_STOP);
230 		} else {
231 			len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX);
232 			TXFIFO_WR(smbus, len);
233 			for (i = 1; i < len; i++)
234 				TXFIFO_WR(smbus, data->block[i]);
235 			TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP);
236 		}
237 		break;
238 	case I2C_SMBUS_PROC_CALL:
239 		read_write = I2C_SMBUS_READ;
240 		TXFIFO_WR(smbus, addr | MTXFIFO_START);
241 		TXFIFO_WR(smbus, command);
242 		TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
243 		TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M);
244 		TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
245 		TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ);
246 		break;
247 	case I2C_SMBUS_BLOCK_PROC_CALL:
248 		len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1);
249 		read_write = I2C_SMBUS_READ;
250 		TXFIFO_WR(smbus, addr | MTXFIFO_START);
251 		TXFIFO_WR(smbus, command);
252 		TXFIFO_WR(smbus, len);
253 		for (i = 1; i <= len; i++)
254 			TXFIFO_WR(smbus, data->block[i]);
255 		TXFIFO_WR(smbus, addr | I2C_SMBUS_READ);
256 		TXFIFO_WR(smbus, MTXFIFO_READ | 1);
257 		rd = RXFIFO_RD(smbus);
258 		len = min_t(u8, (rd & MRXFIFO_DATA_M),
259 			    I2C_SMBUS_BLOCK_MAX - len);
260 		TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP);
261 		break;
262 
263 	default:
264 		dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
265 		return -EINVAL;
266 	}
267 
268 	err = pasemi_smb_waitready(smbus);
269 	if (err)
270 		goto reset_out;
271 
272 	if (read_write == I2C_SMBUS_WRITE)
273 		return 0;
274 
275 	switch (size) {
276 	case I2C_SMBUS_BYTE:
277 	case I2C_SMBUS_BYTE_DATA:
278 		rd = RXFIFO_RD(smbus);
279 		if (rd & MRXFIFO_EMPTY) {
280 			err = -ENODATA;
281 			goto reset_out;
282 		}
283 		data->byte = rd & MRXFIFO_DATA_M;
284 		break;
285 	case I2C_SMBUS_WORD_DATA:
286 	case I2C_SMBUS_PROC_CALL:
287 		rd = RXFIFO_RD(smbus);
288 		if (rd & MRXFIFO_EMPTY) {
289 			err = -ENODATA;
290 			goto reset_out;
291 		}
292 		data->word = rd & MRXFIFO_DATA_M;
293 		rd = RXFIFO_RD(smbus);
294 		if (rd & MRXFIFO_EMPTY) {
295 			err = -ENODATA;
296 			goto reset_out;
297 		}
298 		data->word |= (rd & MRXFIFO_DATA_M) << 8;
299 		break;
300 	case I2C_SMBUS_BLOCK_DATA:
301 	case I2C_SMBUS_BLOCK_PROC_CALL:
302 		data->block[0] = len;
303 		for (i = 1; i <= len; i ++) {
304 			rd = RXFIFO_RD(smbus);
305 			if (rd & MRXFIFO_EMPTY) {
306 				err = -ENODATA;
307 				goto reset_out;
308 			}
309 			data->block[i] = rd & MRXFIFO_DATA_M;
310 		}
311 		break;
312 	}
313 
314 	return 0;
315 
316  reset_out:
317 	pasemi_reset(smbus);
318 	return err;
319 }
320 
321 static u32 pasemi_smb_func(struct i2c_adapter *adapter)
322 {
323 	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
324 	       I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
325 	       I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
326 	       I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
327 }
328 
329 static const struct i2c_algorithm smbus_algorithm = {
330 	.master_xfer	= pasemi_i2c_xfer,
331 	.smbus_xfer	= pasemi_smb_xfer,
332 	.functionality	= pasemi_smb_func,
333 };
334 
335 int pasemi_i2c_common_probe(struct pasemi_smbus *smbus)
336 {
337 	int error;
338 
339 	smbus->adapter.owner = THIS_MODULE;
340 	snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
341 		 "PA Semi SMBus adapter (%s)", dev_name(smbus->dev));
342 	smbus->adapter.algo = &smbus_algorithm;
343 	smbus->adapter.algo_data = smbus;
344 
345 	/* set up the sysfs linkage to our parent device */
346 	smbus->adapter.dev.parent = smbus->dev;
347 
348 	if (smbus->hw_rev != PASEMI_HW_REV_PCI)
349 		smbus->hw_rev = reg_read(smbus, REG_REV);
350 
351 	pasemi_reset(smbus);
352 
353 	error = devm_i2c_add_adapter(smbus->dev, &smbus->adapter);
354 	if (error)
355 		return error;
356 
357 	return 0;
358 }
359