1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Actions Semiconductor Owl SoC's I2C driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 20 /* I2C registers */ 21 #define OWL_I2C_REG_CTL 0x0000 22 #define OWL_I2C_REG_CLKDIV 0x0004 23 #define OWL_I2C_REG_STAT 0x0008 24 #define OWL_I2C_REG_ADDR 0x000C 25 #define OWL_I2C_REG_TXDAT 0x0010 26 #define OWL_I2C_REG_RXDAT 0x0014 27 #define OWL_I2C_REG_CMD 0x0018 28 #define OWL_I2C_REG_FIFOCTL 0x001C 29 #define OWL_I2C_REG_FIFOSTAT 0x0020 30 #define OWL_I2C_REG_DATCNT 0x0024 31 #define OWL_I2C_REG_RCNT 0x0028 32 33 /* I2Cx_CTL Bit Mask */ 34 #define OWL_I2C_CTL_RB BIT(1) 35 #define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) 36 #define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) 37 #define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) 38 #define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) 39 #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) 40 #define OWL_I2C_CTL_IRQE BIT(5) 41 #define OWL_I2C_CTL_EN BIT(7) 42 #define OWL_I2C_CTL_AE BIT(8) 43 #define OWL_I2C_CTL_SHSM BIT(10) 44 45 #define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) 46 47 /* I2Cx_STAT Bit Mask */ 48 #define OWL_I2C_STAT_RACK BIT(0) 49 #define OWL_I2C_STAT_BEB BIT(1) 50 #define OWL_I2C_STAT_IRQP BIT(2) 51 #define OWL_I2C_STAT_LAB BIT(3) 52 #define OWL_I2C_STAT_STPD BIT(4) 53 #define OWL_I2C_STAT_STAD BIT(5) 54 #define OWL_I2C_STAT_BBB BIT(6) 55 #define OWL_I2C_STAT_TCB BIT(7) 56 #define OWL_I2C_STAT_LBST BIT(8) 57 #define OWL_I2C_STAT_SAMB BIT(9) 58 #define OWL_I2C_STAT_SRGC BIT(10) 59 60 /* I2Cx_CMD Bit Mask */ 61 #define OWL_I2C_CMD_SBE BIT(0) 62 #define OWL_I2C_CMD_RBE BIT(4) 63 #define OWL_I2C_CMD_DE BIT(8) 64 #define OWL_I2C_CMD_NS BIT(9) 65 #define OWL_I2C_CMD_SE BIT(10) 66 #define OWL_I2C_CMD_MSS BIT(11) 67 #define OWL_I2C_CMD_WRS BIT(12) 68 #define OWL_I2C_CMD_SECL BIT(15) 69 70 #define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) 71 #define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) 72 73 /* I2Cx_FIFOCTL Bit Mask */ 74 #define OWL_I2C_FIFOCTL_NIB BIT(0) 75 #define OWL_I2C_FIFOCTL_RFR BIT(1) 76 #define OWL_I2C_FIFOCTL_TFR BIT(2) 77 78 /* I2Cc_FIFOSTAT Bit Mask */ 79 #define OWL_I2C_FIFOSTAT_RNB BIT(1) 80 #define OWL_I2C_FIFOSTAT_RFE BIT(2) 81 #define OWL_I2C_FIFOSTAT_TFF BIT(5) 82 #define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) 83 #define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) 84 85 /* I2C bus timeout */ 86 #define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000) 87 88 #define OWL_I2C_MAX_RETRIES 50 89 90 struct owl_i2c_dev { 91 struct i2c_adapter adap; 92 struct i2c_msg *msg; 93 struct completion msg_complete; 94 struct clk *clk; 95 spinlock_t lock; 96 void __iomem *base; 97 unsigned long clk_rate; 98 u32 bus_freq; 99 u32 msg_ptr; 100 int err; 101 }; 102 103 static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) 104 { 105 unsigned int regval; 106 107 regval = readl(reg); 108 109 if (state) 110 regval |= val; 111 else 112 regval &= ~val; 113 114 writel(regval, reg); 115 } 116 117 static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev) 118 { 119 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 120 OWL_I2C_CTL_EN, false); 121 mdelay(1); 122 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 123 OWL_I2C_CTL_EN, true); 124 125 /* Clear status registers */ 126 writel(0, i2c_dev->base + OWL_I2C_REG_STAT); 127 } 128 129 static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev) 130 { 131 unsigned int val, timeout = 0; 132 133 /* Reset FIFO */ 134 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 135 OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, 136 true); 137 138 /* Wait 50ms for FIFO reset complete */ 139 do { 140 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); 141 if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) 142 break; 143 usleep_range(500, 1000); 144 } while (timeout++ < OWL_I2C_MAX_RETRIES); 145 146 if (timeout > OWL_I2C_MAX_RETRIES) { 147 dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n"); 148 return -ETIMEDOUT; 149 } 150 151 return 0; 152 } 153 154 static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) 155 { 156 unsigned int val; 157 158 val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16); 159 160 /* Set clock divider factor */ 161 writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); 162 } 163 164 static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) 165 { 166 struct owl_i2c_dev *i2c_dev = _dev; 167 struct i2c_msg *msg = i2c_dev->msg; 168 unsigned long flags; 169 unsigned int stat, fifostat; 170 171 spin_lock_irqsave(&i2c_dev->lock, flags); 172 173 i2c_dev->err = 0; 174 175 /* Handle NACK from slave */ 176 fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); 177 if (fifostat & OWL_I2C_FIFOSTAT_RNB) { 178 i2c_dev->err = -ENXIO; 179 goto stop; 180 } 181 182 /* Handle bus error */ 183 stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); 184 if (stat & OWL_I2C_STAT_BEB) { 185 i2c_dev->err = -EIO; 186 goto stop; 187 } 188 189 /* Handle FIFO read */ 190 if (msg->flags & I2C_M_RD) { 191 while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 192 OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) { 193 msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + 194 OWL_I2C_REG_RXDAT); 195 } 196 } else { 197 /* Handle the remaining bytes which were not sent */ 198 while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 199 OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) { 200 writel(msg->buf[i2c_dev->msg_ptr++], 201 i2c_dev->base + OWL_I2C_REG_TXDAT); 202 } 203 } 204 205 stop: 206 /* Clear pending interrupts */ 207 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 208 OWL_I2C_STAT_IRQP, true); 209 210 complete_all(&i2c_dev->msg_complete); 211 spin_unlock_irqrestore(&i2c_dev->lock, flags); 212 213 return IRQ_HANDLED; 214 } 215 216 static u32 owl_i2c_func(struct i2c_adapter *adap) 217 { 218 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 219 } 220 221 static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) 222 { 223 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 224 unsigned long timeout; 225 226 /* Check for Bus busy */ 227 timeout = jiffies + OWL_I2C_TIMEOUT; 228 while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { 229 if (time_after(jiffies, timeout)) { 230 dev_err(&adap->dev, "Bus busy timeout\n"); 231 return -ETIMEDOUT; 232 } 233 } 234 235 return 0; 236 } 237 238 static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 239 int num) 240 { 241 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 242 struct i2c_msg *msg; 243 unsigned long time_left, flags; 244 unsigned int i2c_cmd, val; 245 unsigned int addr; 246 int ret, idx; 247 248 spin_lock_irqsave(&i2c_dev->lock, flags); 249 250 /* Reset I2C controller */ 251 owl_i2c_reset(i2c_dev); 252 253 /* Set bus frequency */ 254 owl_i2c_set_freq(i2c_dev); 255 256 /* 257 * Spinlock should be released before calling reset FIFO and 258 * bus busy check since those functions may sleep 259 */ 260 spin_unlock_irqrestore(&i2c_dev->lock, flags); 261 262 /* Reset FIFO */ 263 ret = owl_i2c_reset_fifo(i2c_dev); 264 if (ret) 265 goto unlocked_err_exit; 266 267 /* Check for bus busy */ 268 ret = owl_i2c_check_bus_busy(adap); 269 if (ret) 270 goto unlocked_err_exit; 271 272 spin_lock_irqsave(&i2c_dev->lock, flags); 273 274 /* Check for Arbitration lost */ 275 val = readl(i2c_dev->base + OWL_I2C_REG_STAT); 276 if (val & OWL_I2C_STAT_LAB) { 277 val &= ~OWL_I2C_STAT_LAB; 278 writel(val, i2c_dev->base + OWL_I2C_REG_STAT); 279 ret = -EAGAIN; 280 goto err_exit; 281 } 282 283 reinit_completion(&i2c_dev->msg_complete); 284 285 /* Enable I2C controller interrupt */ 286 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 287 OWL_I2C_CTL_IRQE, true); 288 289 /* 290 * Select: FIFO enable, Master mode, Stop enable, Data count enable, 291 * Send start bit 292 */ 293 i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE | 294 OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE; 295 296 /* Handle repeated start condition */ 297 if (num > 1) { 298 /* Set internal address length and enable repeated start */ 299 i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) | 300 OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE; 301 302 /* Write slave address */ 303 addr = i2c_8bit_addr_from_msg(&msgs[0]); 304 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); 305 306 /* Write internal register address */ 307 for (idx = 0; idx < msgs[0].len; idx++) 308 writel(msgs[0].buf[idx], 309 i2c_dev->base + OWL_I2C_REG_TXDAT); 310 311 msg = &msgs[1]; 312 } else { 313 /* Set address length */ 314 i2c_cmd |= OWL_I2C_CMD_AS(1); 315 msg = &msgs[0]; 316 } 317 318 i2c_dev->msg = msg; 319 i2c_dev->msg_ptr = 0; 320 321 /* Set data count for the message */ 322 writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); 323 324 addr = i2c_8bit_addr_from_msg(msg); 325 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); 326 327 if (!(msg->flags & I2C_M_RD)) { 328 /* Write data to FIFO */ 329 for (idx = 0; idx < msg->len; idx++) { 330 /* Check for FIFO full */ 331 if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 332 OWL_I2C_FIFOSTAT_TFF) 333 break; 334 335 writel(msg->buf[idx], 336 i2c_dev->base + OWL_I2C_REG_TXDAT); 337 } 338 339 i2c_dev->msg_ptr = idx; 340 } 341 342 /* Ignore the NACK if needed */ 343 if (msg->flags & I2C_M_IGNORE_NAK) 344 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 345 OWL_I2C_FIFOCTL_NIB, true); 346 else 347 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 348 OWL_I2C_FIFOCTL_NIB, false); 349 350 /* Start the transfer */ 351 writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); 352 353 spin_unlock_irqrestore(&i2c_dev->lock, flags); 354 355 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 356 adap->timeout); 357 358 spin_lock_irqsave(&i2c_dev->lock, flags); 359 if (time_left == 0) { 360 dev_err(&adap->dev, "Transaction timed out\n"); 361 /* Send stop condition and release the bus */ 362 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 363 OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, 364 true); 365 ret = -ETIMEDOUT; 366 goto err_exit; 367 } 368 369 ret = i2c_dev->err < 0 ? i2c_dev->err : num; 370 371 err_exit: 372 spin_unlock_irqrestore(&i2c_dev->lock, flags); 373 374 unlocked_err_exit: 375 /* Disable I2C controller */ 376 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 377 OWL_I2C_CTL_EN, false); 378 379 return ret; 380 } 381 382 static const struct i2c_algorithm owl_i2c_algorithm = { 383 .master_xfer = owl_i2c_master_xfer, 384 .functionality = owl_i2c_func, 385 }; 386 387 static const struct i2c_adapter_quirks owl_i2c_quirks = { 388 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, 389 .max_read_len = 240, 390 .max_write_len = 240, 391 .max_comb_1st_msg_len = 6, 392 .max_comb_2nd_msg_len = 240, 393 }; 394 395 static int owl_i2c_probe(struct platform_device *pdev) 396 { 397 struct device *dev = &pdev->dev; 398 struct owl_i2c_dev *i2c_dev; 399 struct resource *res; 400 int ret, irq; 401 402 i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); 403 if (!i2c_dev) 404 return -ENOMEM; 405 406 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 407 i2c_dev->base = devm_ioremap_resource(dev, res); 408 if (IS_ERR(i2c_dev->base)) 409 return PTR_ERR(i2c_dev->base); 410 411 irq = platform_get_irq(pdev, 0); 412 if (irq < 0) { 413 dev_err(dev, "failed to get IRQ number\n"); 414 return irq; 415 } 416 417 if (of_property_read_u32(dev->of_node, "clock-frequency", 418 &i2c_dev->bus_freq)) 419 i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ; 420 421 /* We support only frequencies of 100k and 400k for now */ 422 if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ && 423 i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) { 424 dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); 425 return -EINVAL; 426 } 427 428 i2c_dev->clk = devm_clk_get(dev, NULL); 429 if (IS_ERR(i2c_dev->clk)) { 430 dev_err(dev, "failed to get clock\n"); 431 return PTR_ERR(i2c_dev->clk); 432 } 433 434 ret = clk_prepare_enable(i2c_dev->clk); 435 if (ret) 436 return ret; 437 438 i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); 439 if (!i2c_dev->clk_rate) { 440 dev_err(dev, "input clock rate should not be zero\n"); 441 ret = -EINVAL; 442 goto disable_clk; 443 } 444 445 init_completion(&i2c_dev->msg_complete); 446 spin_lock_init(&i2c_dev->lock); 447 i2c_dev->adap.owner = THIS_MODULE; 448 i2c_dev->adap.algo = &owl_i2c_algorithm; 449 i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; 450 i2c_dev->adap.quirks = &owl_i2c_quirks; 451 i2c_dev->adap.dev.parent = dev; 452 i2c_dev->adap.dev.of_node = dev->of_node; 453 snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), 454 "%s", "OWL I2C adapter"); 455 i2c_set_adapdata(&i2c_dev->adap, i2c_dev); 456 457 platform_set_drvdata(pdev, i2c_dev); 458 459 ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, 460 i2c_dev); 461 if (ret) { 462 dev_err(dev, "failed to request irq %d\n", irq); 463 goto disable_clk; 464 } 465 466 return i2c_add_adapter(&i2c_dev->adap); 467 468 disable_clk: 469 clk_disable_unprepare(i2c_dev->clk); 470 471 return ret; 472 } 473 474 static const struct of_device_id owl_i2c_of_match[] = { 475 { .compatible = "actions,s700-i2c" }, 476 { .compatible = "actions,s900-i2c" }, 477 { /* sentinel */ } 478 }; 479 MODULE_DEVICE_TABLE(of, owl_i2c_of_match); 480 481 static struct platform_driver owl_i2c_driver = { 482 .probe = owl_i2c_probe, 483 .driver = { 484 .name = "owl-i2c", 485 .of_match_table = of_match_ptr(owl_i2c_of_match), 486 }, 487 }; 488 module_platform_driver(owl_i2c_driver); 489 490 MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>"); 491 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 492 MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver"); 493 MODULE_LICENSE("GPL"); 494