1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Actions Semiconductor Owl SoC's I2C driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 21 /* I2C registers */ 22 #define OWL_I2C_REG_CTL 0x0000 23 #define OWL_I2C_REG_CLKDIV 0x0004 24 #define OWL_I2C_REG_STAT 0x0008 25 #define OWL_I2C_REG_ADDR 0x000C 26 #define OWL_I2C_REG_TXDAT 0x0010 27 #define OWL_I2C_REG_RXDAT 0x0014 28 #define OWL_I2C_REG_CMD 0x0018 29 #define OWL_I2C_REG_FIFOCTL 0x001C 30 #define OWL_I2C_REG_FIFOSTAT 0x0020 31 #define OWL_I2C_REG_DATCNT 0x0024 32 #define OWL_I2C_REG_RCNT 0x0028 33 34 /* I2Cx_CTL Bit Mask */ 35 #define OWL_I2C_CTL_RB BIT(1) 36 #define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) 37 #define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) 38 #define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) 39 #define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) 40 #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) 41 #define OWL_I2C_CTL_IRQE BIT(5) 42 #define OWL_I2C_CTL_EN BIT(7) 43 #define OWL_I2C_CTL_AE BIT(8) 44 #define OWL_I2C_CTL_SHSM BIT(10) 45 46 #define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) 47 48 /* I2Cx_STAT Bit Mask */ 49 #define OWL_I2C_STAT_RACK BIT(0) 50 #define OWL_I2C_STAT_BEB BIT(1) 51 #define OWL_I2C_STAT_IRQP BIT(2) 52 #define OWL_I2C_STAT_LAB BIT(3) 53 #define OWL_I2C_STAT_STPD BIT(4) 54 #define OWL_I2C_STAT_STAD BIT(5) 55 #define OWL_I2C_STAT_BBB BIT(6) 56 #define OWL_I2C_STAT_TCB BIT(7) 57 #define OWL_I2C_STAT_LBST BIT(8) 58 #define OWL_I2C_STAT_SAMB BIT(9) 59 #define OWL_I2C_STAT_SRGC BIT(10) 60 61 /* I2Cx_CMD Bit Mask */ 62 #define OWL_I2C_CMD_SBE BIT(0) 63 #define OWL_I2C_CMD_RBE BIT(4) 64 #define OWL_I2C_CMD_DE BIT(8) 65 #define OWL_I2C_CMD_NS BIT(9) 66 #define OWL_I2C_CMD_SE BIT(10) 67 #define OWL_I2C_CMD_MSS BIT(11) 68 #define OWL_I2C_CMD_WRS BIT(12) 69 #define OWL_I2C_CMD_SECL BIT(15) 70 71 #define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) 72 #define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) 73 74 /* I2Cx_FIFOCTL Bit Mask */ 75 #define OWL_I2C_FIFOCTL_NIB BIT(0) 76 #define OWL_I2C_FIFOCTL_RFR BIT(1) 77 #define OWL_I2C_FIFOCTL_TFR BIT(2) 78 79 /* I2Cc_FIFOSTAT Bit Mask */ 80 #define OWL_I2C_FIFOSTAT_CECB BIT(0) 81 #define OWL_I2C_FIFOSTAT_RNB BIT(1) 82 #define OWL_I2C_FIFOSTAT_RFE BIT(2) 83 #define OWL_I2C_FIFOSTAT_TFF BIT(5) 84 #define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) 85 #define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) 86 87 /* I2C bus timeout */ 88 #define OWL_I2C_TIMEOUT_MS (4 * 1000) 89 #define OWL_I2C_TIMEOUT msecs_to_jiffies(OWL_I2C_TIMEOUT_MS) 90 91 #define OWL_I2C_MAX_RETRIES 50 92 93 struct owl_i2c_dev { 94 struct i2c_adapter adap; 95 struct i2c_msg *msg; 96 struct completion msg_complete; 97 struct clk *clk; 98 spinlock_t lock; 99 void __iomem *base; 100 unsigned long clk_rate; 101 u32 bus_freq; 102 u32 msg_ptr; 103 int err; 104 }; 105 106 static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) 107 { 108 unsigned int regval; 109 110 regval = readl(reg); 111 112 if (state) 113 regval |= val; 114 else 115 regval &= ~val; 116 117 writel(regval, reg); 118 } 119 120 static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev) 121 { 122 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 123 OWL_I2C_CTL_EN, false); 124 mdelay(1); 125 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 126 OWL_I2C_CTL_EN, true); 127 128 /* Clear status registers */ 129 writel(0, i2c_dev->base + OWL_I2C_REG_STAT); 130 } 131 132 static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev) 133 { 134 unsigned int val, timeout = 0; 135 136 /* Reset FIFO */ 137 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 138 OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, 139 true); 140 141 /* Wait 50ms for FIFO reset complete */ 142 do { 143 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); 144 if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) 145 break; 146 usleep_range(500, 1000); 147 } while (timeout++ < OWL_I2C_MAX_RETRIES); 148 149 if (timeout > OWL_I2C_MAX_RETRIES) { 150 dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n"); 151 return -ETIMEDOUT; 152 } 153 154 return 0; 155 } 156 157 static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) 158 { 159 unsigned int val; 160 161 val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16); 162 163 /* Set clock divider factor */ 164 writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); 165 } 166 167 static void owl_i2c_xfer_data(struct owl_i2c_dev *i2c_dev) 168 { 169 struct i2c_msg *msg = i2c_dev->msg; 170 unsigned int stat, fifostat; 171 172 i2c_dev->err = 0; 173 174 /* Handle NACK from slave */ 175 fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); 176 if (fifostat & OWL_I2C_FIFOSTAT_RNB) { 177 i2c_dev->err = -ENXIO; 178 /* Clear NACK error bit by writing "1" */ 179 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, 180 OWL_I2C_FIFOSTAT_RNB, true); 181 return; 182 } 183 184 /* Handle bus error */ 185 stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); 186 if (stat & OWL_I2C_STAT_BEB) { 187 i2c_dev->err = -EIO; 188 /* Clear BUS error bit by writing "1" */ 189 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 190 OWL_I2C_STAT_BEB, true); 191 return; 192 } 193 194 /* Handle FIFO read */ 195 if (msg->flags & I2C_M_RD) { 196 while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 197 OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) { 198 msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + 199 OWL_I2C_REG_RXDAT); 200 } 201 } else { 202 /* Handle the remaining bytes which were not sent */ 203 while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 204 OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) { 205 writel(msg->buf[i2c_dev->msg_ptr++], 206 i2c_dev->base + OWL_I2C_REG_TXDAT); 207 } 208 } 209 } 210 211 static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) 212 { 213 struct owl_i2c_dev *i2c_dev = _dev; 214 215 spin_lock(&i2c_dev->lock); 216 217 owl_i2c_xfer_data(i2c_dev); 218 219 /* Clear pending interrupts */ 220 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 221 OWL_I2C_STAT_IRQP, true); 222 223 complete_all(&i2c_dev->msg_complete); 224 spin_unlock(&i2c_dev->lock); 225 226 return IRQ_HANDLED; 227 } 228 229 static u32 owl_i2c_func(struct i2c_adapter *adap) 230 { 231 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 232 } 233 234 static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) 235 { 236 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 237 unsigned long timeout; 238 239 /* Check for Bus busy */ 240 timeout = jiffies + OWL_I2C_TIMEOUT; 241 while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { 242 if (time_after(jiffies, timeout)) { 243 dev_err(&adap->dev, "Bus busy timeout\n"); 244 return -ETIMEDOUT; 245 } 246 } 247 248 return 0; 249 } 250 251 static int owl_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg *msgs, 252 int num, bool atomic) 253 { 254 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 255 struct i2c_msg *msg; 256 unsigned long time_left, flags; 257 unsigned int i2c_cmd, val; 258 unsigned int addr; 259 int ret, idx; 260 261 spin_lock_irqsave(&i2c_dev->lock, flags); 262 263 /* Reset I2C controller */ 264 owl_i2c_reset(i2c_dev); 265 266 /* Set bus frequency */ 267 owl_i2c_set_freq(i2c_dev); 268 269 /* 270 * Spinlock should be released before calling reset FIFO and 271 * bus busy check since those functions may sleep 272 */ 273 spin_unlock_irqrestore(&i2c_dev->lock, flags); 274 275 /* Reset FIFO */ 276 ret = owl_i2c_reset_fifo(i2c_dev); 277 if (ret) 278 goto unlocked_err_exit; 279 280 /* Check for bus busy */ 281 ret = owl_i2c_check_bus_busy(adap); 282 if (ret) 283 goto unlocked_err_exit; 284 285 spin_lock_irqsave(&i2c_dev->lock, flags); 286 287 /* Check for Arbitration lost */ 288 val = readl(i2c_dev->base + OWL_I2C_REG_STAT); 289 if (val & OWL_I2C_STAT_LAB) { 290 val &= ~OWL_I2C_STAT_LAB; 291 writel(val, i2c_dev->base + OWL_I2C_REG_STAT); 292 ret = -EAGAIN; 293 goto err_exit; 294 } 295 296 if (!atomic) 297 reinit_completion(&i2c_dev->msg_complete); 298 299 /* Enable/disable I2C controller interrupt */ 300 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 301 OWL_I2C_CTL_IRQE, !atomic); 302 303 /* 304 * Select: FIFO enable, Master mode, Stop enable, Data count enable, 305 * Send start bit 306 */ 307 i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE | 308 OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE; 309 310 /* Handle repeated start condition */ 311 if (num > 1) { 312 /* Set internal address length and enable repeated start */ 313 i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) | 314 OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE; 315 316 /* Write slave address */ 317 addr = i2c_8bit_addr_from_msg(&msgs[0]); 318 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); 319 320 /* Write internal register address */ 321 for (idx = 0; idx < msgs[0].len; idx++) 322 writel(msgs[0].buf[idx], 323 i2c_dev->base + OWL_I2C_REG_TXDAT); 324 325 msg = &msgs[1]; 326 } else { 327 /* Set address length */ 328 i2c_cmd |= OWL_I2C_CMD_AS(1); 329 msg = &msgs[0]; 330 } 331 332 i2c_dev->msg = msg; 333 i2c_dev->msg_ptr = 0; 334 335 /* Set data count for the message */ 336 writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); 337 338 addr = i2c_8bit_addr_from_msg(msg); 339 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); 340 341 if (!(msg->flags & I2C_M_RD)) { 342 /* Write data to FIFO */ 343 for (idx = 0; idx < msg->len; idx++) { 344 /* Check for FIFO full */ 345 if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 346 OWL_I2C_FIFOSTAT_TFF) 347 break; 348 349 writel(msg->buf[idx], 350 i2c_dev->base + OWL_I2C_REG_TXDAT); 351 } 352 353 i2c_dev->msg_ptr = idx; 354 } 355 356 /* Ignore the NACK if needed */ 357 if (msg->flags & I2C_M_IGNORE_NAK) 358 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 359 OWL_I2C_FIFOCTL_NIB, true); 360 else 361 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 362 OWL_I2C_FIFOCTL_NIB, false); 363 364 /* Start the transfer */ 365 writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); 366 367 spin_unlock_irqrestore(&i2c_dev->lock, flags); 368 369 if (atomic) { 370 /* Wait for Command Execute Completed or NACK Error bits */ 371 ret = readl_poll_timeout_atomic(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, 372 val, val & (OWL_I2C_FIFOSTAT_CECB | 373 OWL_I2C_FIFOSTAT_RNB), 374 10, OWL_I2C_TIMEOUT_MS * 1000); 375 } else { 376 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 377 adap->timeout); 378 if (!time_left) 379 ret = -ETIMEDOUT; 380 } 381 382 spin_lock_irqsave(&i2c_dev->lock, flags); 383 384 if (ret) { 385 dev_err(&adap->dev, "Transaction timed out\n"); 386 /* Send stop condition and release the bus */ 387 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 388 OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, 389 true); 390 goto err_exit; 391 } 392 393 if (atomic) 394 owl_i2c_xfer_data(i2c_dev); 395 396 ret = i2c_dev->err < 0 ? i2c_dev->err : num; 397 398 err_exit: 399 spin_unlock_irqrestore(&i2c_dev->lock, flags); 400 401 unlocked_err_exit: 402 /* Disable I2C controller */ 403 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 404 OWL_I2C_CTL_EN, false); 405 406 return ret; 407 } 408 409 static int owl_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 410 int num) 411 { 412 return owl_i2c_xfer_common(adap, msgs, num, false); 413 } 414 415 static int owl_i2c_xfer_atomic(struct i2c_adapter *adap, 416 struct i2c_msg *msgs, int num) 417 { 418 return owl_i2c_xfer_common(adap, msgs, num, true); 419 } 420 421 static const struct i2c_algorithm owl_i2c_algorithm = { 422 .master_xfer = owl_i2c_xfer, 423 .master_xfer_atomic = owl_i2c_xfer_atomic, 424 .functionality = owl_i2c_func, 425 }; 426 427 static const struct i2c_adapter_quirks owl_i2c_quirks = { 428 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, 429 .max_read_len = 240, 430 .max_write_len = 240, 431 .max_comb_1st_msg_len = 6, 432 .max_comb_2nd_msg_len = 240, 433 }; 434 435 static int owl_i2c_probe(struct platform_device *pdev) 436 { 437 struct device *dev = &pdev->dev; 438 struct owl_i2c_dev *i2c_dev; 439 int ret, irq; 440 441 i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); 442 if (!i2c_dev) 443 return -ENOMEM; 444 445 i2c_dev->base = devm_platform_ioremap_resource(pdev, 0); 446 if (IS_ERR(i2c_dev->base)) 447 return PTR_ERR(i2c_dev->base); 448 449 irq = platform_get_irq(pdev, 0); 450 if (irq < 0) 451 return irq; 452 453 if (of_property_read_u32(dev->of_node, "clock-frequency", 454 &i2c_dev->bus_freq)) 455 i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ; 456 457 /* We support only frequencies of 100k and 400k for now */ 458 if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ && 459 i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) { 460 dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); 461 return -EINVAL; 462 } 463 464 i2c_dev->clk = devm_clk_get(dev, NULL); 465 if (IS_ERR(i2c_dev->clk)) { 466 dev_err(dev, "failed to get clock\n"); 467 return PTR_ERR(i2c_dev->clk); 468 } 469 470 ret = clk_prepare_enable(i2c_dev->clk); 471 if (ret) 472 return ret; 473 474 i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); 475 if (!i2c_dev->clk_rate) { 476 dev_err(dev, "input clock rate should not be zero\n"); 477 ret = -EINVAL; 478 goto disable_clk; 479 } 480 481 init_completion(&i2c_dev->msg_complete); 482 spin_lock_init(&i2c_dev->lock); 483 i2c_dev->adap.owner = THIS_MODULE; 484 i2c_dev->adap.algo = &owl_i2c_algorithm; 485 i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; 486 i2c_dev->adap.quirks = &owl_i2c_quirks; 487 i2c_dev->adap.dev.parent = dev; 488 i2c_dev->adap.dev.of_node = dev->of_node; 489 snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), 490 "%s", "OWL I2C adapter"); 491 i2c_set_adapdata(&i2c_dev->adap, i2c_dev); 492 493 platform_set_drvdata(pdev, i2c_dev); 494 495 ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, 496 i2c_dev); 497 if (ret) { 498 dev_err(dev, "failed to request irq %d\n", irq); 499 goto disable_clk; 500 } 501 502 return i2c_add_adapter(&i2c_dev->adap); 503 504 disable_clk: 505 clk_disable_unprepare(i2c_dev->clk); 506 507 return ret; 508 } 509 510 static const struct of_device_id owl_i2c_of_match[] = { 511 { .compatible = "actions,s500-i2c" }, 512 { .compatible = "actions,s700-i2c" }, 513 { .compatible = "actions,s900-i2c" }, 514 { /* sentinel */ } 515 }; 516 MODULE_DEVICE_TABLE(of, owl_i2c_of_match); 517 518 static struct platform_driver owl_i2c_driver = { 519 .probe = owl_i2c_probe, 520 .driver = { 521 .name = "owl-i2c", 522 .of_match_table = owl_i2c_of_match, 523 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 524 }, 525 }; 526 module_platform_driver(owl_i2c_driver); 527 528 MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>"); 529 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 530 MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver"); 531 MODULE_LICENSE("GPL"); 532