1 /* 2 * TI OMAP I2C master mode driver 3 * 4 * Copyright (C) 2003 MontaVista Software, Inc. 5 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2004 - 2007 Texas Instruments. 7 * 8 * Originally written by MontaVista Software, Inc. 9 * Additional contributions by: 10 * Tony Lindgren <tony@atomide.com> 11 * Imre Deak <imre.deak@nokia.com> 12 * Juha Yrjölä <juha.yrjola@solidboot.com> 13 * Syed Khasim <x0khasim@ti.com> 14 * Nishant Menon <nm@ti.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 */ 26 27 #include <linux/module.h> 28 #include <linux/delay.h> 29 #include <linux/i2c.h> 30 #include <linux/err.h> 31 #include <linux/interrupt.h> 32 #include <linux/completion.h> 33 #include <linux/platform_device.h> 34 #include <linux/clk.h> 35 #include <linux/io.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/slab.h> 39 #include <linux/platform_data/i2c-omap.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/pinctrl/consumer.h> 42 43 /* I2C controller revisions */ 44 #define OMAP_I2C_OMAP1_REV_2 0x20 45 46 /* I2C controller revisions present on specific hardware */ 47 #define OMAP_I2C_REV_ON_2430 0x00000036 48 #define OMAP_I2C_REV_ON_3430_3530 0x0000003C 49 #define OMAP_I2C_REV_ON_3630 0x00000040 50 #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 51 52 /* timeout waiting for the controller to respond */ 53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 54 55 /* timeout for pm runtime autosuspend */ 56 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ 57 58 /* timeout for making decision on bus free status */ 59 #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10)) 60 61 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 62 enum { 63 OMAP_I2C_REV_REG = 0, 64 OMAP_I2C_IE_REG, 65 OMAP_I2C_STAT_REG, 66 OMAP_I2C_IV_REG, 67 OMAP_I2C_WE_REG, 68 OMAP_I2C_SYSS_REG, 69 OMAP_I2C_BUF_REG, 70 OMAP_I2C_CNT_REG, 71 OMAP_I2C_DATA_REG, 72 OMAP_I2C_SYSC_REG, 73 OMAP_I2C_CON_REG, 74 OMAP_I2C_OA_REG, 75 OMAP_I2C_SA_REG, 76 OMAP_I2C_PSC_REG, 77 OMAP_I2C_SCLL_REG, 78 OMAP_I2C_SCLH_REG, 79 OMAP_I2C_SYSTEST_REG, 80 OMAP_I2C_BUFSTAT_REG, 81 /* only on OMAP4430 */ 82 OMAP_I2C_IP_V2_REVNB_LO, 83 OMAP_I2C_IP_V2_REVNB_HI, 84 OMAP_I2C_IP_V2_IRQSTATUS_RAW, 85 OMAP_I2C_IP_V2_IRQENABLE_SET, 86 OMAP_I2C_IP_V2_IRQENABLE_CLR, 87 }; 88 89 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 90 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ 91 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ 92 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ 93 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ 94 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ 95 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ 96 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ 97 98 /* I2C Status Register (OMAP_I2C_STAT): */ 99 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ 100 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ 101 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ 102 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 103 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 104 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ 105 #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */ 106 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 107 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 108 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ 109 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ 110 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ 111 112 /* I2C WE wakeup enable register */ 113 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ 114 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ 115 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ 116 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ 117 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ 118 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ 119 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ 120 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ 121 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ 122 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ 123 124 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ 125 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ 126 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ 127 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ 128 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) 129 130 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ 131 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ 132 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ 133 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ 134 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ 135 136 /* I2C Configuration Register (OMAP_I2C_CON): */ 137 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ 138 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ 139 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ 140 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ 141 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ 142 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ 143 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ 144 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ 145 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ 146 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ 147 148 /* I2C SCL time value when Master */ 149 #define OMAP_I2C_SCLL_HSSCLL 8 150 #define OMAP_I2C_SCLH_HSSCLH 8 151 152 /* I2C System Test Register (OMAP_I2C_SYSTEST): */ 153 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 154 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ 155 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 156 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 157 /* Functional mode */ 158 #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */ 159 #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */ 160 #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */ 161 #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */ 162 /* SDA/SCL IO mode */ 163 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ 164 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ 165 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ 166 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ 167 168 /* OCP_SYSSTATUS bit definitions */ 169 #define SYSS_RESETDONE_MASK (1 << 0) 170 171 /* OCP_SYSCONFIG bit definitions */ 172 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) 173 #define SYSC_SIDLEMODE_MASK (0x3 << 3) 174 #define SYSC_ENAWAKEUP_MASK (1 << 2) 175 #define SYSC_SOFTRESET_MASK (1 << 1) 176 #define SYSC_AUTOIDLE_MASK (1 << 0) 177 178 #define SYSC_IDLEMODE_SMART 0x2 179 #define SYSC_CLOCKACTIVITY_FCLK 0x2 180 181 /* Errata definitions */ 182 #define I2C_OMAP_ERRATA_I207 (1 << 0) 183 #define I2C_OMAP_ERRATA_I462 (1 << 1) 184 185 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF 186 187 struct omap_i2c_dev { 188 struct device *dev; 189 void __iomem *base; /* virtual */ 190 int irq; 191 int reg_shift; /* bit shift for I2C register addresses */ 192 struct completion cmd_complete; 193 struct resource *ioarea; 194 u32 latency; /* maximum mpu wkup latency */ 195 void (*set_mpu_wkup_lat)(struct device *dev, 196 long latency); 197 u32 speed; /* Speed of bus in kHz */ 198 u32 flags; 199 u16 scheme; 200 u16 cmd_err; 201 u8 *buf; 202 u8 *regs; 203 size_t buf_len; 204 struct i2c_adapter adapter; 205 u8 threshold; 206 u8 fifo_size; /* use as flag and value 207 * fifo_size==0 implies no fifo 208 * if set, should be trsh+1 209 */ 210 u32 rev; 211 unsigned b_hw:1; /* bad h/w fixes */ 212 unsigned bb_valid:1; /* true when BB-bit reflects 213 * the I2C bus state 214 */ 215 unsigned receiver:1; /* true when we're in receiver mode */ 216 u16 iestate; /* Saved interrupt register */ 217 u16 pscstate; 218 u16 scllstate; 219 u16 sclhstate; 220 u16 syscstate; 221 u16 westate; 222 u16 errata; 223 }; 224 225 static const u8 reg_map_ip_v1[] = { 226 [OMAP_I2C_REV_REG] = 0x00, 227 [OMAP_I2C_IE_REG] = 0x01, 228 [OMAP_I2C_STAT_REG] = 0x02, 229 [OMAP_I2C_IV_REG] = 0x03, 230 [OMAP_I2C_WE_REG] = 0x03, 231 [OMAP_I2C_SYSS_REG] = 0x04, 232 [OMAP_I2C_BUF_REG] = 0x05, 233 [OMAP_I2C_CNT_REG] = 0x06, 234 [OMAP_I2C_DATA_REG] = 0x07, 235 [OMAP_I2C_SYSC_REG] = 0x08, 236 [OMAP_I2C_CON_REG] = 0x09, 237 [OMAP_I2C_OA_REG] = 0x0a, 238 [OMAP_I2C_SA_REG] = 0x0b, 239 [OMAP_I2C_PSC_REG] = 0x0c, 240 [OMAP_I2C_SCLL_REG] = 0x0d, 241 [OMAP_I2C_SCLH_REG] = 0x0e, 242 [OMAP_I2C_SYSTEST_REG] = 0x0f, 243 [OMAP_I2C_BUFSTAT_REG] = 0x10, 244 }; 245 246 static const u8 reg_map_ip_v2[] = { 247 [OMAP_I2C_REV_REG] = 0x04, 248 [OMAP_I2C_IE_REG] = 0x2c, 249 [OMAP_I2C_STAT_REG] = 0x28, 250 [OMAP_I2C_IV_REG] = 0x34, 251 [OMAP_I2C_WE_REG] = 0x34, 252 [OMAP_I2C_SYSS_REG] = 0x90, 253 [OMAP_I2C_BUF_REG] = 0x94, 254 [OMAP_I2C_CNT_REG] = 0x98, 255 [OMAP_I2C_DATA_REG] = 0x9c, 256 [OMAP_I2C_SYSC_REG] = 0x10, 257 [OMAP_I2C_CON_REG] = 0xa4, 258 [OMAP_I2C_OA_REG] = 0xa8, 259 [OMAP_I2C_SA_REG] = 0xac, 260 [OMAP_I2C_PSC_REG] = 0xb0, 261 [OMAP_I2C_SCLL_REG] = 0xb4, 262 [OMAP_I2C_SCLH_REG] = 0xb8, 263 [OMAP_I2C_SYSTEST_REG] = 0xbC, 264 [OMAP_I2C_BUFSTAT_REG] = 0xc0, 265 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, 266 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, 267 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, 268 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, 269 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, 270 }; 271 272 static int omap_i2c_xfer_data(struct omap_i2c_dev *omap); 273 274 static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap, 275 int reg, u16 val) 276 { 277 writew_relaxed(val, omap->base + 278 (omap->regs[reg] << omap->reg_shift)); 279 } 280 281 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg) 282 { 283 return readw_relaxed(omap->base + 284 (omap->regs[reg] << omap->reg_shift)); 285 } 286 287 static void __omap_i2c_init(struct omap_i2c_dev *omap) 288 { 289 290 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); 291 292 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ 293 omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate); 294 295 /* SCL low and high time values */ 296 omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate); 297 omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate); 298 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) 299 omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate); 300 301 /* Take the I2C module out of reset: */ 302 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 303 304 /* 305 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the 306 * bus is busy. It will be changed to 1 on the next IP FCLK clock. 307 * udelay(1) will be enough to fix that. 308 */ 309 310 /* 311 * Don't write to this register if the IE state is 0 as it can 312 * cause deadlock. 313 */ 314 if (omap->iestate) 315 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate); 316 } 317 318 static int omap_i2c_reset(struct omap_i2c_dev *omap) 319 { 320 unsigned long timeout; 321 u16 sysc; 322 323 if (omap->rev >= OMAP_I2C_OMAP1_REV_2) { 324 sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG); 325 326 /* Disable I2C controller before soft reset */ 327 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 328 omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) & 329 ~(OMAP_I2C_CON_EN)); 330 331 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); 332 /* For some reason we need to set the EN bit before the 333 * reset done bit gets set. */ 334 timeout = jiffies + OMAP_I2C_TIMEOUT; 335 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 336 while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) & 337 SYSS_RESETDONE_MASK)) { 338 if (time_after(jiffies, timeout)) { 339 dev_warn(omap->dev, "timeout waiting " 340 "for controller reset\n"); 341 return -ETIMEDOUT; 342 } 343 msleep(1); 344 } 345 346 /* SYSC register is cleared by the reset; rewrite it */ 347 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc); 348 349 if (omap->rev > OMAP_I2C_REV_ON_3430_3530) { 350 /* Schedule I2C-bus monitoring on the next transfer */ 351 omap->bb_valid = 0; 352 } 353 } 354 355 return 0; 356 } 357 358 static int omap_i2c_init(struct omap_i2c_dev *omap) 359 { 360 u16 psc = 0, scll = 0, sclh = 0; 361 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; 362 unsigned long fclk_rate = 12000000; 363 unsigned long internal_clk = 0; 364 struct clk *fclk; 365 int error; 366 367 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) { 368 /* 369 * Enabling all wakup sources to stop I2C freezing on 370 * WFI instruction. 371 * REVISIT: Some wkup sources might not be needed. 372 */ 373 omap->westate = OMAP_I2C_WE_ALL; 374 } 375 376 if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { 377 /* 378 * The I2C functional clock is the armxor_ck, so there's 379 * no need to get "armxor_ck" separately. Now, if OMAP2420 380 * always returns 12MHz for the functional clock, we can 381 * do this bit unconditionally. 382 */ 383 fclk = clk_get(omap->dev, "fck"); 384 if (IS_ERR(fclk)) { 385 error = PTR_ERR(fclk); 386 dev_err(omap->dev, "could not get fck: %i\n", error); 387 388 return error; 389 } 390 391 fclk_rate = clk_get_rate(fclk); 392 clk_put(fclk); 393 394 /* TRM for 5912 says the I2C clock must be prescaled to be 395 * between 7 - 12 MHz. The XOR input clock is typically 396 * 12, 13 or 19.2 MHz. So we should have code that produces: 397 * 398 * XOR MHz Divider Prescaler 399 * 12 1 0 400 * 13 2 1 401 * 19.2 2 1 402 */ 403 if (fclk_rate > 12000000) 404 psc = fclk_rate / 12000000; 405 } 406 407 if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { 408 409 /* 410 * HSI2C controller internal clk rate should be 19.2 Mhz for 411 * HS and for all modes on 2430. On 34xx we can use lower rate 412 * to get longer filter period for better noise suppression. 413 * The filter is iclk (fclk for HS) period. 414 */ 415 if (omap->speed > 400 || 416 omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) 417 internal_clk = 19200; 418 else if (omap->speed > 100) 419 internal_clk = 9600; 420 else 421 internal_clk = 4000; 422 fclk = clk_get(omap->dev, "fck"); 423 if (IS_ERR(fclk)) { 424 error = PTR_ERR(fclk); 425 dev_err(omap->dev, "could not get fck: %i\n", error); 426 427 return error; 428 } 429 fclk_rate = clk_get_rate(fclk) / 1000; 430 clk_put(fclk); 431 432 /* Compute prescaler divisor */ 433 psc = fclk_rate / internal_clk; 434 psc = psc - 1; 435 436 /* If configured for High Speed */ 437 if (omap->speed > 400) { 438 unsigned long scl; 439 440 /* For first phase of HS mode */ 441 scl = internal_clk / 400; 442 fsscll = scl - (scl / 3) - 7; 443 fssclh = (scl / 3) - 5; 444 445 /* For second phase of HS mode */ 446 scl = fclk_rate / omap->speed; 447 hsscll = scl - (scl / 3) - 7; 448 hssclh = (scl / 3) - 5; 449 } else if (omap->speed > 100) { 450 unsigned long scl; 451 452 /* Fast mode */ 453 scl = internal_clk / omap->speed; 454 fsscll = scl - (scl / 3) - 7; 455 fssclh = (scl / 3) - 5; 456 } else { 457 /* Standard mode */ 458 fsscll = internal_clk / (omap->speed * 2) - 7; 459 fssclh = internal_clk / (omap->speed * 2) - 5; 460 } 461 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; 462 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; 463 } else { 464 /* Program desired operating rate */ 465 fclk_rate /= (psc + 1) * 1000; 466 if (psc > 2) 467 psc = 2; 468 scll = fclk_rate / (omap->speed * 2) - 7 + psc; 469 sclh = fclk_rate / (omap->speed * 2) - 7 + psc; 470 } 471 472 omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | 473 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | 474 OMAP_I2C_IE_AL) | ((omap->fifo_size) ? 475 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); 476 477 omap->pscstate = psc; 478 omap->scllstate = scll; 479 omap->sclhstate = sclh; 480 481 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) { 482 /* Not implemented */ 483 omap->bb_valid = 1; 484 } 485 486 __omap_i2c_init(omap); 487 488 return 0; 489 } 490 491 /* 492 * Try bus recovery, but only if SDA is actually low. 493 */ 494 static int omap_i2c_recover_bus(struct omap_i2c_dev *omap) 495 { 496 u16 systest; 497 498 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG); 499 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) && 500 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) 501 return 0; /* bus seems to already be fine */ 502 if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC)) 503 return -EBUSY; /* recovery would not fix SCL */ 504 return i2c_recover_bus(&omap->adapter); 505 } 506 507 /* 508 * Waiting on Bus Busy 509 */ 510 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap) 511 { 512 unsigned long timeout; 513 514 timeout = jiffies + OMAP_I2C_TIMEOUT; 515 while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { 516 if (time_after(jiffies, timeout)) 517 return omap_i2c_recover_bus(omap); 518 msleep(1); 519 } 520 521 return 0; 522 } 523 524 /* 525 * Wait while BB-bit doesn't reflect the I2C bus state 526 * 527 * In a multimaster environment, after IP software reset, BB-bit value doesn't 528 * correspond to the current bus state. It may happen what BB-bit will be 0, 529 * while the bus is busy due to another I2C master activity. 530 * Here are BB-bit values after reset: 531 * SDA SCL BB NOTES 532 * 0 0 0 1, 2 533 * 1 0 0 1, 2 534 * 0 1 1 535 * 1 1 0 3 536 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START) 537 * combinations on the bus, it set BB-bit to 1. 538 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus, 539 * it set BB-bit to 0 and BF to 1. 540 * BB and BF bits correctly tracks the bus state while IP is suspended 541 * BB bit became valid on the next FCLK clock after CON_EN bit set 542 * 543 * NOTES: 544 * 1. Any transfer started when BB=0 and bus is busy wouldn't be 545 * completed by IP and results in controller timeout. 546 * 2. Any transfer started when BB=0 and SCL=0 results in IP 547 * starting to drive SDA low. In that case IP corrupt data 548 * on the bus. 549 * 3. Any transfer started in the middle of another master's transfer 550 * results in unpredictable results and data corruption 551 */ 552 static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap) 553 { 554 unsigned long bus_free_timeout = 0; 555 unsigned long timeout; 556 int bus_free = 0; 557 u16 stat, systest; 558 559 if (omap->bb_valid) 560 return 0; 561 562 timeout = jiffies + OMAP_I2C_TIMEOUT; 563 while (1) { 564 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); 565 /* 566 * We will see BB or BF event in a case IP had detected any 567 * activity on the I2C bus. Now IP correctly tracks the bus 568 * state. BB-bit value is valid. 569 */ 570 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF)) 571 break; 572 573 /* 574 * Otherwise, we must look signals on the bus to make 575 * the right decision. 576 */ 577 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG); 578 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) && 579 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) { 580 if (!bus_free) { 581 bus_free_timeout = jiffies + 582 OMAP_I2C_BUS_FREE_TIMEOUT; 583 bus_free = 1; 584 } 585 586 /* 587 * SDA and SCL lines was high for 10 ms without bus 588 * activity detected. The bus is free. Consider 589 * BB-bit value is valid. 590 */ 591 if (time_after(jiffies, bus_free_timeout)) 592 break; 593 } else { 594 bus_free = 0; 595 } 596 597 if (time_after(jiffies, timeout)) { 598 /* 599 * SDA or SCL were low for the entire timeout without 600 * any activity detected. Most likely, a slave is 601 * locking up the bus with no master driving the clock. 602 */ 603 dev_warn(omap->dev, "timeout waiting for bus ready\n"); 604 return omap_i2c_recover_bus(omap); 605 } 606 607 msleep(1); 608 } 609 610 omap->bb_valid = 1; 611 return 0; 612 } 613 614 static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx) 615 { 616 u16 buf; 617 618 if (omap->flags & OMAP_I2C_FLAG_NO_FIFO) 619 return; 620 621 /* 622 * Set up notification threshold based on message size. We're doing 623 * this to try and avoid draining feature as much as possible. Whenever 624 * we have big messages to transfer (bigger than our total fifo size) 625 * then we might use draining feature to transfer the remaining bytes. 626 */ 627 628 omap->threshold = clamp(size, (u8) 1, omap->fifo_size); 629 630 buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG); 631 632 if (is_rx) { 633 /* Clear RX Threshold */ 634 buf &= ~(0x3f << 8); 635 buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; 636 } else { 637 /* Clear TX Threshold */ 638 buf &= ~0x3f; 639 buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; 640 } 641 642 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf); 643 644 if (omap->rev < OMAP_I2C_REV_ON_3630) 645 omap->b_hw = 1; /* Enable hardware fixes */ 646 647 /* calculate wakeup latency constraint for MPU */ 648 if (omap->set_mpu_wkup_lat != NULL) 649 omap->latency = (1000000 * omap->threshold) / 650 (1000 * omap->speed / 8); 651 } 652 653 static void omap_i2c_wait(struct omap_i2c_dev *omap) 654 { 655 u16 stat; 656 u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); 657 int count = 0; 658 659 do { 660 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); 661 count++; 662 } while (!(stat & mask) && count < 5); 663 } 664 665 /* 666 * Low level master read/write transaction. 667 */ 668 static int omap_i2c_xfer_msg(struct i2c_adapter *adap, 669 struct i2c_msg *msg, int stop, bool polling) 670 { 671 struct omap_i2c_dev *omap = i2c_get_adapdata(adap); 672 unsigned long timeout; 673 u16 w; 674 int ret; 675 676 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 677 msg->addr, msg->len, msg->flags, stop); 678 679 omap->receiver = !!(msg->flags & I2C_M_RD); 680 omap_i2c_resize_fifo(omap, msg->len, omap->receiver); 681 682 omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr); 683 684 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ 685 omap->buf = msg->buf; 686 omap->buf_len = msg->len; 687 688 /* make sure writes to omap->buf_len are ordered */ 689 barrier(); 690 691 omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len); 692 693 /* Clear the FIFO Buffers */ 694 w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG); 695 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; 696 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w); 697 698 if (!polling) 699 reinit_completion(&omap->cmd_complete); 700 omap->cmd_err = 0; 701 702 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; 703 704 /* High speed configuration */ 705 if (omap->speed > 400) 706 w |= OMAP_I2C_CON_OPMODE_HS; 707 708 if (msg->flags & I2C_M_STOP) 709 stop = 1; 710 if (msg->flags & I2C_M_TEN) 711 w |= OMAP_I2C_CON_XA; 712 if (!(msg->flags & I2C_M_RD)) 713 w |= OMAP_I2C_CON_TRX; 714 715 if (!omap->b_hw && stop) 716 w |= OMAP_I2C_CON_STP; 717 /* 718 * NOTE: STAT_BB bit could became 1 here if another master occupy 719 * the bus. IP successfully complete transfer when the bus will be 720 * free again (BB reset to 0). 721 */ 722 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); 723 724 /* 725 * Don't write stt and stp together on some hardware. 726 */ 727 if (omap->b_hw && stop) { 728 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; 729 u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); 730 while (con & OMAP_I2C_CON_STT) { 731 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); 732 733 /* Let the user know if i2c is in a bad state */ 734 if (time_after(jiffies, delay)) { 735 dev_err(omap->dev, "controller timed out " 736 "waiting for start condition to finish\n"); 737 return -ETIMEDOUT; 738 } 739 cpu_relax(); 740 } 741 742 w |= OMAP_I2C_CON_STP; 743 w &= ~OMAP_I2C_CON_STT; 744 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); 745 } 746 747 /* 748 * REVISIT: We should abort the transfer on signals, but the bus goes 749 * into arbitration and we're currently unable to recover from it. 750 */ 751 if (!polling) { 752 timeout = wait_for_completion_timeout(&omap->cmd_complete, 753 OMAP_I2C_TIMEOUT); 754 } else { 755 do { 756 omap_i2c_wait(omap); 757 ret = omap_i2c_xfer_data(omap); 758 } while (ret == -EAGAIN); 759 760 timeout = !ret; 761 } 762 763 if (timeout == 0) { 764 dev_err(omap->dev, "controller timed out\n"); 765 omap_i2c_reset(omap); 766 __omap_i2c_init(omap); 767 return -ETIMEDOUT; 768 } 769 770 if (likely(!omap->cmd_err)) 771 return 0; 772 773 /* We have an error */ 774 if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) { 775 omap_i2c_reset(omap); 776 __omap_i2c_init(omap); 777 return -EIO; 778 } 779 780 if (omap->cmd_err & OMAP_I2C_STAT_AL) 781 return -EAGAIN; 782 783 if (omap->cmd_err & OMAP_I2C_STAT_NACK) { 784 if (msg->flags & I2C_M_IGNORE_NAK) 785 return 0; 786 787 w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); 788 w |= OMAP_I2C_CON_STP; 789 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); 790 return -EREMOTEIO; 791 } 792 return -EIO; 793 } 794 795 796 /* 797 * Prepare controller for a transaction and call omap_i2c_xfer_msg 798 * to do the work during IRQ processing. 799 */ 800 static int 801 omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num, 802 bool polling) 803 { 804 struct omap_i2c_dev *omap = i2c_get_adapdata(adap); 805 int i; 806 int r; 807 808 r = pm_runtime_get_sync(omap->dev); 809 if (r < 0) 810 goto out; 811 812 r = omap_i2c_wait_for_bb_valid(omap); 813 if (r < 0) 814 goto out; 815 816 r = omap_i2c_wait_for_bb(omap); 817 if (r < 0) 818 goto out; 819 820 if (omap->set_mpu_wkup_lat != NULL) 821 omap->set_mpu_wkup_lat(omap->dev, omap->latency); 822 823 for (i = 0; i < num; i++) { 824 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)), 825 polling); 826 if (r != 0) 827 break; 828 } 829 830 if (r == 0) 831 r = num; 832 833 omap_i2c_wait_for_bb(omap); 834 835 if (omap->set_mpu_wkup_lat != NULL) 836 omap->set_mpu_wkup_lat(omap->dev, -1); 837 838 out: 839 pm_runtime_mark_last_busy(omap->dev); 840 pm_runtime_put_autosuspend(omap->dev); 841 return r; 842 } 843 844 static int 845 omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 846 { 847 return omap_i2c_xfer_common(adap, msgs, num, false); 848 } 849 850 static int 851 omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 852 { 853 return omap_i2c_xfer_common(adap, msgs, num, true); 854 } 855 856 static u32 857 omap_i2c_func(struct i2c_adapter *adap) 858 { 859 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 860 I2C_FUNC_PROTOCOL_MANGLING; 861 } 862 863 static inline void 864 omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err) 865 { 866 omap->cmd_err |= err; 867 complete(&omap->cmd_complete); 868 } 869 870 static inline void 871 omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat) 872 { 873 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat); 874 } 875 876 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat) 877 { 878 /* 879 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) 880 * Not applicable for OMAP4. 881 * Under certain rare conditions, RDR could be set again 882 * when the bus is busy, then ignore the interrupt and 883 * clear the interrupt. 884 */ 885 if (stat & OMAP_I2C_STAT_RDR) { 886 /* Step 1: If RDR is set, clear it */ 887 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); 888 889 /* Step 2: */ 890 if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) 891 & OMAP_I2C_STAT_BB)) { 892 893 /* Step 3: */ 894 if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) 895 & OMAP_I2C_STAT_RDR) { 896 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); 897 dev_dbg(omap->dev, "RDR when bus is busy.\n"); 898 } 899 900 } 901 } 902 } 903 904 /* rev1 devices are apparently only on some 15xx */ 905 #ifdef CONFIG_ARCH_OMAP15XX 906 907 static irqreturn_t 908 omap_i2c_omap1_isr(int this_irq, void *dev_id) 909 { 910 struct omap_i2c_dev *omap = dev_id; 911 u16 iv, w; 912 913 if (pm_runtime_suspended(omap->dev)) 914 return IRQ_NONE; 915 916 iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); 917 switch (iv) { 918 case 0x00: /* None */ 919 break; 920 case 0x01: /* Arbitration lost */ 921 dev_err(omap->dev, "Arbitration lost\n"); 922 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL); 923 break; 924 case 0x02: /* No acknowledgement */ 925 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK); 926 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); 927 break; 928 case 0x03: /* Register access ready */ 929 omap_i2c_complete_cmd(omap, 0); 930 break; 931 case 0x04: /* Receive data ready */ 932 if (omap->buf_len) { 933 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG); 934 *omap->buf++ = w; 935 omap->buf_len--; 936 if (omap->buf_len) { 937 *omap->buf++ = w >> 8; 938 omap->buf_len--; 939 } 940 } else 941 dev_err(omap->dev, "RRDY IRQ while no data requested\n"); 942 break; 943 case 0x05: /* Transmit data ready */ 944 if (omap->buf_len) { 945 w = *omap->buf++; 946 omap->buf_len--; 947 if (omap->buf_len) { 948 w |= *omap->buf++ << 8; 949 omap->buf_len--; 950 } 951 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w); 952 } else 953 dev_err(omap->dev, "XRDY IRQ while no data to send\n"); 954 break; 955 default: 956 return IRQ_NONE; 957 } 958 959 return IRQ_HANDLED; 960 } 961 #else 962 #define omap_i2c_omap1_isr NULL 963 #endif 964 965 /* 966 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing 967 * data to DATA_REG. Otherwise some data bytes can be lost while transferring 968 * them from the memory to the I2C interface. 969 */ 970 static int errata_omap3_i462(struct omap_i2c_dev *omap) 971 { 972 unsigned long timeout = 10000; 973 u16 stat; 974 975 do { 976 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); 977 if (stat & OMAP_I2C_STAT_XUDF) 978 break; 979 980 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { 981 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY | 982 OMAP_I2C_STAT_XDR)); 983 if (stat & OMAP_I2C_STAT_NACK) { 984 omap->cmd_err |= OMAP_I2C_STAT_NACK; 985 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK); 986 } 987 988 if (stat & OMAP_I2C_STAT_AL) { 989 dev_err(omap->dev, "Arbitration lost\n"); 990 omap->cmd_err |= OMAP_I2C_STAT_AL; 991 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL); 992 } 993 994 return -EIO; 995 } 996 997 cpu_relax(); 998 } while (--timeout); 999 1000 if (!timeout) { 1001 dev_err(omap->dev, "timeout waiting on XUDF bit\n"); 1002 return 0; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes, 1009 bool is_rdr) 1010 { 1011 u16 w; 1012 1013 while (num_bytes--) { 1014 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG); 1015 *omap->buf++ = w; 1016 omap->buf_len--; 1017 1018 /* 1019 * Data reg in 2430, omap3 and 1020 * omap4 is 8 bit wide 1021 */ 1022 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { 1023 *omap->buf++ = w >> 8; 1024 omap->buf_len--; 1025 } 1026 } 1027 } 1028 1029 static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes, 1030 bool is_xdr) 1031 { 1032 u16 w; 1033 1034 while (num_bytes--) { 1035 w = *omap->buf++; 1036 omap->buf_len--; 1037 1038 /* 1039 * Data reg in 2430, omap3 and 1040 * omap4 is 8 bit wide 1041 */ 1042 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { 1043 w |= *omap->buf++ << 8; 1044 omap->buf_len--; 1045 } 1046 1047 if (omap->errata & I2C_OMAP_ERRATA_I462) { 1048 int ret; 1049 1050 ret = errata_omap3_i462(omap); 1051 if (ret < 0) 1052 return ret; 1053 } 1054 1055 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w); 1056 } 1057 1058 return 0; 1059 } 1060 1061 static irqreturn_t 1062 omap_i2c_isr(int irq, void *dev_id) 1063 { 1064 struct omap_i2c_dev *omap = dev_id; 1065 irqreturn_t ret = IRQ_HANDLED; 1066 u16 mask; 1067 u16 stat; 1068 1069 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); 1070 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); 1071 1072 if (stat & mask) 1073 ret = IRQ_WAKE_THREAD; 1074 1075 return ret; 1076 } 1077 1078 static int omap_i2c_xfer_data(struct omap_i2c_dev *omap) 1079 { 1080 u16 bits; 1081 u16 stat; 1082 int err = 0, count = 0; 1083 1084 do { 1085 bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); 1086 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); 1087 stat &= bits; 1088 1089 /* If we're in receiver mode, ignore XDR/XRDY */ 1090 if (omap->receiver) 1091 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); 1092 else 1093 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); 1094 1095 if (!stat) { 1096 /* my work here is done */ 1097 err = -EAGAIN; 1098 break; 1099 } 1100 1101 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat); 1102 if (count++ == 100) { 1103 dev_warn(omap->dev, "Too much work in one IRQ\n"); 1104 break; 1105 } 1106 1107 if (stat & OMAP_I2C_STAT_NACK) { 1108 err |= OMAP_I2C_STAT_NACK; 1109 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK); 1110 } 1111 1112 if (stat & OMAP_I2C_STAT_AL) { 1113 dev_err(omap->dev, "Arbitration lost\n"); 1114 err |= OMAP_I2C_STAT_AL; 1115 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL); 1116 } 1117 1118 /* 1119 * ProDB0017052: Clear ARDY bit twice 1120 */ 1121 if (stat & OMAP_I2C_STAT_ARDY) 1122 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY); 1123 1124 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | 1125 OMAP_I2C_STAT_AL)) { 1126 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY | 1127 OMAP_I2C_STAT_RDR | 1128 OMAP_I2C_STAT_XRDY | 1129 OMAP_I2C_STAT_XDR | 1130 OMAP_I2C_STAT_ARDY)); 1131 break; 1132 } 1133 1134 if (stat & OMAP_I2C_STAT_RDR) { 1135 u8 num_bytes = 1; 1136 1137 if (omap->fifo_size) 1138 num_bytes = omap->buf_len; 1139 1140 if (omap->errata & I2C_OMAP_ERRATA_I207) { 1141 i2c_omap_errata_i207(omap, stat); 1142 num_bytes = (omap_i2c_read_reg(omap, 1143 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F; 1144 } 1145 1146 omap_i2c_receive_data(omap, num_bytes, true); 1147 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); 1148 continue; 1149 } 1150 1151 if (stat & OMAP_I2C_STAT_RRDY) { 1152 u8 num_bytes = 1; 1153 1154 if (omap->threshold) 1155 num_bytes = omap->threshold; 1156 1157 omap_i2c_receive_data(omap, num_bytes, false); 1158 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY); 1159 continue; 1160 } 1161 1162 if (stat & OMAP_I2C_STAT_XDR) { 1163 u8 num_bytes = 1; 1164 int ret; 1165 1166 if (omap->fifo_size) 1167 num_bytes = omap->buf_len; 1168 1169 ret = omap_i2c_transmit_data(omap, num_bytes, true); 1170 if (ret < 0) 1171 break; 1172 1173 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR); 1174 continue; 1175 } 1176 1177 if (stat & OMAP_I2C_STAT_XRDY) { 1178 u8 num_bytes = 1; 1179 int ret; 1180 1181 if (omap->threshold) 1182 num_bytes = omap->threshold; 1183 1184 ret = omap_i2c_transmit_data(omap, num_bytes, false); 1185 if (ret < 0) 1186 break; 1187 1188 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY); 1189 continue; 1190 } 1191 1192 if (stat & OMAP_I2C_STAT_ROVR) { 1193 dev_err(omap->dev, "Receive overrun\n"); 1194 err |= OMAP_I2C_STAT_ROVR; 1195 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR); 1196 break; 1197 } 1198 1199 if (stat & OMAP_I2C_STAT_XUDF) { 1200 dev_err(omap->dev, "Transmit underflow\n"); 1201 err |= OMAP_I2C_STAT_XUDF; 1202 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF); 1203 break; 1204 } 1205 } while (stat); 1206 1207 return err; 1208 } 1209 1210 static irqreturn_t 1211 omap_i2c_isr_thread(int this_irq, void *dev_id) 1212 { 1213 int ret; 1214 struct omap_i2c_dev *omap = dev_id; 1215 1216 ret = omap_i2c_xfer_data(omap); 1217 if (ret != -EAGAIN) 1218 omap_i2c_complete_cmd(omap, ret); 1219 1220 return IRQ_HANDLED; 1221 } 1222 1223 static const struct i2c_algorithm omap_i2c_algo = { 1224 .master_xfer = omap_i2c_xfer_irq, 1225 .master_xfer_atomic = omap_i2c_xfer_polling, 1226 .functionality = omap_i2c_func, 1227 }; 1228 1229 static const struct i2c_adapter_quirks omap_i2c_quirks = { 1230 .flags = I2C_AQ_NO_ZERO_LEN, 1231 }; 1232 1233 #ifdef CONFIG_OF 1234 static struct omap_i2c_bus_platform_data omap2420_pdata = { 1235 .rev = OMAP_I2C_IP_VERSION_1, 1236 .flags = OMAP_I2C_FLAG_NO_FIFO | 1237 OMAP_I2C_FLAG_SIMPLE_CLOCK | 1238 OMAP_I2C_FLAG_16BIT_DATA_REG | 1239 OMAP_I2C_FLAG_BUS_SHIFT_2, 1240 }; 1241 1242 static struct omap_i2c_bus_platform_data omap2430_pdata = { 1243 .rev = OMAP_I2C_IP_VERSION_1, 1244 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | 1245 OMAP_I2C_FLAG_FORCE_19200_INT_CLK, 1246 }; 1247 1248 static struct omap_i2c_bus_platform_data omap3_pdata = { 1249 .rev = OMAP_I2C_IP_VERSION_1, 1250 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 1251 }; 1252 1253 static struct omap_i2c_bus_platform_data omap4_pdata = { 1254 .rev = OMAP_I2C_IP_VERSION_2, 1255 }; 1256 1257 static const struct of_device_id omap_i2c_of_match[] = { 1258 { 1259 .compatible = "ti,omap4-i2c", 1260 .data = &omap4_pdata, 1261 }, 1262 { 1263 .compatible = "ti,omap3-i2c", 1264 .data = &omap3_pdata, 1265 }, 1266 { 1267 .compatible = "ti,omap2430-i2c", 1268 .data = &omap2430_pdata, 1269 }, 1270 { 1271 .compatible = "ti,omap2420-i2c", 1272 .data = &omap2420_pdata, 1273 }, 1274 { }, 1275 }; 1276 MODULE_DEVICE_TABLE(of, omap_i2c_of_match); 1277 #endif 1278 1279 #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14) 1280 1281 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4) 1282 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf) 1283 1284 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7) 1285 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f) 1286 #define OMAP_I2C_SCHEME_0 0 1287 #define OMAP_I2C_SCHEME_1 1 1288 1289 static int omap_i2c_get_scl(struct i2c_adapter *adap) 1290 { 1291 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 1292 u32 reg; 1293 1294 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); 1295 1296 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC; 1297 } 1298 1299 static int omap_i2c_get_sda(struct i2c_adapter *adap) 1300 { 1301 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 1302 u32 reg; 1303 1304 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); 1305 1306 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC; 1307 } 1308 1309 static void omap_i2c_set_scl(struct i2c_adapter *adap, int val) 1310 { 1311 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 1312 u32 reg; 1313 1314 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); 1315 if (val) 1316 reg |= OMAP_I2C_SYSTEST_SCL_O; 1317 else 1318 reg &= ~OMAP_I2C_SYSTEST_SCL_O; 1319 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); 1320 } 1321 1322 static void omap_i2c_prepare_recovery(struct i2c_adapter *adap) 1323 { 1324 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 1325 u32 reg; 1326 1327 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); 1328 /* enable test mode */ 1329 reg |= OMAP_I2C_SYSTEST_ST_EN; 1330 /* select SDA/SCL IO mode */ 1331 reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT; 1332 /* set SCL to high-impedance state (reset value is 0) */ 1333 reg |= OMAP_I2C_SYSTEST_SCL_O; 1334 /* set SDA to high-impedance state (reset value is 0) */ 1335 reg |= OMAP_I2C_SYSTEST_SDA_O; 1336 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); 1337 } 1338 1339 static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap) 1340 { 1341 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 1342 u32 reg; 1343 1344 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); 1345 /* restore reset values */ 1346 reg &= ~OMAP_I2C_SYSTEST_ST_EN; 1347 reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK; 1348 reg &= ~OMAP_I2C_SYSTEST_SCL_O; 1349 reg &= ~OMAP_I2C_SYSTEST_SDA_O; 1350 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); 1351 } 1352 1353 static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = { 1354 .get_scl = omap_i2c_get_scl, 1355 .get_sda = omap_i2c_get_sda, 1356 .set_scl = omap_i2c_set_scl, 1357 .prepare_recovery = omap_i2c_prepare_recovery, 1358 .unprepare_recovery = omap_i2c_unprepare_recovery, 1359 .recover_bus = i2c_generic_scl_recovery, 1360 }; 1361 1362 static int 1363 omap_i2c_probe(struct platform_device *pdev) 1364 { 1365 struct omap_i2c_dev *omap; 1366 struct i2c_adapter *adap; 1367 struct resource *mem; 1368 const struct omap_i2c_bus_platform_data *pdata = 1369 dev_get_platdata(&pdev->dev); 1370 struct device_node *node = pdev->dev.of_node; 1371 const struct of_device_id *match; 1372 int irq; 1373 int r; 1374 u32 rev; 1375 u16 minor, major; 1376 1377 irq = platform_get_irq(pdev, 0); 1378 if (irq < 0) { 1379 dev_err(&pdev->dev, "no irq resource?\n"); 1380 return irq; 1381 } 1382 1383 omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); 1384 if (!omap) 1385 return -ENOMEM; 1386 1387 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1388 omap->base = devm_ioremap_resource(&pdev->dev, mem); 1389 if (IS_ERR(omap->base)) 1390 return PTR_ERR(omap->base); 1391 1392 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); 1393 if (match) { 1394 u32 freq = 100000; /* default to 100000 Hz */ 1395 1396 pdata = match->data; 1397 omap->flags = pdata->flags; 1398 1399 of_property_read_u32(node, "clock-frequency", &freq); 1400 /* convert DT freq value in Hz into kHz for speed */ 1401 omap->speed = freq / 1000; 1402 } else if (pdata != NULL) { 1403 omap->speed = pdata->clkrate; 1404 omap->flags = pdata->flags; 1405 omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; 1406 } 1407 1408 omap->dev = &pdev->dev; 1409 omap->irq = irq; 1410 1411 platform_set_drvdata(pdev, omap); 1412 init_completion(&omap->cmd_complete); 1413 1414 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; 1415 1416 pm_runtime_enable(omap->dev); 1417 pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT); 1418 pm_runtime_use_autosuspend(omap->dev); 1419 1420 r = pm_runtime_get_sync(omap->dev); 1421 if (r < 0) 1422 goto err_free_mem; 1423 1424 /* 1425 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. 1426 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. 1427 * Also since the omap_i2c_read_reg uses reg_map_ip_* a 1428 * readw_relaxed is done. 1429 */ 1430 rev = readw_relaxed(omap->base + 0x04); 1431 1432 omap->scheme = OMAP_I2C_SCHEME(rev); 1433 switch (omap->scheme) { 1434 case OMAP_I2C_SCHEME_0: 1435 omap->regs = (u8 *)reg_map_ip_v1; 1436 omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG); 1437 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev); 1438 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev); 1439 break; 1440 case OMAP_I2C_SCHEME_1: 1441 /* FALLTHROUGH */ 1442 default: 1443 omap->regs = (u8 *)reg_map_ip_v2; 1444 rev = (rev << 16) | 1445 omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO); 1446 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev); 1447 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev); 1448 omap->rev = rev; 1449 } 1450 1451 omap->errata = 0; 1452 1453 if (omap->rev >= OMAP_I2C_REV_ON_2430 && 1454 omap->rev < OMAP_I2C_REV_ON_4430_PLUS) 1455 omap->errata |= I2C_OMAP_ERRATA_I207; 1456 1457 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) 1458 omap->errata |= I2C_OMAP_ERRATA_I462; 1459 1460 if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) { 1461 u16 s; 1462 1463 /* Set up the fifo size - Get total size */ 1464 s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; 1465 omap->fifo_size = 0x8 << s; 1466 1467 /* 1468 * Set up notification threshold as half the total available 1469 * size. This is to ensure that we can handle the status on int 1470 * call back latencies. 1471 */ 1472 1473 omap->fifo_size = (omap->fifo_size / 2); 1474 1475 if (omap->rev < OMAP_I2C_REV_ON_3630) 1476 omap->b_hw = 1; /* Enable hardware fixes */ 1477 1478 /* calculate wakeup latency constraint for MPU */ 1479 if (omap->set_mpu_wkup_lat != NULL) 1480 omap->latency = (1000000 * omap->fifo_size) / 1481 (1000 * omap->speed / 8); 1482 } 1483 1484 /* reset ASAP, clearing any IRQs */ 1485 omap_i2c_init(omap); 1486 1487 if (omap->rev < OMAP_I2C_OMAP1_REV_2) 1488 r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr, 1489 IRQF_NO_SUSPEND, pdev->name, omap); 1490 else 1491 r = devm_request_threaded_irq(&pdev->dev, omap->irq, 1492 omap_i2c_isr, omap_i2c_isr_thread, 1493 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1494 pdev->name, omap); 1495 1496 if (r) { 1497 dev_err(omap->dev, "failure requesting irq %i\n", omap->irq); 1498 goto err_unuse_clocks; 1499 } 1500 1501 adap = &omap->adapter; 1502 i2c_set_adapdata(adap, omap); 1503 adap->owner = THIS_MODULE; 1504 adap->class = I2C_CLASS_DEPRECATED; 1505 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); 1506 adap->algo = &omap_i2c_algo; 1507 adap->quirks = &omap_i2c_quirks; 1508 adap->dev.parent = &pdev->dev; 1509 adap->dev.of_node = pdev->dev.of_node; 1510 adap->bus_recovery_info = &omap_i2c_bus_recovery_info; 1511 1512 /* i2c device drivers may be active on return from add_adapter() */ 1513 adap->nr = pdev->id; 1514 r = i2c_add_numbered_adapter(adap); 1515 if (r) 1516 goto err_unuse_clocks; 1517 1518 dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr, 1519 major, minor, omap->speed); 1520 1521 pm_runtime_mark_last_busy(omap->dev); 1522 pm_runtime_put_autosuspend(omap->dev); 1523 1524 return 0; 1525 1526 err_unuse_clocks: 1527 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); 1528 pm_runtime_dont_use_autosuspend(omap->dev); 1529 pm_runtime_put_sync(omap->dev); 1530 pm_runtime_disable(&pdev->dev); 1531 err_free_mem: 1532 1533 return r; 1534 } 1535 1536 static int omap_i2c_remove(struct platform_device *pdev) 1537 { 1538 struct omap_i2c_dev *omap = platform_get_drvdata(pdev); 1539 int ret; 1540 1541 i2c_del_adapter(&omap->adapter); 1542 ret = pm_runtime_get_sync(&pdev->dev); 1543 if (ret < 0) 1544 return ret; 1545 1546 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); 1547 pm_runtime_dont_use_autosuspend(&pdev->dev); 1548 pm_runtime_put_sync(&pdev->dev); 1549 pm_runtime_disable(&pdev->dev); 1550 return 0; 1551 } 1552 1553 static int __maybe_unused omap_i2c_runtime_suspend(struct device *dev) 1554 { 1555 struct omap_i2c_dev *omap = dev_get_drvdata(dev); 1556 1557 omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); 1558 1559 if (omap->scheme == OMAP_I2C_SCHEME_0) 1560 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0); 1561 else 1562 omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1563 OMAP_I2C_IP_V2_INTERRUPTS_MASK); 1564 1565 if (omap->rev < OMAP_I2C_OMAP1_REV_2) { 1566 omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */ 1567 } else { 1568 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate); 1569 1570 /* Flush posted write */ 1571 omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); 1572 } 1573 1574 pinctrl_pm_select_sleep_state(dev); 1575 1576 return 0; 1577 } 1578 1579 static int __maybe_unused omap_i2c_runtime_resume(struct device *dev) 1580 { 1581 struct omap_i2c_dev *omap = dev_get_drvdata(dev); 1582 1583 pinctrl_pm_select_default_state(dev); 1584 1585 if (!omap->regs) 1586 return 0; 1587 1588 __omap_i2c_init(omap); 1589 1590 return 0; 1591 } 1592 1593 static const struct dev_pm_ops omap_i2c_pm_ops = { 1594 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1595 pm_runtime_force_resume) 1596 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, 1597 omap_i2c_runtime_resume, NULL) 1598 }; 1599 1600 static struct platform_driver omap_i2c_driver = { 1601 .probe = omap_i2c_probe, 1602 .remove = omap_i2c_remove, 1603 .driver = { 1604 .name = "omap_i2c", 1605 .pm = &omap_i2c_pm_ops, 1606 .of_match_table = of_match_ptr(omap_i2c_of_match), 1607 }, 1608 }; 1609 1610 /* I2C may be needed to bring up other drivers */ 1611 static int __init 1612 omap_i2c_init_driver(void) 1613 { 1614 return platform_driver_register(&omap_i2c_driver); 1615 } 1616 subsys_initcall(omap_i2c_init_driver); 1617 1618 static void __exit omap_i2c_exit_driver(void) 1619 { 1620 platform_driver_unregister(&omap_i2c_driver); 1621 } 1622 module_exit(omap_i2c_exit_driver); 1623 1624 MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); 1625 MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); 1626 MODULE_LICENSE("GPL"); 1627 MODULE_ALIAS("platform:omap_i2c"); 1628