1 /* 2 * TI OMAP I2C master mode driver 3 * 4 * Copyright (C) 2003 MontaVista Software, Inc. 5 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2004 - 2007 Texas Instruments. 7 * 8 * Originally written by MontaVista Software, Inc. 9 * Additional contributions by: 10 * Tony Lindgren <tony@atomide.com> 11 * Imre Deak <imre.deak@nokia.com> 12 * Juha Yrjölä <juha.yrjola@solidboot.com> 13 * Syed Khasim <x0khasim@ti.com> 14 * Nishant Menon <nm@ti.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 */ 26 27 #include <linux/module.h> 28 #include <linux/delay.h> 29 #include <linux/i2c.h> 30 #include <linux/err.h> 31 #include <linux/interrupt.h> 32 #include <linux/completion.h> 33 #include <linux/platform_device.h> 34 #include <linux/clk.h> 35 #include <linux/io.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/slab.h> 39 #include <linux/i2c-omap.h> 40 #include <linux/pm_runtime.h> 41 42 /* I2C controller revisions */ 43 #define OMAP_I2C_OMAP1_REV_2 0x20 44 45 /* I2C controller revisions present on specific hardware */ 46 #define OMAP_I2C_REV_ON_2430 0x00000036 47 #define OMAP_I2C_REV_ON_3430_3530 0x0000003C 48 #define OMAP_I2C_REV_ON_3630 0x00000040 49 #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 50 51 /* timeout waiting for the controller to respond */ 52 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 53 54 /* timeout for pm runtime autosuspend */ 55 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ 56 57 /* timeout for making decision on bus free status */ 58 #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10)) 59 60 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 61 enum { 62 OMAP_I2C_REV_REG = 0, 63 OMAP_I2C_IE_REG, 64 OMAP_I2C_STAT_REG, 65 OMAP_I2C_IV_REG, 66 OMAP_I2C_WE_REG, 67 OMAP_I2C_SYSS_REG, 68 OMAP_I2C_BUF_REG, 69 OMAP_I2C_CNT_REG, 70 OMAP_I2C_DATA_REG, 71 OMAP_I2C_SYSC_REG, 72 OMAP_I2C_CON_REG, 73 OMAP_I2C_OA_REG, 74 OMAP_I2C_SA_REG, 75 OMAP_I2C_PSC_REG, 76 OMAP_I2C_SCLL_REG, 77 OMAP_I2C_SCLH_REG, 78 OMAP_I2C_SYSTEST_REG, 79 OMAP_I2C_BUFSTAT_REG, 80 /* only on OMAP4430 */ 81 OMAP_I2C_IP_V2_REVNB_LO, 82 OMAP_I2C_IP_V2_REVNB_HI, 83 OMAP_I2C_IP_V2_IRQSTATUS_RAW, 84 OMAP_I2C_IP_V2_IRQENABLE_SET, 85 OMAP_I2C_IP_V2_IRQENABLE_CLR, 86 }; 87 88 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 89 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ 90 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ 91 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ 92 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ 93 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ 94 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ 95 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ 96 97 /* I2C Status Register (OMAP_I2C_STAT): */ 98 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ 99 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ 100 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ 101 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 102 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 103 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ 104 #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */ 105 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 106 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 107 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ 108 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ 109 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ 110 111 /* I2C WE wakeup enable register */ 112 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ 113 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ 114 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ 115 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ 116 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ 117 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ 118 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ 119 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ 120 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ 121 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ 122 123 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ 124 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ 125 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ 126 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ 127 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) 128 129 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ 130 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ 131 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ 132 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ 133 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ 134 135 /* I2C Configuration Register (OMAP_I2C_CON): */ 136 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ 137 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ 138 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ 139 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ 140 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ 141 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ 142 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ 143 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ 144 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ 145 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ 146 147 /* I2C SCL time value when Master */ 148 #define OMAP_I2C_SCLL_HSSCLL 8 149 #define OMAP_I2C_SCLH_HSSCLH 8 150 151 /* I2C System Test Register (OMAP_I2C_SYSTEST): */ 152 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 153 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ 154 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 155 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 156 /* Functional mode */ 157 #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */ 158 #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */ 159 #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */ 160 #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */ 161 /* SDA/SCL IO mode */ 162 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ 163 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ 164 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ 165 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ 166 167 /* OCP_SYSSTATUS bit definitions */ 168 #define SYSS_RESETDONE_MASK (1 << 0) 169 170 /* OCP_SYSCONFIG bit definitions */ 171 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) 172 #define SYSC_SIDLEMODE_MASK (0x3 << 3) 173 #define SYSC_ENAWAKEUP_MASK (1 << 2) 174 #define SYSC_SOFTRESET_MASK (1 << 1) 175 #define SYSC_AUTOIDLE_MASK (1 << 0) 176 177 #define SYSC_IDLEMODE_SMART 0x2 178 #define SYSC_CLOCKACTIVITY_FCLK 0x2 179 180 /* Errata definitions */ 181 #define I2C_OMAP_ERRATA_I207 (1 << 0) 182 #define I2C_OMAP_ERRATA_I462 (1 << 1) 183 184 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF 185 186 struct omap_i2c_dev { 187 spinlock_t lock; /* IRQ synchronization */ 188 struct device *dev; 189 void __iomem *base; /* virtual */ 190 int irq; 191 int reg_shift; /* bit shift for I2C register addresses */ 192 struct completion cmd_complete; 193 struct resource *ioarea; 194 u32 latency; /* maximum mpu wkup latency */ 195 void (*set_mpu_wkup_lat)(struct device *dev, 196 long latency); 197 u32 speed; /* Speed of bus in kHz */ 198 u32 flags; 199 u16 scheme; 200 u16 cmd_err; 201 u8 *buf; 202 u8 *regs; 203 size_t buf_len; 204 struct i2c_adapter adapter; 205 u8 threshold; 206 u8 fifo_size; /* use as flag and value 207 * fifo_size==0 implies no fifo 208 * if set, should be trsh+1 209 */ 210 u32 rev; 211 unsigned b_hw:1; /* bad h/w fixes */ 212 unsigned bb_valid:1; /* true when BB-bit reflects 213 * the I2C bus state 214 */ 215 unsigned receiver:1; /* true when we're in receiver mode */ 216 u16 iestate; /* Saved interrupt register */ 217 u16 pscstate; 218 u16 scllstate; 219 u16 sclhstate; 220 u16 syscstate; 221 u16 westate; 222 u16 errata; 223 }; 224 225 static const u8 reg_map_ip_v1[] = { 226 [OMAP_I2C_REV_REG] = 0x00, 227 [OMAP_I2C_IE_REG] = 0x01, 228 [OMAP_I2C_STAT_REG] = 0x02, 229 [OMAP_I2C_IV_REG] = 0x03, 230 [OMAP_I2C_WE_REG] = 0x03, 231 [OMAP_I2C_SYSS_REG] = 0x04, 232 [OMAP_I2C_BUF_REG] = 0x05, 233 [OMAP_I2C_CNT_REG] = 0x06, 234 [OMAP_I2C_DATA_REG] = 0x07, 235 [OMAP_I2C_SYSC_REG] = 0x08, 236 [OMAP_I2C_CON_REG] = 0x09, 237 [OMAP_I2C_OA_REG] = 0x0a, 238 [OMAP_I2C_SA_REG] = 0x0b, 239 [OMAP_I2C_PSC_REG] = 0x0c, 240 [OMAP_I2C_SCLL_REG] = 0x0d, 241 [OMAP_I2C_SCLH_REG] = 0x0e, 242 [OMAP_I2C_SYSTEST_REG] = 0x0f, 243 [OMAP_I2C_BUFSTAT_REG] = 0x10, 244 }; 245 246 static const u8 reg_map_ip_v2[] = { 247 [OMAP_I2C_REV_REG] = 0x04, 248 [OMAP_I2C_IE_REG] = 0x2c, 249 [OMAP_I2C_STAT_REG] = 0x28, 250 [OMAP_I2C_IV_REG] = 0x34, 251 [OMAP_I2C_WE_REG] = 0x34, 252 [OMAP_I2C_SYSS_REG] = 0x90, 253 [OMAP_I2C_BUF_REG] = 0x94, 254 [OMAP_I2C_CNT_REG] = 0x98, 255 [OMAP_I2C_DATA_REG] = 0x9c, 256 [OMAP_I2C_SYSC_REG] = 0x10, 257 [OMAP_I2C_CON_REG] = 0xa4, 258 [OMAP_I2C_OA_REG] = 0xa8, 259 [OMAP_I2C_SA_REG] = 0xac, 260 [OMAP_I2C_PSC_REG] = 0xb0, 261 [OMAP_I2C_SCLL_REG] = 0xb4, 262 [OMAP_I2C_SCLH_REG] = 0xb8, 263 [OMAP_I2C_SYSTEST_REG] = 0xbC, 264 [OMAP_I2C_BUFSTAT_REG] = 0xc0, 265 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, 266 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, 267 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, 268 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, 269 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, 270 }; 271 272 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 273 int reg, u16 val) 274 { 275 writew_relaxed(val, i2c_dev->base + 276 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 277 } 278 279 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) 280 { 281 return readw_relaxed(i2c_dev->base + 282 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 283 } 284 285 static void __omap_i2c_init(struct omap_i2c_dev *dev) 286 { 287 288 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 289 290 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ 291 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); 292 293 /* SCL low and high time values */ 294 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); 295 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate); 296 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) 297 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); 298 299 /* Take the I2C module out of reset: */ 300 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 301 302 /* 303 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the 304 * bus is busy. It will be changed to 1 on the next IP FCLK clock. 305 * udelay(1) will be enough to fix that. 306 */ 307 308 /* 309 * Don't write to this register if the IE state is 0 as it can 310 * cause deadlock. 311 */ 312 if (dev->iestate) 313 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); 314 } 315 316 static int omap_i2c_reset(struct omap_i2c_dev *dev) 317 { 318 unsigned long timeout; 319 u16 sysc; 320 321 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { 322 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG); 323 324 /* Disable I2C controller before soft reset */ 325 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 326 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & 327 ~(OMAP_I2C_CON_EN)); 328 329 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); 330 /* For some reason we need to set the EN bit before the 331 * reset done bit gets set. */ 332 timeout = jiffies + OMAP_I2C_TIMEOUT; 333 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 334 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & 335 SYSS_RESETDONE_MASK)) { 336 if (time_after(jiffies, timeout)) { 337 dev_warn(dev->dev, "timeout waiting " 338 "for controller reset\n"); 339 return -ETIMEDOUT; 340 } 341 msleep(1); 342 } 343 344 /* SYSC register is cleared by the reset; rewrite it */ 345 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc); 346 347 if (dev->rev > OMAP_I2C_REV_ON_3430_3530) { 348 /* Schedule I2C-bus monitoring on the next transfer */ 349 dev->bb_valid = 0; 350 } 351 } 352 353 return 0; 354 } 355 356 static int omap_i2c_init(struct omap_i2c_dev *dev) 357 { 358 u16 psc = 0, scll = 0, sclh = 0; 359 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; 360 unsigned long fclk_rate = 12000000; 361 unsigned long internal_clk = 0; 362 struct clk *fclk; 363 364 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { 365 /* 366 * Enabling all wakup sources to stop I2C freezing on 367 * WFI instruction. 368 * REVISIT: Some wkup sources might not be needed. 369 */ 370 dev->westate = OMAP_I2C_WE_ALL; 371 } 372 373 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { 374 /* 375 * The I2C functional clock is the armxor_ck, so there's 376 * no need to get "armxor_ck" separately. Now, if OMAP2420 377 * always returns 12MHz for the functional clock, we can 378 * do this bit unconditionally. 379 */ 380 fclk = clk_get(dev->dev, "fck"); 381 fclk_rate = clk_get_rate(fclk); 382 clk_put(fclk); 383 384 /* TRM for 5912 says the I2C clock must be prescaled to be 385 * between 7 - 12 MHz. The XOR input clock is typically 386 * 12, 13 or 19.2 MHz. So we should have code that produces: 387 * 388 * XOR MHz Divider Prescaler 389 * 12 1 0 390 * 13 2 1 391 * 19.2 2 1 392 */ 393 if (fclk_rate > 12000000) 394 psc = fclk_rate / 12000000; 395 } 396 397 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { 398 399 /* 400 * HSI2C controller internal clk rate should be 19.2 Mhz for 401 * HS and for all modes on 2430. On 34xx we can use lower rate 402 * to get longer filter period for better noise suppression. 403 * The filter is iclk (fclk for HS) period. 404 */ 405 if (dev->speed > 400 || 406 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) 407 internal_clk = 19200; 408 else if (dev->speed > 100) 409 internal_clk = 9600; 410 else 411 internal_clk = 4000; 412 fclk = clk_get(dev->dev, "fck"); 413 fclk_rate = clk_get_rate(fclk) / 1000; 414 clk_put(fclk); 415 416 /* Compute prescaler divisor */ 417 psc = fclk_rate / internal_clk; 418 psc = psc - 1; 419 420 /* If configured for High Speed */ 421 if (dev->speed > 400) { 422 unsigned long scl; 423 424 /* For first phase of HS mode */ 425 scl = internal_clk / 400; 426 fsscll = scl - (scl / 3) - 7; 427 fssclh = (scl / 3) - 5; 428 429 /* For second phase of HS mode */ 430 scl = fclk_rate / dev->speed; 431 hsscll = scl - (scl / 3) - 7; 432 hssclh = (scl / 3) - 5; 433 } else if (dev->speed > 100) { 434 unsigned long scl; 435 436 /* Fast mode */ 437 scl = internal_clk / dev->speed; 438 fsscll = scl - (scl / 3) - 7; 439 fssclh = (scl / 3) - 5; 440 } else { 441 /* Standard mode */ 442 fsscll = internal_clk / (dev->speed * 2) - 7; 443 fssclh = internal_clk / (dev->speed * 2) - 5; 444 } 445 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; 446 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; 447 } else { 448 /* Program desired operating rate */ 449 fclk_rate /= (psc + 1) * 1000; 450 if (psc > 2) 451 psc = 2; 452 scll = fclk_rate / (dev->speed * 2) - 7 + psc; 453 sclh = fclk_rate / (dev->speed * 2) - 7 + psc; 454 } 455 456 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | 457 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | 458 OMAP_I2C_IE_AL) | ((dev->fifo_size) ? 459 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); 460 461 dev->pscstate = psc; 462 dev->scllstate = scll; 463 dev->sclhstate = sclh; 464 465 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) { 466 /* Not implemented */ 467 dev->bb_valid = 1; 468 } 469 470 __omap_i2c_init(dev); 471 472 return 0; 473 } 474 475 /* 476 * Waiting on Bus Busy 477 */ 478 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) 479 { 480 unsigned long timeout; 481 482 timeout = jiffies + OMAP_I2C_TIMEOUT; 483 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { 484 if (time_after(jiffies, timeout)) { 485 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 486 return -ETIMEDOUT; 487 } 488 msleep(1); 489 } 490 491 return 0; 492 } 493 494 /* 495 * Wait while BB-bit doesn't reflect the I2C bus state 496 * 497 * In a multimaster environment, after IP software reset, BB-bit value doesn't 498 * correspond to the current bus state. It may happen what BB-bit will be 0, 499 * while the bus is busy due to another I2C master activity. 500 * Here are BB-bit values after reset: 501 * SDA SCL BB NOTES 502 * 0 0 0 1, 2 503 * 1 0 0 1, 2 504 * 0 1 1 505 * 1 1 0 3 506 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START) 507 * combinations on the bus, it set BB-bit to 1. 508 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus, 509 * it set BB-bit to 0 and BF to 1. 510 * BB and BF bits correctly tracks the bus state while IP is suspended 511 * BB bit became valid on the next FCLK clock after CON_EN bit set 512 * 513 * NOTES: 514 * 1. Any transfer started when BB=0 and bus is busy wouldn't be 515 * completed by IP and results in controller timeout. 516 * 2. Any transfer started when BB=0 and SCL=0 results in IP 517 * starting to drive SDA low. In that case IP corrupt data 518 * on the bus. 519 * 3. Any transfer started in the middle of another master's transfer 520 * results in unpredictable results and data corruption 521 */ 522 static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev) 523 { 524 unsigned long bus_free_timeout = 0; 525 unsigned long timeout; 526 int bus_free = 0; 527 u16 stat, systest; 528 529 if (dev->bb_valid) 530 return 0; 531 532 timeout = jiffies + OMAP_I2C_TIMEOUT; 533 while (1) { 534 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 535 /* 536 * We will see BB or BF event in a case IP had detected any 537 * activity on the I2C bus. Now IP correctly tracks the bus 538 * state. BB-bit value is valid. 539 */ 540 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF)) 541 break; 542 543 /* 544 * Otherwise, we must look signals on the bus to make 545 * the right decision. 546 */ 547 systest = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); 548 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) && 549 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) { 550 if (!bus_free) { 551 bus_free_timeout = jiffies + 552 OMAP_I2C_BUS_FREE_TIMEOUT; 553 bus_free = 1; 554 } 555 556 /* 557 * SDA and SCL lines was high for 10 ms without bus 558 * activity detected. The bus is free. Consider 559 * BB-bit value is valid. 560 */ 561 if (time_after(jiffies, bus_free_timeout)) 562 break; 563 } else { 564 bus_free = 0; 565 } 566 567 if (time_after(jiffies, timeout)) { 568 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 569 return -ETIMEDOUT; 570 } 571 572 msleep(1); 573 } 574 575 dev->bb_valid = 1; 576 return 0; 577 } 578 579 static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) 580 { 581 u16 buf; 582 583 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO) 584 return; 585 586 /* 587 * Set up notification threshold based on message size. We're doing 588 * this to try and avoid draining feature as much as possible. Whenever 589 * we have big messages to transfer (bigger than our total fifo size) 590 * then we might use draining feature to transfer the remaining bytes. 591 */ 592 593 dev->threshold = clamp(size, (u8) 1, dev->fifo_size); 594 595 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); 596 597 if (is_rx) { 598 /* Clear RX Threshold */ 599 buf &= ~(0x3f << 8); 600 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; 601 } else { 602 /* Clear TX Threshold */ 603 buf &= ~0x3f; 604 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; 605 } 606 607 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); 608 609 if (dev->rev < OMAP_I2C_REV_ON_3630) 610 dev->b_hw = 1; /* Enable hardware fixes */ 611 612 /* calculate wakeup latency constraint for MPU */ 613 if (dev->set_mpu_wkup_lat != NULL) 614 dev->latency = (1000000 * dev->threshold) / 615 (1000 * dev->speed / 8); 616 } 617 618 /* 619 * Low level master read/write transaction. 620 */ 621 static int omap_i2c_xfer_msg(struct i2c_adapter *adap, 622 struct i2c_msg *msg, int stop) 623 { 624 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 625 unsigned long timeout; 626 u16 w; 627 628 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 629 msg->addr, msg->len, msg->flags, stop); 630 631 if (msg->len == 0) 632 return -EINVAL; 633 634 dev->receiver = !!(msg->flags & I2C_M_RD); 635 omap_i2c_resize_fifo(dev, msg->len, dev->receiver); 636 637 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); 638 639 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ 640 dev->buf = msg->buf; 641 dev->buf_len = msg->len; 642 643 /* make sure writes to dev->buf_len are ordered */ 644 barrier(); 645 646 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); 647 648 /* Clear the FIFO Buffers */ 649 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); 650 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; 651 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); 652 653 reinit_completion(&dev->cmd_complete); 654 dev->cmd_err = 0; 655 656 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; 657 658 /* High speed configuration */ 659 if (dev->speed > 400) 660 w |= OMAP_I2C_CON_OPMODE_HS; 661 662 if (msg->flags & I2C_M_STOP) 663 stop = 1; 664 if (msg->flags & I2C_M_TEN) 665 w |= OMAP_I2C_CON_XA; 666 if (!(msg->flags & I2C_M_RD)) 667 w |= OMAP_I2C_CON_TRX; 668 669 if (!dev->b_hw && stop) 670 w |= OMAP_I2C_CON_STP; 671 /* 672 * NOTE: STAT_BB bit could became 1 here if another master occupy 673 * the bus. IP successfully complete transfer when the bus will be 674 * free again (BB reset to 0). 675 */ 676 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 677 678 /* 679 * Don't write stt and stp together on some hardware. 680 */ 681 if (dev->b_hw && stop) { 682 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; 683 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 684 while (con & OMAP_I2C_CON_STT) { 685 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 686 687 /* Let the user know if i2c is in a bad state */ 688 if (time_after(jiffies, delay)) { 689 dev_err(dev->dev, "controller timed out " 690 "waiting for start condition to finish\n"); 691 return -ETIMEDOUT; 692 } 693 cpu_relax(); 694 } 695 696 w |= OMAP_I2C_CON_STP; 697 w &= ~OMAP_I2C_CON_STT; 698 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 699 } 700 701 /* 702 * REVISIT: We should abort the transfer on signals, but the bus goes 703 * into arbitration and we're currently unable to recover from it. 704 */ 705 timeout = wait_for_completion_timeout(&dev->cmd_complete, 706 OMAP_I2C_TIMEOUT); 707 if (timeout == 0) { 708 dev_err(dev->dev, "controller timed out\n"); 709 omap_i2c_reset(dev); 710 __omap_i2c_init(dev); 711 return -ETIMEDOUT; 712 } 713 714 if (likely(!dev->cmd_err)) 715 return 0; 716 717 /* We have an error */ 718 if (dev->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) { 719 omap_i2c_reset(dev); 720 __omap_i2c_init(dev); 721 return -EIO; 722 } 723 724 if (dev->cmd_err & OMAP_I2C_STAT_AL) 725 return -EAGAIN; 726 727 if (dev->cmd_err & OMAP_I2C_STAT_NACK) { 728 if (msg->flags & I2C_M_IGNORE_NAK) 729 return 0; 730 731 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 732 w |= OMAP_I2C_CON_STP; 733 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 734 return -EREMOTEIO; 735 } 736 return -EIO; 737 } 738 739 740 /* 741 * Prepare controller for a transaction and call omap_i2c_xfer_msg 742 * to do the work during IRQ processing. 743 */ 744 static int 745 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 746 { 747 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 748 int i; 749 int r; 750 751 r = pm_runtime_get_sync(dev->dev); 752 if (r < 0) 753 goto out; 754 755 r = omap_i2c_wait_for_bb_valid(dev); 756 if (r < 0) 757 goto out; 758 759 r = omap_i2c_wait_for_bb(dev); 760 if (r < 0) 761 goto out; 762 763 if (dev->set_mpu_wkup_lat != NULL) 764 dev->set_mpu_wkup_lat(dev->dev, dev->latency); 765 766 for (i = 0; i < num; i++) { 767 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); 768 if (r != 0) 769 break; 770 } 771 772 if (r == 0) 773 r = num; 774 775 omap_i2c_wait_for_bb(dev); 776 777 if (dev->set_mpu_wkup_lat != NULL) 778 dev->set_mpu_wkup_lat(dev->dev, -1); 779 780 out: 781 pm_runtime_mark_last_busy(dev->dev); 782 pm_runtime_put_autosuspend(dev->dev); 783 return r; 784 } 785 786 static u32 787 omap_i2c_func(struct i2c_adapter *adap) 788 { 789 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 790 I2C_FUNC_PROTOCOL_MANGLING; 791 } 792 793 static inline void 794 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) 795 { 796 dev->cmd_err |= err; 797 complete(&dev->cmd_complete); 798 } 799 800 static inline void 801 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) 802 { 803 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); 804 } 805 806 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) 807 { 808 /* 809 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) 810 * Not applicable for OMAP4. 811 * Under certain rare conditions, RDR could be set again 812 * when the bus is busy, then ignore the interrupt and 813 * clear the interrupt. 814 */ 815 if (stat & OMAP_I2C_STAT_RDR) { 816 /* Step 1: If RDR is set, clear it */ 817 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 818 819 /* Step 2: */ 820 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) 821 & OMAP_I2C_STAT_BB)) { 822 823 /* Step 3: */ 824 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) 825 & OMAP_I2C_STAT_RDR) { 826 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 827 dev_dbg(dev->dev, "RDR when bus is busy.\n"); 828 } 829 830 } 831 } 832 } 833 834 /* rev1 devices are apparently only on some 15xx */ 835 #ifdef CONFIG_ARCH_OMAP15XX 836 837 static irqreturn_t 838 omap_i2c_omap1_isr(int this_irq, void *dev_id) 839 { 840 struct omap_i2c_dev *dev = dev_id; 841 u16 iv, w; 842 843 if (pm_runtime_suspended(dev->dev)) 844 return IRQ_NONE; 845 846 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); 847 switch (iv) { 848 case 0x00: /* None */ 849 break; 850 case 0x01: /* Arbitration lost */ 851 dev_err(dev->dev, "Arbitration lost\n"); 852 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); 853 break; 854 case 0x02: /* No acknowledgement */ 855 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); 856 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); 857 break; 858 case 0x03: /* Register access ready */ 859 omap_i2c_complete_cmd(dev, 0); 860 break; 861 case 0x04: /* Receive data ready */ 862 if (dev->buf_len) { 863 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 864 *dev->buf++ = w; 865 dev->buf_len--; 866 if (dev->buf_len) { 867 *dev->buf++ = w >> 8; 868 dev->buf_len--; 869 } 870 } else 871 dev_err(dev->dev, "RRDY IRQ while no data requested\n"); 872 break; 873 case 0x05: /* Transmit data ready */ 874 if (dev->buf_len) { 875 w = *dev->buf++; 876 dev->buf_len--; 877 if (dev->buf_len) { 878 w |= *dev->buf++ << 8; 879 dev->buf_len--; 880 } 881 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 882 } else 883 dev_err(dev->dev, "XRDY IRQ while no data to send\n"); 884 break; 885 default: 886 return IRQ_NONE; 887 } 888 889 return IRQ_HANDLED; 890 } 891 #else 892 #define omap_i2c_omap1_isr NULL 893 #endif 894 895 /* 896 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing 897 * data to DATA_REG. Otherwise some data bytes can be lost while transferring 898 * them from the memory to the I2C interface. 899 */ 900 static int errata_omap3_i462(struct omap_i2c_dev *dev) 901 { 902 unsigned long timeout = 10000; 903 u16 stat; 904 905 do { 906 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 907 if (stat & OMAP_I2C_STAT_XUDF) 908 break; 909 910 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { 911 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY | 912 OMAP_I2C_STAT_XDR)); 913 if (stat & OMAP_I2C_STAT_NACK) { 914 dev->cmd_err |= OMAP_I2C_STAT_NACK; 915 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); 916 } 917 918 if (stat & OMAP_I2C_STAT_AL) { 919 dev_err(dev->dev, "Arbitration lost\n"); 920 dev->cmd_err |= OMAP_I2C_STAT_AL; 921 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); 922 } 923 924 return -EIO; 925 } 926 927 cpu_relax(); 928 } while (--timeout); 929 930 if (!timeout) { 931 dev_err(dev->dev, "timeout waiting on XUDF bit\n"); 932 return 0; 933 } 934 935 return 0; 936 } 937 938 static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes, 939 bool is_rdr) 940 { 941 u16 w; 942 943 while (num_bytes--) { 944 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 945 *dev->buf++ = w; 946 dev->buf_len--; 947 948 /* 949 * Data reg in 2430, omap3 and 950 * omap4 is 8 bit wide 951 */ 952 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { 953 *dev->buf++ = w >> 8; 954 dev->buf_len--; 955 } 956 } 957 } 958 959 static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes, 960 bool is_xdr) 961 { 962 u16 w; 963 964 while (num_bytes--) { 965 w = *dev->buf++; 966 dev->buf_len--; 967 968 /* 969 * Data reg in 2430, omap3 and 970 * omap4 is 8 bit wide 971 */ 972 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { 973 w |= *dev->buf++ << 8; 974 dev->buf_len--; 975 } 976 977 if (dev->errata & I2C_OMAP_ERRATA_I462) { 978 int ret; 979 980 ret = errata_omap3_i462(dev); 981 if (ret < 0) 982 return ret; 983 } 984 985 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 986 } 987 988 return 0; 989 } 990 991 static irqreturn_t 992 omap_i2c_isr(int irq, void *dev_id) 993 { 994 struct omap_i2c_dev *dev = dev_id; 995 irqreturn_t ret = IRQ_HANDLED; 996 u16 mask; 997 u16 stat; 998 999 spin_lock(&dev->lock); 1000 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 1001 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 1002 1003 if (stat & mask) 1004 ret = IRQ_WAKE_THREAD; 1005 1006 spin_unlock(&dev->lock); 1007 1008 return ret; 1009 } 1010 1011 static irqreturn_t 1012 omap_i2c_isr_thread(int this_irq, void *dev_id) 1013 { 1014 struct omap_i2c_dev *dev = dev_id; 1015 unsigned long flags; 1016 u16 bits; 1017 u16 stat; 1018 int err = 0, count = 0; 1019 1020 spin_lock_irqsave(&dev->lock, flags); 1021 do { 1022 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 1023 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 1024 stat &= bits; 1025 1026 /* If we're in receiver mode, ignore XDR/XRDY */ 1027 if (dev->receiver) 1028 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); 1029 else 1030 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); 1031 1032 if (!stat) { 1033 /* my work here is done */ 1034 goto out; 1035 } 1036 1037 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); 1038 if (count++ == 100) { 1039 dev_warn(dev->dev, "Too much work in one IRQ\n"); 1040 break; 1041 } 1042 1043 if (stat & OMAP_I2C_STAT_NACK) { 1044 err |= OMAP_I2C_STAT_NACK; 1045 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); 1046 } 1047 1048 if (stat & OMAP_I2C_STAT_AL) { 1049 dev_err(dev->dev, "Arbitration lost\n"); 1050 err |= OMAP_I2C_STAT_AL; 1051 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); 1052 } 1053 1054 /* 1055 * ProDB0017052: Clear ARDY bit twice 1056 */ 1057 if (stat & OMAP_I2C_STAT_ARDY) 1058 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY); 1059 1060 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | 1061 OMAP_I2C_STAT_AL)) { 1062 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY | 1063 OMAP_I2C_STAT_RDR | 1064 OMAP_I2C_STAT_XRDY | 1065 OMAP_I2C_STAT_XDR | 1066 OMAP_I2C_STAT_ARDY)); 1067 break; 1068 } 1069 1070 if (stat & OMAP_I2C_STAT_RDR) { 1071 u8 num_bytes = 1; 1072 1073 if (dev->fifo_size) 1074 num_bytes = dev->buf_len; 1075 1076 if (dev->errata & I2C_OMAP_ERRATA_I207) { 1077 i2c_omap_errata_i207(dev, stat); 1078 num_bytes = (omap_i2c_read_reg(dev, 1079 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F; 1080 } 1081 1082 omap_i2c_receive_data(dev, num_bytes, true); 1083 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 1084 continue; 1085 } 1086 1087 if (stat & OMAP_I2C_STAT_RRDY) { 1088 u8 num_bytes = 1; 1089 1090 if (dev->threshold) 1091 num_bytes = dev->threshold; 1092 1093 omap_i2c_receive_data(dev, num_bytes, false); 1094 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY); 1095 continue; 1096 } 1097 1098 if (stat & OMAP_I2C_STAT_XDR) { 1099 u8 num_bytes = 1; 1100 int ret; 1101 1102 if (dev->fifo_size) 1103 num_bytes = dev->buf_len; 1104 1105 ret = omap_i2c_transmit_data(dev, num_bytes, true); 1106 if (ret < 0) 1107 break; 1108 1109 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR); 1110 continue; 1111 } 1112 1113 if (stat & OMAP_I2C_STAT_XRDY) { 1114 u8 num_bytes = 1; 1115 int ret; 1116 1117 if (dev->threshold) 1118 num_bytes = dev->threshold; 1119 1120 ret = omap_i2c_transmit_data(dev, num_bytes, false); 1121 if (ret < 0) 1122 break; 1123 1124 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY); 1125 continue; 1126 } 1127 1128 if (stat & OMAP_I2C_STAT_ROVR) { 1129 dev_err(dev->dev, "Receive overrun\n"); 1130 err |= OMAP_I2C_STAT_ROVR; 1131 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR); 1132 break; 1133 } 1134 1135 if (stat & OMAP_I2C_STAT_XUDF) { 1136 dev_err(dev->dev, "Transmit underflow\n"); 1137 err |= OMAP_I2C_STAT_XUDF; 1138 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF); 1139 break; 1140 } 1141 } while (stat); 1142 1143 omap_i2c_complete_cmd(dev, err); 1144 1145 out: 1146 spin_unlock_irqrestore(&dev->lock, flags); 1147 1148 return IRQ_HANDLED; 1149 } 1150 1151 static const struct i2c_algorithm omap_i2c_algo = { 1152 .master_xfer = omap_i2c_xfer, 1153 .functionality = omap_i2c_func, 1154 }; 1155 1156 #ifdef CONFIG_OF 1157 static struct omap_i2c_bus_platform_data omap2420_pdata = { 1158 .rev = OMAP_I2C_IP_VERSION_1, 1159 .flags = OMAP_I2C_FLAG_NO_FIFO | 1160 OMAP_I2C_FLAG_SIMPLE_CLOCK | 1161 OMAP_I2C_FLAG_16BIT_DATA_REG | 1162 OMAP_I2C_FLAG_BUS_SHIFT_2, 1163 }; 1164 1165 static struct omap_i2c_bus_platform_data omap2430_pdata = { 1166 .rev = OMAP_I2C_IP_VERSION_1, 1167 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | 1168 OMAP_I2C_FLAG_FORCE_19200_INT_CLK, 1169 }; 1170 1171 static struct omap_i2c_bus_platform_data omap3_pdata = { 1172 .rev = OMAP_I2C_IP_VERSION_1, 1173 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 1174 }; 1175 1176 static struct omap_i2c_bus_platform_data omap4_pdata = { 1177 .rev = OMAP_I2C_IP_VERSION_2, 1178 }; 1179 1180 static const struct of_device_id omap_i2c_of_match[] = { 1181 { 1182 .compatible = "ti,omap4-i2c", 1183 .data = &omap4_pdata, 1184 }, 1185 { 1186 .compatible = "ti,omap3-i2c", 1187 .data = &omap3_pdata, 1188 }, 1189 { 1190 .compatible = "ti,omap2430-i2c", 1191 .data = &omap2430_pdata, 1192 }, 1193 { 1194 .compatible = "ti,omap2420-i2c", 1195 .data = &omap2420_pdata, 1196 }, 1197 { }, 1198 }; 1199 MODULE_DEVICE_TABLE(of, omap_i2c_of_match); 1200 #endif 1201 1202 #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14) 1203 1204 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4) 1205 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf) 1206 1207 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7) 1208 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f) 1209 #define OMAP_I2C_SCHEME_0 0 1210 #define OMAP_I2C_SCHEME_1 1 1211 1212 static int 1213 omap_i2c_probe(struct platform_device *pdev) 1214 { 1215 struct omap_i2c_dev *dev; 1216 struct i2c_adapter *adap; 1217 struct resource *mem; 1218 const struct omap_i2c_bus_platform_data *pdata = 1219 dev_get_platdata(&pdev->dev); 1220 struct device_node *node = pdev->dev.of_node; 1221 const struct of_device_id *match; 1222 int irq; 1223 int r; 1224 u32 rev; 1225 u16 minor, major; 1226 1227 irq = platform_get_irq(pdev, 0); 1228 if (irq < 0) { 1229 dev_err(&pdev->dev, "no irq resource?\n"); 1230 return irq; 1231 } 1232 1233 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); 1234 if (!dev) 1235 return -ENOMEM; 1236 1237 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1238 dev->base = devm_ioremap_resource(&pdev->dev, mem); 1239 if (IS_ERR(dev->base)) 1240 return PTR_ERR(dev->base); 1241 1242 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); 1243 if (match) { 1244 u32 freq = 100000; /* default to 100000 Hz */ 1245 1246 pdata = match->data; 1247 dev->flags = pdata->flags; 1248 1249 of_property_read_u32(node, "clock-frequency", &freq); 1250 /* convert DT freq value in Hz into kHz for speed */ 1251 dev->speed = freq / 1000; 1252 } else if (pdata != NULL) { 1253 dev->speed = pdata->clkrate; 1254 dev->flags = pdata->flags; 1255 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; 1256 } 1257 1258 dev->dev = &pdev->dev; 1259 dev->irq = irq; 1260 1261 spin_lock_init(&dev->lock); 1262 1263 platform_set_drvdata(pdev, dev); 1264 init_completion(&dev->cmd_complete); 1265 1266 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; 1267 1268 pm_runtime_enable(dev->dev); 1269 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT); 1270 pm_runtime_use_autosuspend(dev->dev); 1271 1272 r = pm_runtime_get_sync(dev->dev); 1273 if (r < 0) 1274 goto err_free_mem; 1275 1276 /* 1277 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. 1278 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. 1279 * Also since the omap_i2c_read_reg uses reg_map_ip_* a 1280 * readw_relaxed is done. 1281 */ 1282 rev = readw_relaxed(dev->base + 0x04); 1283 1284 dev->scheme = OMAP_I2C_SCHEME(rev); 1285 switch (dev->scheme) { 1286 case OMAP_I2C_SCHEME_0: 1287 dev->regs = (u8 *)reg_map_ip_v1; 1288 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG); 1289 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); 1290 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); 1291 break; 1292 case OMAP_I2C_SCHEME_1: 1293 /* FALLTHROUGH */ 1294 default: 1295 dev->regs = (u8 *)reg_map_ip_v2; 1296 rev = (rev << 16) | 1297 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO); 1298 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev); 1299 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev); 1300 dev->rev = rev; 1301 } 1302 1303 dev->errata = 0; 1304 1305 if (dev->rev >= OMAP_I2C_REV_ON_2430 && 1306 dev->rev < OMAP_I2C_REV_ON_4430_PLUS) 1307 dev->errata |= I2C_OMAP_ERRATA_I207; 1308 1309 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) 1310 dev->errata |= I2C_OMAP_ERRATA_I462; 1311 1312 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { 1313 u16 s; 1314 1315 /* Set up the fifo size - Get total size */ 1316 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; 1317 dev->fifo_size = 0x8 << s; 1318 1319 /* 1320 * Set up notification threshold as half the total available 1321 * size. This is to ensure that we can handle the status on int 1322 * call back latencies. 1323 */ 1324 1325 dev->fifo_size = (dev->fifo_size / 2); 1326 1327 if (dev->rev < OMAP_I2C_REV_ON_3630) 1328 dev->b_hw = 1; /* Enable hardware fixes */ 1329 1330 /* calculate wakeup latency constraint for MPU */ 1331 if (dev->set_mpu_wkup_lat != NULL) 1332 dev->latency = (1000000 * dev->fifo_size) / 1333 (1000 * dev->speed / 8); 1334 } 1335 1336 /* reset ASAP, clearing any IRQs */ 1337 omap_i2c_init(dev); 1338 1339 if (dev->rev < OMAP_I2C_OMAP1_REV_2) 1340 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr, 1341 IRQF_NO_SUSPEND, pdev->name, dev); 1342 else 1343 r = devm_request_threaded_irq(&pdev->dev, dev->irq, 1344 omap_i2c_isr, omap_i2c_isr_thread, 1345 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1346 pdev->name, dev); 1347 1348 if (r) { 1349 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); 1350 goto err_unuse_clocks; 1351 } 1352 1353 adap = &dev->adapter; 1354 i2c_set_adapdata(adap, dev); 1355 adap->owner = THIS_MODULE; 1356 adap->class = I2C_CLASS_DEPRECATED; 1357 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); 1358 adap->algo = &omap_i2c_algo; 1359 adap->dev.parent = &pdev->dev; 1360 adap->dev.of_node = pdev->dev.of_node; 1361 1362 /* i2c device drivers may be active on return from add_adapter() */ 1363 adap->nr = pdev->id; 1364 r = i2c_add_numbered_adapter(adap); 1365 if (r) { 1366 dev_err(dev->dev, "failure adding adapter\n"); 1367 goto err_unuse_clocks; 1368 } 1369 1370 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr, 1371 major, minor, dev->speed); 1372 1373 pm_runtime_mark_last_busy(dev->dev); 1374 pm_runtime_put_autosuspend(dev->dev); 1375 1376 return 0; 1377 1378 err_unuse_clocks: 1379 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1380 pm_runtime_put(dev->dev); 1381 pm_runtime_disable(&pdev->dev); 1382 err_free_mem: 1383 1384 return r; 1385 } 1386 1387 static int omap_i2c_remove(struct platform_device *pdev) 1388 { 1389 struct omap_i2c_dev *dev = platform_get_drvdata(pdev); 1390 int ret; 1391 1392 i2c_del_adapter(&dev->adapter); 1393 ret = pm_runtime_get_sync(&pdev->dev); 1394 if (ret < 0) 1395 return ret; 1396 1397 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1398 pm_runtime_put(&pdev->dev); 1399 pm_runtime_disable(&pdev->dev); 1400 return 0; 1401 } 1402 1403 #ifdef CONFIG_PM 1404 static int omap_i2c_runtime_suspend(struct device *dev) 1405 { 1406 struct platform_device *pdev = to_platform_device(dev); 1407 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1408 1409 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); 1410 1411 if (_dev->scheme == OMAP_I2C_SCHEME_0) 1412 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); 1413 else 1414 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1415 OMAP_I2C_IP_V2_INTERRUPTS_MASK); 1416 1417 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { 1418 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ 1419 } else { 1420 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); 1421 1422 /* Flush posted write */ 1423 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); 1424 } 1425 1426 return 0; 1427 } 1428 1429 static int omap_i2c_runtime_resume(struct device *dev) 1430 { 1431 struct platform_device *pdev = to_platform_device(dev); 1432 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1433 1434 if (!_dev->regs) 1435 return 0; 1436 1437 __omap_i2c_init(_dev); 1438 1439 return 0; 1440 } 1441 1442 static struct dev_pm_ops omap_i2c_pm_ops = { 1443 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, 1444 omap_i2c_runtime_resume, NULL) 1445 }; 1446 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) 1447 #else 1448 #define OMAP_I2C_PM_OPS NULL 1449 #endif /* CONFIG_PM */ 1450 1451 static struct platform_driver omap_i2c_driver = { 1452 .probe = omap_i2c_probe, 1453 .remove = omap_i2c_remove, 1454 .driver = { 1455 .name = "omap_i2c", 1456 .pm = OMAP_I2C_PM_OPS, 1457 .of_match_table = of_match_ptr(omap_i2c_of_match), 1458 }, 1459 }; 1460 1461 /* I2C may be needed to bring up other drivers */ 1462 static int __init 1463 omap_i2c_init_driver(void) 1464 { 1465 return platform_driver_register(&omap_i2c_driver); 1466 } 1467 subsys_initcall(omap_i2c_init_driver); 1468 1469 static void __exit omap_i2c_exit_driver(void) 1470 { 1471 platform_driver_unregister(&omap_i2c_driver); 1472 } 1473 module_exit(omap_i2c_exit_driver); 1474 1475 MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); 1476 MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); 1477 MODULE_LICENSE("GPL"); 1478 MODULE_ALIAS("platform:omap_i2c"); 1479