1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #include <linux/atomic.h> 3 #include <linux/clk.h> 4 #include <linux/delay.h> 5 #include <linux/device.h> 6 #include <linux/i2c.h> 7 #include <linux/i2c-smbus.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 11 /* Controller command patterns */ 12 #define SW_TWSI_V BIT_ULL(63) /* Valid bit */ 13 #define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */ 14 #define SW_TWSI_R BIT_ULL(56) /* Result or read bit */ 15 #define SW_TWSI_SOVR BIT_ULL(55) /* Size override */ 16 #define SW_TWSI_SIZE_SHIFT 52 17 #define SW_TWSI_ADDR_SHIFT 40 18 #define SW_TWSI_IA_SHIFT 32 /* Internal address */ 19 20 /* Controller opcode word (bits 60:57) */ 21 #define SW_TWSI_OP_SHIFT 57 22 #define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT) 23 #define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT) 24 #define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT) 25 #define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT) 26 #define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT) 27 #define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */ 28 29 /* Controller extended opcode word (bits 34:32) */ 30 #define SW_TWSI_EOP_SHIFT 32 31 #define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT) 32 #define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT) 33 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT) 34 #define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT) 35 #define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT) 36 37 /* Controller command and status bits */ 38 #define TWSI_CTL_CE 0x80 /* High level controller enable */ 39 #define TWSI_CTL_ENAB 0x40 /* Bus enable */ 40 #define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */ 41 #define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */ 42 #define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */ 43 #define TWSI_CTL_AAK 0x04 /* Assert ACK */ 44 45 /* Status values */ 46 #define STAT_BUS_ERROR 0x00 47 #define STAT_START 0x08 48 #define STAT_REP_START 0x10 49 #define STAT_TXADDR_ACK 0x18 50 #define STAT_TXADDR_NAK 0x20 51 #define STAT_TXDATA_ACK 0x28 52 #define STAT_TXDATA_NAK 0x30 53 #define STAT_LOST_ARB_38 0x38 54 #define STAT_RXADDR_ACK 0x40 55 #define STAT_RXADDR_NAK 0x48 56 #define STAT_RXDATA_ACK 0x50 57 #define STAT_RXDATA_NAK 0x58 58 #define STAT_SLAVE_60 0x60 59 #define STAT_LOST_ARB_68 0x68 60 #define STAT_SLAVE_70 0x70 61 #define STAT_LOST_ARB_78 0x78 62 #define STAT_SLAVE_80 0x80 63 #define STAT_SLAVE_88 0x88 64 #define STAT_GENDATA_ACK 0x90 65 #define STAT_GENDATA_NAK 0x98 66 #define STAT_SLAVE_A0 0xA0 67 #define STAT_SLAVE_A8 0xA8 68 #define STAT_LOST_ARB_B0 0xB0 69 #define STAT_SLAVE_LOST 0xB8 70 #define STAT_SLAVE_NAK 0xC0 71 #define STAT_SLAVE_ACK 0xC8 72 #define STAT_AD2W_ACK 0xD0 73 #define STAT_AD2W_NAK 0xD8 74 #define STAT_IDLE 0xF8 75 76 /* TWSI_INT values */ 77 #define TWSI_INT_ST_INT BIT_ULL(0) 78 #define TWSI_INT_TS_INT BIT_ULL(1) 79 #define TWSI_INT_CORE_INT BIT_ULL(2) 80 #define TWSI_INT_ST_EN BIT_ULL(4) 81 #define TWSI_INT_TS_EN BIT_ULL(5) 82 #define TWSI_INT_CORE_EN BIT_ULL(6) 83 #define TWSI_INT_SDA_OVR BIT_ULL(8) 84 #define TWSI_INT_SCL_OVR BIT_ULL(9) 85 #define TWSI_INT_SDA BIT_ULL(10) 86 #define TWSI_INT_SCL BIT_ULL(11) 87 88 #define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */ 89 90 /* Register offsets */ 91 struct octeon_i2c_reg_offset { 92 unsigned int sw_twsi; 93 unsigned int twsi_int; 94 unsigned int sw_twsi_ext; 95 }; 96 97 #define SW_TWSI(x) (x->roff.sw_twsi) 98 #define TWSI_INT(x) (x->roff.twsi_int) 99 #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) 100 101 struct octeon_i2c { 102 wait_queue_head_t queue; 103 struct i2c_adapter adap; 104 struct octeon_i2c_reg_offset roff; 105 struct clk *clk; 106 int irq; 107 int hlc_irq; /* For cn7890 only */ 108 u32 twsi_freq; 109 int sys_freq; 110 void __iomem *twsi_base; 111 struct device *dev; 112 bool hlc_enabled; 113 bool broken_irq_mode; 114 bool broken_irq_check; 115 void (*int_enable)(struct octeon_i2c *); 116 void (*int_disable)(struct octeon_i2c *); 117 void (*hlc_int_enable)(struct octeon_i2c *); 118 void (*hlc_int_disable)(struct octeon_i2c *); 119 atomic_t int_enable_cnt; 120 atomic_t hlc_int_enable_cnt; 121 struct i2c_smbus_alert_setup alert_data; 122 struct i2c_client *ara; 123 }; 124 125 static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr) 126 { 127 __raw_writeq(val, addr); 128 __raw_readq(addr); /* wait for write to land */ 129 } 130 131 /** 132 * octeon_i2c_reg_write - write an I2C core register 133 * @i2c: The struct octeon_i2c 134 * @eop_reg: Register selector 135 * @data: Value to be written 136 * 137 * The I2C core registers are accessed indirectly via the SW_TWSI CSR. 138 */ 139 static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data) 140 { 141 int tries = 1000; 142 u64 tmp; 143 144 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c)); 145 do { 146 tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 147 if (--tries < 0) 148 return; 149 } while ((tmp & SW_TWSI_V) != 0); 150 } 151 152 #define octeon_i2c_ctl_write(i2c, val) \ 153 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val) 154 #define octeon_i2c_data_write(i2c, val) \ 155 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val) 156 157 /** 158 * octeon_i2c_reg_read - read lower bits of an I2C core register 159 * @i2c: The struct octeon_i2c 160 * @eop_reg: Register selector 161 * 162 * Returns the data. 163 * 164 * The I2C core registers are accessed indirectly via the SW_TWSI CSR. 165 */ 166 static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg, 167 int *error) 168 { 169 int tries = 1000; 170 u64 tmp; 171 172 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c)); 173 do { 174 tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 175 if (--tries < 0) { 176 /* signal that the returned data is invalid */ 177 if (error) 178 *error = -EIO; 179 return 0; 180 } 181 } while ((tmp & SW_TWSI_V) != 0); 182 183 return tmp & 0xFF; 184 } 185 186 #define octeon_i2c_ctl_read(i2c) \ 187 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL) 188 #define octeon_i2c_data_read(i2c, error) \ 189 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error) 190 #define octeon_i2c_stat_read(i2c) \ 191 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL) 192 193 /** 194 * octeon_i2c_read_int - read the TWSI_INT register 195 * @i2c: The struct octeon_i2c 196 * 197 * Returns the value of the register. 198 */ 199 static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c) 200 { 201 return __raw_readq(i2c->twsi_base + TWSI_INT(i2c)); 202 } 203 204 /** 205 * octeon_i2c_write_int - write the TWSI_INT register 206 * @i2c: The struct octeon_i2c 207 * @data: Value to be written 208 */ 209 static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) 210 { 211 octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); 212 } 213 214 /* Prototypes */ 215 irqreturn_t octeon_i2c_isr(int irq, void *dev_id); 216 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); 217 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c); 218 void octeon_i2c_set_clock(struct octeon_i2c *i2c); 219 extern struct i2c_bus_recovery_info octeon_i2c_recovery_info; 220